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EK-RX02-UG-001 



RX02 Floppy Disk 

System 

User's Guide 



digital equipment corporation • maynard, massachusetts 



1st Edition, My 1978 



Copyright ® 1978 by Digital Equipment Corporation 

The material in this manual is for informational purposes and is 
subject to change without notice. 

Digital Equipment Corporation assumes no responsibility for any 
errors which may appear in this manual. 



Printed in U.S.A. 



This document was set on DIGITAL'S DECset-8000 computerized 
typesetting system. 



The following are trademarks of Digital Equipment Corporation, 
Maynard, Massachusetts: 



DIGITAL 


DEC system- 10 


MASSBUS 


DEC 


DECSYSTEM-20 


OMNIBUS 


PDF 


DIBOL 


OS/8 


DECUS 


EDUSYSTEM 


RSTS 


UNIBUS 


VAX 


RSX 




VMS 


IAS 



CONTENTS 



Page 
PREFACE 

CHAPTER 1 GENERAL INFORMATION 

1.1 INTRODUCTION 1-1 

1.2 GENERAL DESCRIPTION 1-2 

1.2.1 Interface Modules 1-2 

1.2.2 Microprogrammed Controller 1-5 

1.2.3 Read/Write Electronics 1-5 

1.2.4 Electromechanical Drive 1-5 

1.2.5 Power Supply 1-6 

1.3 OPTION DESCRIPTION 1-6 

1.3.1 Operation For Single Density Recording Only (RX8E, RXl 1, 

RXVll) 1-7 

1.3.1.1 PDP-8 Operation 1-7 

1.3.1.2 PDP-11 Operation 1-7 

1.3.1.3 LSI- 11 Operation 1-7 

1.3.2 Operation For Single or Double Density Recording (RX28, 
RX211,RXV21) 1-7 

1.3.2.1 PDP-8 Operation 1-7 

1.3.2.2 PDP-11 Operation 1-7 

1.3.2.3 LSI- 11 Operation 1-7 

1.4 SPECIFICATIONS 1-7 

1.5 SYSTEMS COMPATIBILITY 1-9 

1.5.1 Media 1-9 

1.5.2 Recording Scheme ! 1-10 

1.5.2.1 Double Frequency (FM) 1-10 

1.5.2.2 Miller Code (MFM) 1-10 

1.5.3 Logical Format 1-12 

1.5.3.1 Header Field Description 1-12 

1.5.3.2 Data Field Description 1-13 

1.5.3.3 Track Usage 1-13 

1.5.3.4 CRC Capability 1-13 

CHAPTER 2 INSTALLATION 

2.1 SITE PREPARATION 2-1 

2.1.1 Space 2-1 

2.1.2 Cabling 2-2 

2.1.3 AC Power 2-2 

2.1.3.1 Power Requirements 2-2 



m 



CONTENTS (Cont) 



Page 



2.1.3.2 

2.1.4 

2.2 

2.3 

2.3.1 

2.3.2 

2.3.3 

2.3.4 

2.3.5 

2.4 

2.4.1 

2.4.2 

2.4.3 

2.4.3.1 

2.4.3.2 

2.4.3.3 

2.5 

2.5.1 

2.6 

CHAPTER 3 

3.1 

3.2 

3.2.1 

3.2.2 

3.2.2.1 

3.2.2.2 

3.2.3 

3.3 

3.4 

CHAPTER 4 

4.1 

4.1.1 

4.1.2 

4.1.2.1 

4.1.2.2 

4.1.2.3 

4.1.2.4 

4.1.2.5 

4.1.2.6 

4.1.2.7 

4.1.2.8 



Input Power Modification Requirements 2-3 

Fire and Safety Precautions 2-3 

CONFIGURATION GUIDELINES 2-3 

ENVIRONMENTAL CONSIDERATIONS 2-4 

General 2-4 

Temperature, Relative Humidity 2-4 

Heat Dissipation 2-5 

Radiated Emissions 2-5 

Cleanliness 2-5 

UNPACKING AND INSPECTION 2-5 

General 2-5 

Tools 2-6 

Unpacking 2-6 

Cabinet-Mounted 2-6 

Separate Container 2-6 

Inspection 2-8 

INSTALLATION 2-8 

PDP8-A Modification 2-10 

TESTING 2-10 

USER INFORMATION 

CUSTOMER RESPONSIBILITY 3-1 

CARE OF MEDIA 3-1 

Handling Practices and Precautions 3-1 

Diskette Storage 3-2 

Short Term (Available for Immediate Use) 3-2 

Long Term 3-2 

Shipping Diskettes 3-2 

OPERATING INSTRUCTIONS 3-3 

OPERATOR TROUBLESHOOTING 3-3 

PROGRAMMING 

RX8E AND RX28 Programming Information 4-1 

Device Codes 4-1 

Instruction Set 4-2 

RX8E Load Command (LCD) 4-2 

RX28 Load Command 4-3 

Transfer Data Register (XDR) 4-3 

STR 4-3 

SER 4-4 

SDN 4-4 

INTR 4-4 

INIT 4-4 



IV 



CONTENTS (Cont) 



Page 

4.1.3 Register Description 4-4 

4.1.3.1 Command Register 4-4 

4.1.3.2 Error Code Register 4-5 

4.1.3.3 RX2TA - RX Track Address 4-6 

4.1.3.4 RX2SA - RX Sector Address 4-6 

4.1.3.5 RX2DB - RX Data Buffer 4-6 

4.1.3.6 RX8E - RX Error and Status 4-6 

4.1.3.7 RX28 - RX Error and Status 4-7 

4.1.4 Function Code Description 4-8 

4.1.4.1 Fill Buffer (000) 4-9 

4.1.4.2 Empty Buffer (001) 4-9 

4.1.4.3 Write Sector (010) 4-9 

4.1.4.4 Read Sector (Oil) 4-10 

4.1.4.5 Set Media Density (100) for RX28 only 4-10 

4.1.4.6 Maintenance Read Status (101) for RX28 only 4-10 

4.1.4.7 Read Status (101) for RX8E only 4-10 

4.1.4.8 Write Deleted Data Sector (110) 4-11 

4.1.4.9 Read Error Code Function (111) 4-11 

4.1.4.10 Power Fail 4-11 

4.1.5 Error Recovery 4-1 1 

4.1.5.1 RX8E : 4-11 

4.1.5.2 RX28 4-12 

4.1.6 RX8E Programming Examples 4-13 

4.1.6.1 Write/Write Deleted Data/Read Functions 4-13 

4.1.6.2 Empty Buffer Function 4-13 

4.1.6.3 Fill Buffer Function 4-13 

4.1.7 RX28 Programming Examples 4-17 

4.1.8 Restrictions and Programming Pitfalls 4-22 

4.2 RXl 1 AND RXVl 1 PROGRAMMING INFORMATION 4-23 

4.2.1 Register and Vector Addresses 4-23 

4.2.2 Register Description 4-24 

4.2.2.1 RXCS- Command and Status (177170) 4-24 

4.2.2.2 RXDB- Data Buffer Register (177172) 4-25 

4.2.2.3 RXTA - RX Track Address 4-25 

4.2.2.4 RXSA - RX Sector Address 4-25 

4.2.2.5 RXDB - RX Data Buffer 4-25 

4.2.2.6 RXES - RX Error and Status 4-26 

4.2.3 Function Codes 4-27 

4.2.3.1 Fill Buffer (000) 4-27 

4.2.3.2 Empty Buffer (001) 4-27 

4.2.3.3 Write Sector (010) 4-28 

4.2.3.4 Read Sector (Oil) 4-28 

4.2.3.5 Read Status (101) 4-29 

4.2.3.6 Write Sector with Deleted Data (1 10) 4-29 

4.2.3.7 Read Error Code Function (1 1 1) 4-29 



CONTENTS (Cont) 



Page 

4.2.3.8 Power Fail 4-29 

4.2.4 Programming Examples 4-30 

4.2.4.1 Read Data/Write Data 4-30 

4.2.4.2 Empty Buffer Function 4-30 

4.2.4.3 Fill Buffer Function 4-30 

4.2.5 Restrictions and Programming Pitfalls 4-30 

4.2.6 Error Recovery 4-34 

4.3 RX21 1 AND RXV21 PROGRAMMING INFORMATION 4-34 

4.3.1 Register and Vector Addresses 4-35 

4.3.2 Register Description 4-35 

4.3.2.1 RX2CS- Command and Status (177 170) 4-35 

4.3.2.2 RX2DB- Data Buffer Register (177 172) 4-36 

4.3.2.3 RX2TA - RX Track Address 4-37 

4.3.2.4 RX2SA - RX Sector Address 4-37 

4.3.2.5 RX2WC - RX Word Count Register 4-37 

4.3.2.6 RX2BA - RX Bus Address Register 4-37 

4.3.2.7 RX2DB - RX Data Buffer 4-37 

4.3.2.8 RX2ES - RX Error and Status 4-38 

4.3.3 Function Codes 4-39 

4.3.3.1 Fill Buffer (000) 4-39 

4.3.3.2 Empty Buffer (001) 4-39 

4.3.3.3 Write Sector (010) 4-39 

4.3.3.4 Read Sector (Oil) 4-40 

4.3.3.5 Set Media Density (100) 4-41 

4.3.3.6 Maintenance Read Status (101) 4-41 

4.3.3.7 Write Sector with Deleted Data (110) 4-41 

4.3.3.8 Read Error Code (111) 4-41 

4.3.3.9 RX02 Power Fail 4-42 

4.3.4 Error Recovery 4-43 

4.3.5 RX21 1/RXV21 Programming Examples 4-43 

4.3.5.1 Write/Fill Buffer 4-43 

4.3.5.2 Read/Empty Buffer 4-45 



FIGURES 



Figure No. Title Page 

1-1 Floppy Disk Configuration 1-3 

1-2 Front View of the Floppy Disk System 1-3 

1-3 Interface Modules 1-4 

1-4 TopViewofRX02 1-5 



VI 



FIGURES (Cont) 



Figure No. Title Page 

1-5 Underside View of Drive 1-6 

1-6 Diskette Media 1-9 

1-7 Flux Reversal Patterns for FM 1-10 

1-8 FM versus MFM Encoding 1-1 1 

1-9 Track Format (Each Track) 1-12 

1-10 Sector Format (Each Sector) 1-12 

2-1 RX02 Outline Dimensions 2-1 

2-2 Cabinet Layout Dimensions 2-2 

2-3 RX02 Rear View 2-3 

2-4 RX02 Unpacking 2-7 

2-5 RX02 Cabinet Mounting Information 2-7 

2-6 KM8-A Modification 2-10 

4-1 LCD Word Format (RX8E) 4-2 

4-2 Command Word Format (RX28) 4-3 

4-3 Command Register Format (RX8E) 4-4 

4-4 Command Register Format (RX28) 4-4 

4-5 Error Code Register Format (RX8E/RX28A) 4-5 

4-6 RX2TA Format (RX8E/RX28A) 4-6 

4-7 RX2SA Format (RX8E/RX28) 4-6 

4-8 RX2DB Format (RX8E/RX28) 4-7 

4-9 RXES Format (RX8E) 4-7 

4-10 RX2ES Format (RX28) 4-8 

4-11 RX8EWrite/Write Deleted Data/ Read Example 4-15 

4-12 RX8E Empty Buffer Example 4-17 

4-13 RX8E Fill Buffer Example 4-18 

4-14 RX28 Write/Write Deleted Data/Read Example 4-19 

4-15 RX28 Fill Buffer Example 4-21 

4-16 RX28 Empty Buffer Example 4-22 

4-17 RXCS Format (RXll/RXV 11) 4-25 

4-18 RXTA Format (RXll/RXVll) 4-26 

4-19 RXSA Format (RXll/RXVll) 4-26 

4-20 RXDB Format (RXll/RXVll) 4-26 

4-21 RXES Format (RXll/RXVll) 4-27 

4-22 RXl 1/RXVl 1 Write/Write Deleted Data/Read Example 4-32 

4-23 RXll/RXVll Empty Buffer Example 4-33 

4-24 RXl 1/RXVl 1 Fill Buffer Example 4-34 

4-25 RX2CS Format (RX211/RXV21) 4-36 

4-26 RX2TA Format (RX211/RXV21) 4-38 

4-27 RX2SA Format (RX211/RXV21) 4-38 

4-28 RX2WC Format (RX21 1/RXV21) 4-38 

4-29 RX2BA and RX2DB Format (RX211/RXV21) 4-38 

4-30 RX2ES Format (RX211/RXV21) 4-39 

4-31 RX211/RXV21 Write/Fill Buffer Example 4-45 

4-32 RX21 1/RXV21 Read/Empty Buffer Example 4-46 



vii 



TABLES 



Table No. Title Page 

1-1 Data Address Mark Code , 1-13 

2-1 RX02 Configurations 2-4 

2-2 Controller Configuration Switch Positions 2-4 

2-3 Interface Code/Jumper Configuration 2-9 

3-1 Operator Troubleshooting Guide 3-3 

4-1 Device Code Switch Selection 4-2 



vni 



PREFACE 



This manual is intended to provide the user with sufficient information to correctly set up and operate 
the RX02 Floppy Disk System in any of the various configurations that are available for use with the 
PDP-8, PDP-1 1, or LSI-1 1 computers. The manual presents general, installation, user, and program- 
ming information for the RX02 Floppy Disk System and the interface options associated with the 
PDP-8, PDP-11, and LSI-1 1 computer systems. 



IX 



CHAPTEE 1 
GENERAL INFORMATION 



Ll INTRODUCTION 

The RX02 is a low cost, random access mass memory device that stores data in fixed length blocks on 
fiexible diskettes with preformatted industry standard headers. The RX02 interfaces with either a 
PDP-8, a PDP-1 1, or an LSI- 11 system. Various interface modules are selected according to the com- 
puter being used and either single or double density recording. The various configurations are: 



Designation 


Computer 


Interface 


Recording 






Module 


Density 


RX8E 


PDP-8 


M8357 


Single 


RX28 


PDP-8 


M8357 


Single or Double 


RXIl 


PDP-11 


M7846 


Single 


RX211 


PDP-11 


M8256 


Single or Double 


RXVll 


LSI-11 


M7946 


Single 


RXV21 


LSI- 11 


M8029 


Single or Double 



NOTE 
The single density recording configurations RX8E, 
RXII, and RXVll are compatible with the RXOl 
Floppy Disk System when the M7744 controller 
module has been switched to be compatible with 
these conflgurations. (See Table 2-2.) 



The RXQ2 consists of two flexible disk drives, a single read/write electronics module, a micro- 
programmed controller module, and a power supply, enclosed in a rack-mountable, 10-1/2 inch, self- 
cooled chassis. A cable is included for connection to dther a PDP-8 interface module, a PDP-11 
interface module, or an LSI-1 1 interface module. The amount of data that can be stored on the RX02 
varies according to the configuration. The recording density can be different for each drive. For each 
drive system using double density recording, up to 512K 8-bit bytes of data (PDP-8, PDP-1 1, LSI-1 1) 
or 256 K 12-bit words (PDP-8) can be stored and retrieved. For each drive system using single density 
recording, up to 256K 8-bit bytes of data or 128K 12-bit words (PDP-8) can be stored and retrieved. 
The RX02 interfaces with IBM-compatible devices when single density data recording is used. 



1-1 



For single or double density recording, the RX02 is used with either an M8357 interface module (PDP- 
8), an M8256 interface module (PDP-11), or an M8029 interface module (LSI-1 1). The interface mod- 
ules convert the RX02 I/O bus to the bus structure of the computer being used. Each module controls 
the interrupts to the CPU initiated by the RX02 and handles the data interchange between the RX02 
and the host computer. Each interface module is powered by the host processor. 



In addition, the RX02 is used for single density recording when it is configured to be compatible with 
the RXOl. The interface module used is either an M8357 (PDP-8), an M7846 (PDP-1 1), or an M7946 
(LSI-1 1). 



To record or retrieve data the RX02 performs implied seeks. Given an absolute sector address, the 
RX02 locates the desired sector and performs the indicated function, including automatic head posi- 
tion verification and hardware calculation and verification of the cyclic redundancy check (CRC) 
character. The CRC character that is read and generated is compatible with IBM 3740 equipment. 



1.2 GENERAL DESCRIPTION 

An RX02 Floppy Disk System consists of the following components: 

M7744 Controller Module 

M7745 Read/Write Electronics Module 

H771-A, -C, or -D Power Supply 

RX02-CA Floppy Disk Drive (60 Hz max of 2) 

RX02-CC Floppy Disk Drive (50 Hz max of 2) 



One interface module is used: 

M8357 (PDP-8, Programmed I/O) 

M7846 (PDP-1 1, Programmed I/O) M8256 (PDP-1 1 with DMA) 

M7946 (LSI-1 1, Programmed I/O) M8029 (LSI-1 1 with DMA) 



All components except the interface modules are housed in a 10-1/2 inch rack-mountable box. The 
power supply, M7744 module, and M7745 module are mounted above the drives. Interconnection 
from the RX02 to the interface is with a 40-conductor BC05L-15 cable of standard length (15 ft). 
Figure 1-1 is a configuration drawing of the system: part A shows the configuration for a bus interface 
with DMA; part B shows the configuration for all Omnibus interfaces (programmed I/O); part C 
shows the configuration for a bus interface (programmed I/O) that is RXOl compatible. Figure 1-2 is a 
front view of a dual drive system. 



L2.1 Interface Modules 

The interface modules plug into a slot on the bus for PDP-8, PDP-1 1, and LSI-1 1 computers. Figure 
1-3 shows the outline of the various modules and areas of interest on each module. 



1-2 



DRIVE #0 



m 



Qread/write B 
electronics 

niVI7745 



z 



DISKETTE 
I A 7015-580 



BC05 
1 



D ficpu 

CONTROLLER 
M7744 * 



r OR »— 



M8029 

BUS 

INTERFACE 



DRIVE # 1 



o 



DISKETTE 



POWER 
SUPPLY H771 



A. BUS INTERFACE WITH DMA 



DRIVE #0 



Jojo 



] READ/WRITE (f 

ELECTRONICS 
nM7745 



Z 



ISKETTE 
I A 7015-580 



BC05L-15 



-g 



/iCPU ff 

CONTROLLER 
M7744 * 



DRIVE # 1 



o 



DISKETTE 



POWER 
SUPPLY 



H771 



( l l OMNI 

y r p" INTE 



M8357 
IBUS 
RFACE 



B. OMNIBUS INTERFACE, PROGRAMMED I/O 
DISKETTE 




DRIVE # 



READ/WRITE tt 

ELECTRONICS 

M7745 



. I A 7015-580 

£ C 



J /iCPU 

CONTROLLER 
M7744 * 



BC05L-15 . 



no •— — 



M8357 

OMNIBUS 

INTERFACE 



DRIVE # 1 



O DISKETTE 



POWER 
SUPPLY H771 



C. BUS INTERFACE, PROGRAMMED I/O (RX01 COMPATIBLE ) 



H 



M7946 

BUS 

INTERFACE 



•/v>. 












M8256 

UNIBUS 

INTERFACE 

_i 




1 









L 
|S 

I U 

I s 



I ui 

I B 
I Ui 
S 





M I 



LSI-11 



PDP-11 



I I ' PDP-8 



I 

I B I 
I U I 

S 



"^ 












M7846 

UNIBUS 

INTERFACE 




1 


OR 




: 



A SWITCH ON THIS MODULE IS POSITIONED TO BE COMPATIBLE WITH THE INTERFACE. 





M 

N 

I 

B 

U 

S 

U 
N 
I 

B 
U 
S 

L 
S 
I 

B 
U 
S 



PDP-8 



Figure 1-1 Floppy Disk Configuration 





M^i R>^02 
















'•' ' 1 f ' \>:r: . vpn p | ^ , ins 

4;tei:.;ii-il:ii;LL:::ii 






- \ 




1 


tzzH 


t": ^ 













Figure 1-2 Front View of the Floppy Disk System 



1-3 



M7946 MODULE (RXVIl) 

r -■ 1 

BC05L-15 
CABLE CONNECTION CABLE CONNECTION 



W1..W3 
W2..W5 
W4..W6 



W7... W13 

WB...W14 

W19..W9 

W16..W9 

W10..W17 

W11..W15 

W12.. 



n 



... W7 
... W8 
... W9 

... W10 

...W11 

...W12 

..W15 
W13..W16 
W14..W17 



...W1 
...W2 
...W3 
...W4 
...W5 
...W6 



n 



BC05L-15 

CABLE CONNECTION 



r ^ 1 




ADDRESS 


JUMPERS 


A12 / 


o\:^A3 

o o * 


1 



^-€- 



V8 



REV C & REV D 



n 



M8029 MODULE (RXV21) 



CABLE CONNECTION DEVICE CODE SWITCH PRIORITY PLUG CABLE CONNECTION 




rL_n n 



r 1 




^ 



n__n n 



ADDRESS 

SWITCH BC05L-15 

0FF=1 PRIORITY PLUG CABLE CONNECTION 



f 1 



VECTOR 
SWITCH 
0N=1 



ji__rL_rL 



M8357 MODULE (RX8E OR RX28) 



M7846 MODULE (RX11) 



M8256 MODULE (RX2n) 



Figure 1-3 Interface Modules 



1.2.2 Microprogrammed Controller 

The M7744 microprogrammed controller module is located in the RX02 cabinet as shown in Figure 
1-4. The M7744 is hinged on the left side and lifts up for access to the M7745 read/write electronics 
module. 

1.2.3 Read/Write Electronics 

The M7745 read/write electronics module is located in the RX02 cabinet as shown in Figure 1-4. 



CONFIGURATION 
SWITCH 




M7745 

READ/WRITE 

ELECTRONICS MODULE 



Figure 1-4 Top View of RX02 



1.2.4 Electromechanical Drive 

A maximum of two drives can be attached to the read/write electronics. The electromechanical drives 
are mounted side by side under the read/write electronics board (M7745). Figure 1-5 is an underside 
view of the drive showing the drive motor connected to the spindle by a belt. (This belt and the drive 
pulley are different on the 50 Hz and 60 Hz units; see Paragraph 2.1.3.2 for complete input power 
modification requirements.) 



1-5 



DRIVE MOTOR 
BELT 



DRIVE SPINDLE 
PULLEY 



AC 

POWER , 

CONNECTOR X \t^ 

^1 




Figure 1-5 Underside View of Drive 



1.2.5 Power Supply 

The H771 power supply is mounted at the rear of the RX02 cabinet as shown in Figure 1-4. The 
H771-A is rated at 60 Hz ±1/2 Hz over a voltage range of 90-128 Vac. The H771-C and -D are rated 
at 50 Hz + 1/2 Hz over four voltage ranges: 



90-120 Vac 

100-128 Vac 
184-240 Vac 

200-256 Vac 



3.5 A circuit breaker; H771-C 



1 .75 A circuit breaker; H771-D 



Two configuration plugs are provided to adapt the H771-C or -D to each voltage range. This is not 
applicable to the H771-A. 



1.3 OPTION DESCRIPTION 

The optional interface modules that are used to interface the RX02 with a PDP-8, PDP-1 1 , and LSI-1 1 
are listed in Paragraphs 1.1 and 1.2. (Each module is powered by the host processor.) The module 
selected is determined by the computer being used and whether the data interchange is between either 
IBM system 3740 compatible devices or DIGITAL system double density devices. Also, when an 
M7744 controller module's configuration switch is set to be compatible, the RX02 can operate as an 
RXOl. The RX02 interfaces with IBM compatible devices when single density data recording is used. 
The RX02 interfaces with DIGITAL system double density recording devices when the controller 
module configuration switch is positioned to be compatible with RX28, RX211, and RXV21 con- 
figurations. 



1-6 



1.3.1 Operation For Single Density Recording Only (RX8E, RXll, RXVll) 

1.3.1.1 PDP-8 Operation - The RX02 connects to the M8357 Omnibus interface module. This mod- 
ule converts the RX02 I/O bus to PDP-8 family Omnibus structure. It controls interrupts to the CPU 
initiated by the RX02, controls data interchange between the RX02 and the host CPU by programmed 
I/O, and handles input/output transfers used for maintenance status conditions. 

1.3.1.2 PDP-11 Operation -The RX02 connects to the M7846 Unibus interface module. This module 
converts the RX02 I/O bus to PDP-1 1 Unibus structure. It controls interrupts to the CPU initiated by 
the RX02, decodes Unibus addresses for register selection, and handles data interchange between the 
RX02 and the host CPU main memory by programmed I/O. 

1.3.1.3 LSI-11 Operation ™ The RX02 connects to the M7946 LSI-11 bus interface module. This 
module converts the RX02 I/O bus to the LSI-11 bus structure. It controls interrupts to the CPU 
initiated by the RX02, decodes LSI-1 1 bus addresses for register selection, and transfers data between 
the RX02 and the host CPU main memory by programmed I/O. 

1.3.2 Operation For Single or Double Density Recording {RX28, RX211, RXV21) 

1.3.2.1 PDP-8 Operation - The RX02 connects to the M8357 Omnibus interface module. This mod- 
ule converts t^e RX02 I/O bus to PDP-8 family Omnibus structure. It controls interrupts to the CPU 
initiated by the RX02, controls transfer of data between the RX02 and host CPU by programmed I/O, 
and handles input/output transfer used to test status conditions. 

1.3.2.2 PDP-1 1 Operation - The RX02 connects to the M8256 Unibus interface module. This module 
converts the RX02 I/O bus to PDP-1 1 Unibus structure. It controls interrupts to the CPU initiated by 
the RX02, decodes Unibus addresses for register selection, and initiates NPR requests to transfer data 
between the RX02 and the host CPU main memory. 

1.3.2.3 LSI-11 Operation - The RX02 connects to the M8029 LSLll bus interface module. This 
module converts the RX02 I/O bus to the LSI-11 bus structure. It controls interrupts to the CPU 
initiated by the RX02, decodes LSI-11 bus addresses for register selection, and initiates NPR requests 
to transfer data between the RX02 and the host CPU main memory. 

1.4 SPECIFICATIONS 

System Reliability 

Minimum number of revo- 3 million/media (head loaded) 

lutions per track 

Seek error rate 1 in 10^ seeks 

Soft data error rate 1 in 10^ bits read or written 

Hard data error rate 1 in 1012 bits read or written 

NOTE 
The above error rates only apply to DEC approved 
media that is properly cared for. Seek error and soft 
data errors are usually attributable to random effects 
in the head/media interface, such as electrical noise, 
dirt, or dust. Both are called "soft" errors if the er- 
ror is recoverable in 10 additional tries or less. 
"Hard" errors cannot be recovered. Seek error ret- 
ries should be preceded by a recalibrate. 



1-7 



Drive Performance 



Capacity 


Recording 




8-bit bytes 


12-bit words 


Per diskette 


FM 






256,256 


128,128 




MFM 






512,512 


256,256 


Per track 


FM 






3,328 


1,664 




MFM 






6,656 


3,328 


Per sector 


FM 






128 


64 




MFM 






256 


128 


Data transfer rate 












Diskette to controller buffer 


4 Ms/data bit (FM) 








2 fis/data 


bit (MFM) 




Buffer to CPU interface 




1.2 


Ms/bit 







NOTE 
PDP-8 interface can operate in 8- or 12-bit modes 
under software control. 



Track-to-track move 
Head settle time 
Rotational speed 
Recording surfaces per disk 
Tracks per disk 
Sectors per track 
Recording technique 
Bit density maximum on 
inner track 
Track density 
Average access 



6 ms/track maximum 

25 ms maximum 

360 rpm ± 2.5%; 166 ms/rev nominal 

1 

77 (0-76) or (0-1 Hg) 

26 (1-26) or (0-328) 

Double frequency (FM) or modified MFM 
3200 bpi (FM) or modified (MFM) 

48 tracks/inch 

262 ms, computed as follov^s: 

Seek Settle 



Rotate 

_-A_ 



77 tks/3 X 6 ms + 25 ms + 166 ms/2 = 262 ms^ 



Environmental Characteristics 



Temperature 

RX02, operating 

RX02, nonoperating 
Media, nonoperating 



15° to 32° C (59° to 90° F) ambient; 
maximum temperature gradient =11° C/hr (20^ 
-35° to +60° C (-30° to +140° F) 
-35° to +52° C (-30° to +125° F) 



F/hr) 



NOTE 
Media temperature must be within operating temper- 
ature range before use. 

Heat Dissipation (RX02 System) Less than 225 Btu/hr 



Relative humidity 
RX02, operating 



25° C (77° F) maximum wet bulb 
2° C (36° F) minimum dew point 
20% to 80% relative humidity 



1-8 



RX02, nonoperating 
Media, nonoperating 
Magnetic field 



Interface modules 

Operating temperature 
Relative humidity 
Maximum wet bulb 
Minimum dew point 



5% to 98% relative humidity (no condensation) 

10% to 80% relative humidity 

Media exposed to a magnetic field strength of 50 oersteds or 

greater may lose data. 



SMoSO*' C(4r 
10% to 90% 
32° C (90° F) 
2° C (36° F) 



to 122° F) 



Electrical 



Power consumption 
RX02 

PDP-11 interface (M7846, 
M8256) 

PDP-8 interface (M8357) 
LSMl interface (M7946, 
M8029) 
AC power 



5 A at +5 Vdc, 25 W; 0. 14 A at -5 Vdc, 0.7 W; 1 .3 A t +24 Vdc, 

31 W 

1.8 A at 5 Vdc 

1.5 A at 5 Vdc 
1.8 A at 5 Vdc 

4 A at 115 Vac 
2 A at 230 Vac 



1.5 SYSTEMS COMPATIBILITY 

This section describes the physical, electrical, and logical aspects of compatibility for data interchange 

with IBM system 3740 devices and for data interchange with double density devices. 

L5J Media 

The media used on the RX02 Floppy Disk system is compatible with the IBM 3740 family of equip- 
ment and is shown in Figure 1-6. The "diskette" media was designed by applying tape technology to 
disk architecture, resulting in a flexible oxide-on-mylar surface. The diskette is encased in a plastic 
envelope with a hole for the read/write head, a hole for the drive spindle hub, and a hole for the hard 
index mark. The envelope is Uned with a fiber material that cleans the diskette surface. The media is 
supplied to the customer preformatted and pretested. 



NDEX HOLE 




REGISTRATION 
HOLE 



READ/'WRITE 
HEAD APERTURE 



Figure 1-6 Diskette Media 



1-9 



1,5,2 Recording Scheme 

There are two recording schemes used in the RX02: double frequency (FM) and modified Miller code 
(MFM). The FM scheme is used for single density data recording which is compatible with IBM 
system 3740 devices. (When this recording scheme is used and the RX02 is configured as shown in 
Figure 1-1 part C, the RX02 is compatible with the RXOl.) The MFM scheme is used for double 
density data recording which is compatible with DIGITAL double density devices but is not com- 
patible with other manufacturers. 

1.5.2.1 Double Frequency (FM) - For the double frequency recording scheme data is recorded be- 
tween bits of a constant clock stream. The clock stream consists of a continuous pattern of one flux 
reversal every four ^s (Figure 1-7). A data "one" is indicated by an additional reversal between clocks 
(i.e., doubling the bit stream frequency; hence the name). A data "zero" is indicated by no flux reversal 
between clocks. 

A continuous stream of ones, shown in the bottom waveform in Figure 1-7, would appear as a "2F" 
bit stream, and a continuous stream of zeros, shown in the top waveform in Figure 1-7, would appear 
as a "IF" or fundamental frequency bit stream. 



__r 



r- 1 I ALL ZEROS 

J I I PATTERN 



J Ln TLJU — LrLTL-TLr 

I I I I I I I <{ I I ! I 

OIOi1lOI1i1iOi1l1lOi1«OiOI 

iji_jijijiji_jijlj1_ri_r^^ 



CHANGING 
PATTERN 



ALL ONES 
PATTERN 



I 1 1 



I 4m sec 



1111111111 



1 I 1 I 1 ! 1 I 1 ! 



Figure 1-7 Flux Reversal Patterns for FM 



1.5.2,2 Miller Code (MFM) - MFM or Miller code encodes clocks between data bits of a continuous 
data stream. The data stream consists of flux reversals for a data "one" and no flux reversal for a data 
"zero." A clock is recorded only between data "zeros." Because it is possible to have double density 
data fields map into a preamble and ID mark, the MFM encoding is modified slightly to prevent a 
false header from being detected within a double density data field, 

NOTE 
The modifiecl MFM encoding is not compatible with 
other manufacturers. 

The encoding algorithms for implementing modified MFM are: 

Encoding Algorithm #1 (MFM or Miller Code Algorithm) 





Data 


Encoded Data 




Dn 


Dn + 1 


Dn 


Cn 


Dn + 1 











1 





1 





1 











1 








1 


1 


1 


1 





I 



-10 



Encoding Algorithm #2 (MFM Modified Algorithm) 

Data 



Dn 


Dn+ 1 


Dn + 2 


Dn + 3 


Dn + 4 


Dn + 5 





1 


1 


1 


I 














1 


Encoded Data 










Dn 


Cn 


Dn + 1 


Cn + 1 


Dn + 2 


Cn + 2 


Dn + 3 


Cn + 3 


Dn + 4 


Cn + 4 


Dn + 5 





1 











1 











1 






The decoding algorithm used in data separation is: 





Encoded 




Decoded 




Dn 


Cn 


Dn+ I 


Dn 


Dn+ ! 











1 




1 





1 













1 








1 













1 







1 


1 





1 


1 




1 



Figure 1-8 shows the waveforms that are generated for a data stream of zeros and ones when FM code, 
MFM code, and modified MFM code are used. 



DATA 



F M 



MFfV! 



iJT-n_n rLrLTLTLr 



r 

s 

1_ 



MODIFIED 

MFM 



DATA ' 0011101111000 

I ! s i M ! I ! i I ! ! 
f ! ! i I I j ! I ! 1 I I 
fill! ill I 1 I ! I 

MOD,F,EDj-L[y-|_JLp 



fVIFM 



WHERE] DATA " = 2 /DATA 



-MODIFYING - 
ALGORITHfvl 



Figure 1-8 FM versus MFM Encoding 



J — \ r 



1-11 



.1.53 Logical Format 

Data is recorded on only one side of the diskette. This surface is divided into 77 concentric circles or 
''tracks" numbered 0-76. Each track is divided into 26 sectors numbered 1-26 (Figure 1-9). Each 
sector contains two major fields: the header field and the data field (Figure 1-10). 



SECTOR 



-L.E.D. TRANSDUCER OUTPUT 



HARD 
INDEX 
MARK 



-iV- 



PRE INDEX 

GAP 
-■320 BYTES 

— ^v— 



SECTOR 



SECTOR 

- 2 



SECTOR 

■~ 3 



SOFT INDEX MARK 
1 BYTE 



-ROTATION 



SECTOR 

- 4 



Figure 1-9 Track Format (Each Track) 















HEADER FIELD 










DATA FIELD 






















.A 






r 








"^ 




\ 














„_££ 




IL 


















1 




'-nr^ 


Q 


< 
< 


!«' 












CO 




fn 








LU 
LL. 


128,0 BYTES OF FM 




LU 




O to 


< 


LU 




UJ 








U 


Q 


DATA 




£B O 


INTER- 


i° 


2 


a 


UJ 

p ^ 


Q 


- LU 


HEADER 




z 
> 


UJ 


OR 


DATA 


?/5 ^ 


SECTOR GAP 
26 BYTES 


Li. UJ 


UJ 


Q 
< 


< 


toH 

o ^ 

, GO 


CRC 

2 BYTES 




to 


LU 

Q > 


256,0 BYTES OF MFM 
(MODIFIED) 


CRC 

2 BYTES 


O °^ 


I's OR O's 


>- m 


Q UJ 


u t" 




g K 


,_. 






< ° 


< ^ 

h- EC 


DATA 




n_ ^ 




CO to 


< > 
D 














2: UJ 


























< m 


< < 












, 












^^gi„ „„ 


Q CO 


O ^ 


St 








— PREAfV 










%1 












1BLE 








1 1 BYTES 






«#— 6 BYTES 


























ID GAP 




1 








WRITE GATE T 


URN OFF 








1's OR O's 






WRITE GATE TURN ON 






— c:r\£3 ift/oiTir r%c 


PRECEEDINC 


3 












- FOR WRITE OF NEXT 










DATA FIELD 










^^^ ROTATION 






DATA FIELD 
































MA. 182? 



Figure l-IO Sector Format (Each Sector) 



L53.1 Header Field Description - The header field is broken into seven bytes (eight bits/byte) of 
information and is preceded by a field of at least six bytes of zeros for synchronization. The header and 
its preamble are always recorded in FM. 

1 . Byte No. 1 : ID Address Mark - This is a unique stream of fiux reversals (not a string of data 
bits) that is decoded by the controller to identify the beginning of the header field. (Data = 
FE hex, clock = C7 hex.) 

2. Byte No. 2: Track Address - This is the absolute (0-1 14g) binary track address. Each sector 
contains track address information to identify its location on 1 of the 77 tracks. 



3. Byte No. 3: ~ Zeros 



M2 



4. Byte No. 4: Sector Address - This is the absolute binary sector address (1-328). Each sector 
contains sector address information to identify its circumferential position on a track. There 
is no sector 0. 

5. Byte No, 5: - Zeros 

6,7. Bytes No. 6 and 7: CRC - This is the cycHc redundancy check character that is calculated for 
each sector from the first five header bytes using the IBM 3740 polynomial. 

L53.2 Data Field Description - The data field contains either 131 lo or 259io bytes of information 
depending on the recording scheme. This field is preceded by a field of zeros for synchronization and 
the header field (Figure 1-10). 



1. 



Byte No. 1: Data or Deleted Data Address mark - This byte is always recorded in FM and is 
unique because it contains missing clocks. It is decoded by the controller to identify the 
beginning of a data field. The deleted data mark is not used during normal operation but the 
RX02 can identify and write deleted data marks under program control as required. There is 
a unique address mark for each density as shown in the following table. One of these marks 
is the first byte of each data field. 

Table 1-1 Data Address Mark Code 







Hex Byte 




Mark 


Density 


Data 


Clock 


Data 


FM 

MFM mod. 


FB 
FD 


C7 
C7 


DELETED 

DATA 


FM 


F8 


C7 


MFM mod. 


F9 


C7 



2. Bytes No. 2: -129 (FM) or ™257 (MFM modified) - This is the data field and it can be 
recorded in either FM or MFM (modified). It is used to store 128io or 256io (depending 
upon encoding) 8-bit bytes of information. 

NOTE 
Partial data fields are not recorded. 

3. Bytes No. 130 and 131 or 258 and 259 -- These bytes comprise the CRC character that is 
calculated for each sector from the first 129 or 257 data field bytes using the industry stand- 
ard polynomial division algorithm designed to detect the types of failures most likely to 
occur in recording on the fioppy media. These bytes will be recorded with the same encoding 

scheme as the data field. 

1333 Track Usage - In the IBM 3740 system, some tracks are commonly designated for special 
purposes such as error information, directories, spares, or unused tracks. The RX02 is capable of 
recreating any system structure through the use of special systems programs, but normal operation will 
make use of all the available tracks as data tracks. Any special file structures must be accomplished 
through user software, 

L53.4 CRC Capability - Each sector has a two-byte header CRC character and a two-byte data 
CRC character to ensure data integrity. The CRC characters are generated by the hardware during a 
write operation and checked to ensure all bits were read correctly during a read operation. The CRC 
character is the same as that used in IBM 3740 series equipment. 



1-13 



CHAPTER 2 
INSTALLATION 



This chapter contains information that is required for site preparation, unpacking, installation, and 
testing of the RX02 Floppy Disk System. Information is also provided to identify the various system 
configurations that are available. 

2.1 SITE PREPARATION 



2.1.1 Space . . , ^ . 

The RX02 is a cabinet-mountable unit that may be installed in a standard Digital Equipment Corpo- 
ration cabinet. This rack-mountable version is approximately 28 cm high, (10-1/2 inches), 48 cm wide, 
(19 inches) and 42 cm deep (16-1/2 inches) as shown in Figure 2-1. 





10 

(26. 


.5" 


mill" "' 


llSliJlil 


/cm) 


- .£IZ1 


i ! 








r 


19" 

■^ {48.3cm) -^ 





IFRONT) 



(FRONT VIEW) 



17.0" 
" (43.2cm) "~ 



z 



-SEE NOTE 
INSIDE TRACK 






26.5" 
~f66.3cm)- 



(SIDE VIEW) 

NOTE: 

DUST COVER ATTACHED TO 
CABINET NOT RX02 



Figure 2-1 RX02 Outline Dimensions 



2-1 



When the RX02 is mounted in a cabinet (Figure 2-2), provision should be made for service clearances 
of approximately 56 cm (22 inches) at the front and rear of the cabinet so that the RX02 can be 
extended or the cabinet rear door opened. 



-SWINGING DOOR 
R.H. OR L.H. 



REMOVABLE- 
END PANEL 



CABLE ACCESS- 



CASTER SJAJIVEL 
RADIUS 2''^- - 
(6.12 cm) 
(4) CASTERS 



r- SWINGING MOUNTING 

\ FRAME DOOR R.H. OR L.H. 



18 hi- 
146.35cm) 



PORTS 




REMOVABLE 
'END PANEL 



48 Vjj" 
(122.47cm) 



3.0" 
(76.2cm) 



CABINET 71 7/16" (182.28 cm) HIGH 
(FLOOR LINE TO CABINET TOP) 



Figure 2-2 Cabinet Layout Dimensions 



2A2 Cabling 

The standard interface cable provided with an RX02 (BC05L-15) is 4.6 m (15 ft) in length; the position- 
ing of the RX02 in relation to the central processor should be planned to take this into consideration. 
The RX02 should be placed near the control console or keyboard so that the operator will have easy 
access to load or unload disks. The position immediately above the CPU is preferred. The ac power 
cord is about 2.7 m (9 ft) long. 

2.13 AC Power 



2.13.1 Power Requirements - The RX02 is designed to use either a 60 Hz or a»50 Hz power source. 
The 60 Hz version will operate from 90-128 Vac, without modifications, and will use less than 4 A 
operating. The 50 Hz version will operate within four voltage ratings and will require field veri- 
fication/modification to ensure that the correct voltage option is selected. The voltage ranges of 
90-120 Vac and 184-240 Vac will use less than 4 A operating. The voltage ranges of 100-128 Vac and 
200-256 Vac will use less than 2 A. Both versions of the RX02 will be required to receive the input 
power from an ac source (e.g., 861 power control) that is controlled by the system's power switch. 



2-2 



2,1.3,2 Input Power Modification Requirements - The 60 Hz version of the RX02 uses the H771-A 
power supply and will operate on 90-128 Vac, without modification. To convert to operate on a 50 Hz 
power source in the field, the H771-A supply must be replaced with an H771-C or -D (Figure 1-4) and 
the drive motor belt and drive motor pulley must be replaced (Figure 1-5). The H771-C operates on a 
90-120 Vac or 100-128 Vac power source. The H771-D operates on a 184-240 Vac or 200-256 Vac 
power source. To convert the H771-C to the higher voltage ranges or the H771-D to the lower voltage 
ranges, the power harness and circuit breaker must be changed. See Figure 2-3 for the appropriate 
jumper and circuit breaker. 



JUMPER PI 




SHIPPING 






POWER PLUGS 


RESTRAINT (RED) 








VOLTAGE (VAC) 




JUMPER 


CIRCUIT BREAKER 


90-120 




70-10696-02 


3.5 A. 12-12301-01 


100-128 




70-10696-01 


3.5 A, 12-123-1-01 


184-240 




70-10696-04 


1.75 A, 12-12301-00 


200-256 




70^10696-03 


1.75 A. 12-12301-00 




Fn 


^ure 2-3 RX02 Rear View 



2AA Fire and Safety Precaptions 

The RX02 Floppy Disk System presents no additional fire or safety hazards to an existing computer 
system. Wiring should be carefully checked, however, to ensure that the capacity is adequate for the 
added load and for any contemplated expansion. 



2.2 CONFIGURATION GUIDELINES 

The most common RX02 Floppy Disk System configurations available are listed in Table 2-1. Each 

interface module listed in the table plugs into a computer bus; it is compatible with the applicable 

computer so that there is adequate power to operate each module. The interconnections between each 

interface module and the RX02 controller for each of the configurations in Table 2-1 is by a BC05L-15 

cable which is 4.6 m (15 ft) maximum. (See Table 2-2 for the controller module configuration switch 

positions.) 



2-3 







Table 2-1 RX02 Configurations 




Computer 


System 
Deagnation 


mCPU 
Controller 


Inteiface 
Module 


RX02 
Model No. 


Power 
Supply 




RX8E 


M7744 ■ 


M8357 


RX02-BA 
RX02-BC 
RX02-BD 


1 15 V, 60 Hz 
115 V, 50Hz 
230 V, 50 Hz 


PDP-8 


RX28E 


M7744 


M8357 


RX02-BA 
RX02-BC 
RX02-BD 


115 V, 60Hz 
115 V, 50 Hz 
230 V, 50 Hz 




RXll 


M7744 


M7846 


RX02-BA 
RX02-BD 
RX02-BD 


115 V, 60Hz 
230 V, 50 Hz 
230 V, 50 Hz 


PDP41 


RX2n 


M7744 


M8256 


RX02-BA 
RX02-BC 
RX02-BD 


115 V, 60 Hz 
115 V, 50Hz 
230 V, 50 Hz 




RXVli 


M7744 


M7946 


RX02-BA 
RX02-BC 
RX02-BD 


115 V, 60Hz 
115 V, 50Hz 
230 V, 50 Hz 


LSI-11 


RXV21 


M7744 


M8029 


RX02-BA 
RX02-BC 
RX02-BD 


1 15 V, 60 Hz 
115 V, 50 Hz 
230 V, 50 Hz 



Table 2-2 Controller Configuration Switch Positions 



Interface 

RX211, RXV21, 
RX8E, RXll, RXVll, 
RX28 



Sl-1 


Sl-2 


OFF 

ON 

OFF 


ON 

OFF 

OFF 




23 ENVIRONMENTAL CONSIDERATIONS 

23.1 General 

The RX02 is capable of efficient operation in computer environments; however, the parameters of the 
operating environment must be determined by the most restrictive facets of the system, which in this 
case are the diskettes. 

23.2 Temperature, Relative Himiidity 

The operating ambient temperature range of the diskette is 15° to 32° C (59° to 90° F) with a max- 
imum temperature gradient of 1 1° C/hr (20° F/hr). The media nonoperating temperature range (stor- 
age) is increased to -34.4° to 51.6° C (-30° to 125° F), but care must be taken to ensure that the media 
has stabilized within the operating temperature range before use. This range will ensure that the media 
will not be operated above its absolute temperature limit of 51.6° C (125° F). 



2-4 



Humidity control is important in any system because static electricity can cause errors in any CPU 
with memory. The RX02 is designed to operate efficiently within a relative humidity range of 20 to 80 
percent, with a maximum wet bulb temperature of 25° C (77° F) and a minimum dew point of 2° C 
(36° F). 



2.3.3 Heat Dissipation 

The heat dissipation factor for the RX02 Floppy Disk System is less than 225 Btu/hr. By adding this 
figure to the total heat dissipation for the other system components and then adjusting the result to 
compensate for such factors as the number of personnel, the heat radiation from adjoining areas, and 
sun exposure through windows, the approximate cooling requirements for the system can be deter- 
mined. It is advisable to allow a safety margin of at least 25 percent above the maximum estimated 
requirements. 



23A Radiated Emissioes 

Sources of radiation, such as FM, vehicle ignitions, and radar transmitters located close to the com- 
puter system, may affect the performance of the RX02 Floppy Disk System because of the possible 
adverse effects magnetic fields can have on diskettes. A magnetic field with an intensity of 50 oersteds 
or greater might destroy all or some of the information recorded on the diskette. 



23.5 Cleaaliness 

Although cleanliness is important in all facets of a computer system, it is particularly important in the 
case of moving magnetic media, such as the RX02. Diskettes are not sealed units and are vulnerable to 
dirt. Such minute obstructions as dust specks or fingerprint smudges may cause data errors. Therefore, 
the RX02 should not be subjected to unusually contaminated atmospheres, especially one with abra- 
sive airborne particles. 



NOTE 
Removable media iiiYohe use^ handlings and maiiite« 
fiance which are beyond DIGITALIS direct control. 
DIGITAL disclaims responsibility for performance 
of the equipment when operated with media not 
meeting DIGITAL specifications or with media not 
maintained in accordance with procedyres approved 
by DIGITAL, DIGITAL shall not be liable for dam- 
ages to the equipment or to media resulting from 
such operation. 



2.4 UNPACKING AND INSPECTION 



2.4.1 General 

The RX02 Floppy Disk System can be shipped in a cabinet as an integral part of a system or in a 
separate container. If the RX02 is shipped in a cabinet, the cabinet should be positioned n c! j final 
installation location before proceeding with the installation. 

2-5 



2A2 Tools 

Installation of an RX02 Floppy Disk System requires no special tools or equipment. Normal hand 
tools are all that are necessary. However, a forklift truck or pallet handling equipment may be needed 
for receiving and installing a cabinet-mounted system. 

2A3 Unpacking 



2 A3. 1 Cabinet-Momited 

1. Remove the protective covering over the cabinet. 

2. Remove the restraint on the rear door latch and open the door. 

3. Carefully roll the cabinet off the pallet; if a forkhft is available, it should be used to lift and 

move the cabinet. 

4. Remove the shipping restraint from the RX02 and save it for possible reuse, 

5. Slide the RX02 out on the chassis slides and visually inspect for any damage as indicated in 

Paragraph 2,43.3. 

2.4 JJ Separate Container 

!. Open the carton (Figure 2-4) and remove the packing pieces. 

2. Lift the RX02 out of the carton. 

3. Remove the shipping fixtures from both sides of the RX02 and inspect for shipping damage 

as indicated in Paragraph 2.4.3.3. 

4. Attach the inside tracks of the chassis slides provided in the carton to the RX02 (Figure 2- 1 ). 

5. Locate the proper holes in the cabinet rails (Figure 2-5) and attach the outside tracks to the 
cabinet. 

6. Place the tracks attached to the RX02 inside the extended cabinet tracks and slide the unit in 
until the tracks lock in the extended position. 

7. Attach the front bezel with the screws supplied. 

8. Locate the RX02 cover in the cabinet above the unit and secure it to the cabinet rails (Figure 

2^5), 



2^6 



SLIDES 



DISKETTES 



DUST 
COVER 




SHIPPING 
CARTON 



Figure 2-4 RX02 Unpacking 




□ 



-COVER 



, SCREWS. 
'chassis SLIDES 



Figure 2-5 RX02 Cabinet Mounting Information 



2-7 



■ 2A33 Inspection 

1 . Inspect the front cover(s) of the RX02 to be sure it operates freely. Compress the latch which 
allows the spring-loaded front cover to open. 

2. Inspect the rear of the RX02 chassis to be sure there are no broken or bent plugs. Also, be 
sure the fuse is not damaged. 

3. Visually inspect the interior of the unit for damaged wires or loose hardware. 

4. Loosen the screws securing the hinged upper module (M7744) and raise the module so that 
modules M7744 and M7745 can be inspected for damaged components or wires. 

5. Verify that the items listed on the shipping order are included in the shipment. Be sure the 
interface cable (BC05L-15) and the appropriate interface m.odule are included, 

NOTE 
If any shipping damage is foend, the customer shoyld 
be notified at this time so he can contact the carrier 
and record the information on the acceptance form, 

2.5 INSTALLATION 

L Ensure that power for the system is off, 

2. Loosen the screws securing the upper module (M7744) and swing it up on the hinge. 

3. Inspect the wiring and connectors for proper routing and ensure that they are seated cor- 
rectly. 

4. This step is for 50 Hz versions only. Check the power configuration to ensure that the proper 
jumpers and the correct circuit breaker are installed (Figure 2-3). 

5. Connect the BC05L-15 cable to the M7744 module and route it along the near side of the 
chassis through the back of the RX02 to the CPU; then connect it to the interface module 
for the PDP-8, PDP-11, or LSI-11. 

The cable is connected to the M7744 module with the red stripe on the left, looking from the 
component side of board; the cable is connected to the interface module with the red stripe 
toward the center of the module. 

6. Refer to Table 2-2 for the correct controller configuration switch positions. 

7. Refer to Table 2-3 for correct device code or addressing jumpers on the interface module. 

8. Insert the interface module into the Omnibus (PDP-8), available SPC slot (PDP-1 1), or LSI 
bus (LSI-11). The PDP-11 and LSI-U interface modules must be inserted in the lowest 
numbered available option location. Modules that use DMA processing should have a 
higher priority than programmed I/O devices. For modules using DMA processing in the 
PDP.l 1 SPC slot, ensure that the NPG (NPG IN, NPG OUT) line (CAl^Bl) is cut on the 
backplane. 

9. Connect the RX02 ac power cord into a switched power source. 

10. Turn the power on, watching for head movement on the drive(s) during the power up, 
initialize phase. The head(s) should move one track toward the center and back to track 
zero. 



2-8 



Table 2-3 Interface Code/ Jumper Configuration 



PDP-8 (M8357) 



Device Codes 





SWl 


SW2 


SW3 


SW4 


SW5 


SW6 


670X* 


ON 


ON 


ON 


OFF 


OFF 


OFF 


67 IX 


ON 


ON 


OFF 


OFF 


OFF 


ON 


672X 


ON 


OFF 


ON 


OFF 


ON 


OFF 


673X 


ON 


OFF 


OFF 


OFF 


ON 


ON 


674X 


OFF 


ON 


ON 


ON 


OFF 


OFF 


675X 


OFF 


ON 


OFF 


ON 


OFF 


ON 


676X 


OFF 


OFF 


ON 


ON 


ON 


OFF 


67 7X 


OFF 


OFF 


OFF 


ON 


ON 


ON 







PDP-11 (M7846) (M8256) 




BR Priority 


Unibus Address 177 17X* 


Vector Address (2648)* 


BR7 - 54-08782 


A 12/W18- Removed 


SWIO OFF 


V2/W1 -Installed 


SWl ON 


BR6 » 54-08780 


A11/W17- Removed 


SW9 OFF 


V3/W2- Removed 


SW2 0FF 


BR5 - 54-08778* 


A10/W16- Removed 


SW8 OFF 


V4/W3 - Installed 


SW3 ON 


BR4- 57-08776 


A9/W15- Removed 


SW7 OFF 


V5/W4- Installed 


SW4 0N 




A8/W14- Installed 


SW6 0N 


V6/W5 - Removed 


SW5 OFF 




A7/W13" Installed 


SW5 ON 


V7/W6" Installed 


SW6 ON 




A6/W1 2 -Removed 


SW4 OFF 


V8/W7 - Removed 


SW7 OFF 




A5/W1 1 - Removed 


SW3 OFF 








A4/W10- Removed 


SW2 OFF 








A3/W9 -Removed 


SWl OFF 







LSI-11 



(M7946) 


(M8029) 


Register Address* 


Vector Address* 


Register Address* 


Vector Address* 


(17717X.) 


(264s) 


(17717Xe) 


(264«) 


A-! - CPU Selectable 


W-l/V-2- Removed 


A- 1- CPU Selectable 


V2™ Installed 


W-7/A-2- Installed 


W-2/V-3- Installed 


A-2-Hardwirai 


V-3 - Removed 


W-8/A-3 - Removed 


W-3/V-4- Removed 


A-3- Installed 


V-4- Installed 


W-9/A-4 - Removed 


W-4/V-5 - Removed 


A-4- Installed 


V-5- Installed 


W-lO/A-5- Removed 


W-5/V-6 - Installed 


A-5-" Installed 


V-6- Removed 


W-ll/A-6- Removed 


W-6/V-7 - Removed 


A-6- Installed 


V-7- Installed 


W-12/A-7™ Installed 




A-7 - Removed 


V-8 - Removed 


W-1 3/ A-8- Installed 




A-8 Removed 




W-14/A-9- Removed 




A-9- Installed 




W-i5/A-10- Removed 




A-IO- Installed 




W-1 6/ A- 11 -Removed 




A- 11 -Installed 




W-17/A-12-Removed 




A-12- Installed 





*Standard 



2-9 



2,5.1 PDPS-A Modification 

In order to bootload from an RX02 on a PDP8-A system, it is necessary to modify the KM8-A 
(M8317) extended option module (if present) as follows (Figure 2-6): 

® replace E82 with prom #23-465A2 

® replace E87 with prom #23-469 A2 

® set SW#1 and SW#2 according to the bootload device as shown below. 

Program S2-5 S2-6 S2-7 S2-8 Sl-1 Sl-2 Sl-3 



H/LPTR 


ON 


ON 


ON 


OFF 


ON 


ON 


ON 


RK8-E 


ON 


OFF 


ON 


OFF 


ON 


OFF 


ON 


RX8-E 


ON 


OFF 


OFF 


ON 


OFF 


ON 


ON 


RL8A 


OFF 


ON 


OFF 


OFF 


OFF 


ON 


OFF 




Figure 2-6 KM8-A Modification 



2.6 TESTING 

To test the operation of RX02, run the DEC diagnostics supplied. Perform the diagnostics in the 

sequence listed for the number of passes (time) indicated. 



RX8 or RXll Diagnostic - 2 passes 
Data Reliability/Exerciser - 3 passes 
DECX-8 or DECX-ll - 10 minutes 

If any errors occur contact Field Service. 



2-10 



CHAPTER 3 

USER INFORMATION 



3.1 CUSTOMER RESPONSIBILITY 

It is the user's responsibility to ensure that the RX02 is located and operated in an area that is free 
from excessive dust and dirt, and meets or exceeds the environmental conditions listed in Paragraph 
1.4. The exterior of the RX02 should be kept clean. Also, it is the user's responsibility to ensure that 
the diskettes are handled and stored properly in order to prevent errors or data loss which might occur 
when recording or reading data; diskette handling procedures are described in Paragraph 3.2. 



3.2 CARE OF MEDIA 



3.2.1 Handling Practices and Precautions 

To prolong the diskette life and prevent errors when recording or reading, reasonable care should be 
taken when handling the media. The following handling recommendations should be followed to 
prevent unnecessary loss of data or interruptions of system operation. 

1 . Do not write on the envelope containing the diskette. Write any information on a label prior 
to affixing it to the diskette. 

2. Paper clips should not be used on the diskette. 

3. Do not use writing instruments that leave flakes, such as lead or grease pencils, on the jacket 
of the media. 

4. Do not touch the disk surface exposed in the diskette slot or index hole. 

5. Do not clean the disk in any manner. 

6. Keep the diskette away from magnets or tools that may have become magnetized. Any disk 
exposed to a magnetic field may lose information. 

7. Do not expose the diskette to a heat source or sunlight. 

8. Always return the diskette to the envelope supplied with it to protect the disk from dust and 
dirt. Diskettes not being used should be stored in a file box if possible. 

9. When the diskette is in use, protect the empty envelope from liquids, dust, and metallic 
materials. 

10. Do not place heavy items on the diskette. 



3-1 



1 1 . Do not store diskettes on top of computer cabinets or in places where dirt can be blown by 
fans into the diskette interior. 

12. If a diskette has been exposed to temperatures outside the operating range, allow five min- 
utes for thermal stabilization before use. The diskette should be removed from its packaging 
during this time. 

CAUTION 
® Do not iise paper clips on diskettes, 
® Do not expose the diskette to a heat soyrce or sMn- 

light, 
® Keep the diskettes from magnetic fields. 
® Do not write on the diskette with an instrument 

that leaves an impression or flakes. 



3.2.2 Diskette Storage 



3.2.2.1 Short Term (Available for Immediate Use) 

1. Store diskettes in their envelopes. 

2. Store horizontally, in piles often or less. If vertical storage is necessary, the diskettes should 
be supported so that they do not lean or sag, but should not be subjected to compressive 
forces. Permanent deformation may result from improper storage. 

3. Store in an environment similar to that of the operating system; at a minimum, store within 
the operating environment range. 



3.2.2.2 Long Term - When diskettes do not need to be available for immediate use, they should be 
stored in their original shipping containers within the nonoperating range of the media. 



3.2.3 Shipping Diskettes 

Data recorded on disks may be degraded by exposure to any sort of small magnet brought into close 
contact with the disk surface. If diskettes are to be shipped in the cargo hold of an aircraft, take 
precautions against possible exposure to magnetic sources. Because physical separation from the mag- 
netic source is the best protection against accidental erasure of a diskette, diskettes should be packed at 
least 3 inches within the outer box. This separation should be adequate to protect against any magnetic 
sources likely to be encountered during transportation, making it generally unnecessary to ship dis- 
kettes in specially shielded boxes. 

When shipping, be sure to label the package: 

DO NOT EXPOSE TO PROLONGED HEAT OR SUNLIGHT 

When received, the carton should be examined for damage. Deformation of the carton should alert the 
receiver to possible damage of the diskette. The carton should be retained, if it is intact, for storage of 
the diskette or for future shipping. 

3-2 



33 OPERATING INSTRUCTIONS 



NOTE 
The left drive is always identified as drive 0. 



The RX02 has no operator controls and indicators. The diskette is inserted on a drive after com- 
pressing the latch to allow the spring-loaded front cover to open. Place the diskette with the label or 
top up (the jacket seams are on the bottom) on the drive spindle. Close the front cover which will 
automatically lock when it is pushed down. Initialize the system (from the computer) and listen for 
audible clicking sounds which indicate the head is moving over the diskette; the RX02 is ready for use. 
Data storage and retrieval is controlled by the user's program. 



CAUTION 
Do not open the drive door while the diskette is in 
use; this results in errors. 



3.4 OPERATOR TROUBLESHOOTING 

Table 3-1 is a list of possible problems and some probable causes the operator may encounter. If the 

problem cannot be corrected, refer to the RX02 Floppy Disk System Technical Manual if available. 



Table 3-1 Operator Troubleshooting Guide 



Problem 


Probable Cause 


Correction 


No power 


a. 


Power cord disconnected 


a. 


Connect power cord 


(drive inoperative) 


b. 


Blown fuse 


b. 


Replace fuse 




c. 


Circuit breaker open 


c. 


Close circuit breaker 


Drive not ready 


a. 


Drive door open 


a. 


Close door 




b. 


Diskette improperly installed 


b. 


Properly seat diskette 


Error in recording 


a. 


Diskette wear 


a. 


If worn, replace 




b. 


Diskette mounting hole 


b. 


If the hole is not concentric, re- 
place diskette 




c. 


Mismatch in recording density 
on a diskette 


c. 


If diskette data density is not 
compatible with data to be re- 
corded, replace diskette with a 
new Preformatted diskette. 



3-3 



CHAPTER 4 
PROGRAMMING 



This chapter contains programming information for the following interface options: RX8E, RX28, 
RXll, RXVll, RX211, and RXV21. The RX8E and RX28 programming information is presented 
followed by the RXl 1 and RXVl 1 information and then the RX21 1 and RXV21 information is pre- 
sented. The RX8E, RXll, and RXVll options are used for single density recording and are com- 
patible with the RXOl Floppy Disk System. The RX28E, RX211, and RXV21 can be used for either 
single or double density recording. 



4.1 RX8E AND EX28 PROGRAMMING INFORMATION 

The RX8E interface allows two modes of data transfer: 8-bit word length and 12-bit word length. In 
the 12-bit mode, 64 words are written in a diskette sector, thus requiring 2 sectors to store 1 page of 
information. The diskette capacity in this mode is 128,128 12-bit words (1001 pages). In the 8-bit 
transfer mode, 128 8-bit words are written in each sector. Disk capacity is 256,256 8-bit words, which is 
a 33 percent increase in disk capacity over the 12-bit mode. The 8-bit mode must be used for generating 
IBM-compatible diskettes, since 12-bit mode does not fully pack the sectors with data. The hardware 
puts in the extra Os. Data transfer requests occur 23 ms after the previous request was serviced for 12- 
bit mode (18 ms for 8-bit mode). There is no maximum time between the transfer request from the 
RX02 and servicing of that request by the host processor. This allows the data transfer to and from the 
RX02 to be interrupted without loss of data. 

The RX28 interface allows two modes of data transfer: 8-bit word length and 12-bit word length. For 
each mode of data transfer there can be either single density or double density storage of data. In the 
12-bit mode single density recording, 64 words are written in a diskette sector, and the diskette capac- 
ity is 128,128 12-bit words; for double density, there are 128 words written in a sector with a diskette 
capacity of 256,256 12-bit words. In the 8-bit word mode single density recording, 128 8-bit bytes are 
written in each sector and the diskette capacity is 256,256 8-bit bytes; for double density, there are 256 
8-bit bytes written in a sector with a diskette capacity of 512,512 8-bit bytes. (For the 12-bit mode, all 
12-bit data words are loaded into the buffer and then the hardware forces zeros to add extra bits to the 
end of the buffer so that the buffer is filled.) 



4.1.1 Device Codes 

The eight possible device codes that can be assigned to the interface are 70-77. These device codes 
define address locations of a specific device and allow up to eight RX8E/RX28 interfaces to be used on 
a single PDP-8. These multiple device codes are also shared with other devices. Depending on what 
other devices are on the system, the RX8E/RX28 device code can be selected to avoid conflicts. (Refer 
to the PDP-8 Small Computer Handbook for specific device codes.) 



4-1 



The device codes are selected by switches according to Table 4-1. These switches control ac bits 6-8, 
while ac bits 3-5 are fixed at Is. The device code is initially selected to be 70. Switches 7 and 8 are not 
connected and will not affect the device selection code. The switches are all located on a single DIP 
switch package that is located on the M8357 RX8E/RX28 interface board. 



Table 4-1 Device Code Switch Selection 




Device 


















Code 


SI 


S2 


S3 


S4 


S5 


S6 


S7 


S8 


77 











1 


I 


1 


X 


X 


76 








1 


I 


1 





X 


X 


75 





1 





1 





1 


X 


X 


74 





1 


1 


1 








X 


X 


73 


1 











1 


1 


X 


X 


72 


1 





1 





1 





X 


X 


. 7! 


I 


1 











1 


X 


X 


70 


1 


1 


1 











X 


X 



O(OFF) 


1 (ON) 




SI 
S2 
S3 

S4 

S5 
S6 
S7 
S8 



































4.1.2 Instryction Set 

The RX8E/RX28 instruction set is listed below and described in the following paragraphs. When 

operating as an RX28, for the 8-bit mode, all instruction set commands are transferred in two 8-bit 

bytes. 

Description 

No Operation 

Load Command, Clear AC 

Transfer Data Register 

Skip on Transfer Request Flag, Clear Flag 

Skip on Error Flag, Clear Flag 

Skip on Done Flag, Clear Flag 

Enable or Disable Disk Interrupts 

Initialize Controller and Interface 



lOT 


Mnemonic 


67x0 




67x1 


LCD 


67x2 


XDR 


67x3 


STR 


67x4 


SER 


67x5 


SDN 


67x6 


INTR 


67x7 


INIT 



4.1.2.1 RX8E Load Command (LCD) -67x1 - This command transfers the contents of the AC to the 
interface register and clears the AC. The RX02 begins to execute the function specified in AC 8, 9, and 
10 on the drive specified by AC 7. A new function cannot be initiated unless the RX02 has completed 
the previous function. The command word is defined as shown in Figure 4-1. The command word is 
described in greater detail in Paragraph 4.1.3.1. 



00 01 02 03 04 05 06 07 08 09 10 11 













8/12 




DRV 
SEL 


FUNCTION 










MINT NOT 
USED 






r 


401 1 


JSED 


f\ 


NOT 
USED 

MA 1863 



Figure 4-1 LCD Word Format (RX8E) 



4-2 



4.1.2.2 RX28 Load Command - (First byte 67x1, second byte - 67x2) - This command transfers the 
contents of the AC to the interface register and clears the AC. The RX02 begins to execute the function 
specified in AC 8, 9, and 10 on the drive specified by AC 7. A new function cannot be initiated unless 
the RX02 has completed the previous function. The command word is defined as shown in Figure 4-2 
and is described in greater detail in Paragraph 4.1.3.1. 



12 BIT 
MODE 



8 BIT 
MODE 















1 










f 










' 00 01 02 03^ ' 04 05 


06 


07 


08 09 10 


11 










DEN 




8/12 






FUNCTION 










r 1 


? 


1 

UNIT 
SEL 
3 


4 b 6 


/ 




NOT RESERVED 
USED 


V!A!NT 
1 


TRANSFER gyQI 
BYTE 1 


















04:11 




1 


2 


3 


4 5 6 


7 




^^^ff %702 (XDR) 






















00:03 







Figure 4-2 Command Word Format (RX28) 



When operating in the 8~bit mode, the Load command is stored in two 8-bit transfers. The first 8 bits 
of the command word (shown as bits 4-1 1 in Figure 4-2) are stored; then TR is asserted and an XDR is 
performed to transfer the remaining bits of data (bit 3, DEN, and bit 2, as shown in Figure 4-2) right- 
justified. The extra bits in the second 8-bit transfer are filled with zeros. Upon completing the transfer 
of the second 8-bit byte, Done is asserted to end the function. 

41.23 Transfer Data Register (XDR) - 67x2 ™ With the maintenance flip-fiop cleared, this instruc- 
tion operates as follows. A word is transferred between the AC and the interface register. The direction 
of transfer is governed by the RX02 and the length of the word transferred is governed by the mode 
selected (8-bit or 12-bit). When Done is negated, executing this instruction indicates to the RX02 that: 

1. The last data word supplied by the RX02 has been accepted by the PDP-8, and the RX02 
can proceed, or 

2. The data or address word requested by the RX02 has been provided by the PDP-8, and the 
RX02 can proceed. 

A data transfer (XDR) from the AC always leaves the AC unchanged. If operation is in 8-bit mode, 
AC 0-3 are transferred to the interface register but are ignored by the RX02. Transfers into the AC are 
12-bit jam transfers when in 12-bit mode. When in 8-bit mode, the 8-bit word is ORed into AC 4-1 1 
and AC 0-3 remain unchanged. When the RX02 is done, this instruction can be used to transfer the 
RXES status word from the interface register to the AC. The selected mode controls this transfer as 
indicated above. 

4.1.2.4 STR - 67x3 - This instruction causes the next instruction to be skipped if the transfer request 
(TR) flag has been set by RX02 and clears the fiag. The TR fiag should be tested prior to transferring 
data or address words with the XDR instruction to ensure the data or address has been received or 
transferred, or after an LCD instruction to ensure the command is in the interface register. In cases 
where an XDR follows an LCD, the TR fiag needs to be tested only once between the two instructions. 



4-3 



4.1.2.5 SER - 67x4 - This instruction causes the next instruction to be skipped if the error flag has 
been set by an error condition in the RX02 and clears the flag. An error also causes the done flag to be 
set (Paragraph 4.1.3.6). 

4.1.2.6 SDN - 67x5 - This instruction causes the next instruction to be skipped if the done flag has 
been set by the RX02, indicating the completion of a function or detection of an error condition. If the 
done flag is set, it is cleared by the SDN instruction. This flag will interrupt if interrupts are enabled. 

4.1.2.7 INTR - 67x6 - This instruction enables interrupts by the done flag if AC 11 = 1. It disables 
interrupts if AC 11=0. 

4.1.2.8 INIT - 67x7 - The instruction initializes the RX02 by moving the head position mechanism of 
drive 1 (if drive 1 is available) to track 0. It reads track 1, sector 1 of drive 0. It zeros the error and 
status register and sets Done upon successful completion of Initialize. Up to 1.8 seconds may elapse 
before the RX02 returns to the Done state. Initialize can be generated by the program or by the 
Omnibus Initialize. 

4.1.3 Register Description 

Only one physical register (the interface register) exists in the RX8E/RX28, but it may represent one of 
the six RX02 registers described in the following paragraphs, according to the protocol of the function 
in progress. 

4.1.3.1 Command Register (Figures 4-3 and 4-4) - The command is loaded into the interface register 
by the LCD instruction for RX8E and by a load command (LCD and XDR) for the RX28 (Para- 
graphs 4.1.2.1 and 4.1.2.2). 



00 


01 


02 


03 


04 


05 


06 


07 


08 09 10 


11 












8/12 




DRV 
SEL 


FUNCTION 




V 








1 




1 






1 



NOT USED MAINT NOT 

USED 



NOT 
USED 



Figure 4-3 Command Register Format (RX8E) 





00 


01 


02 


03 


04 


05 


06 


07 


08 


09 


10 


11 




12B1TM0DE 








DEN 




8/12 






FUNCTION 












! « 


1 5 UNIT 

NOT USED SEL 

2 3 4 5 6 


1 

NOT 
7 




NOT F 
USED 


ESERVED 


1 

MAiNT 

1 


USED 




1ST BYTE 


















04:11 






8-BiTMODE ^ 




1 


2 3 4 5 6 


7 






2ND BYTE 






















00:03 







NOT USED 



Figure 4-4 Command Register Format (RX28) 



4-4 



The function codes (bits 8, 9, 10) are summarized below and described in Paragraph 4.1.4. 
Code Function 

000 Fill Buffer 

001 Empty Buffer 
010 Write Sector 
Oil Read Sector 

100 Not used {RX8E) ™ Set Density (RX28) 

101 Read Status 

110 Write Deleted Data Sector 

1 1 1 Read Error Register 

The DRV (UNIT) SEL bit (bit 7) selects one of the two drives upon which the function will be 
performed: 

AC7 = Select drive 

AC 7 = 1 Select drive 1 

The 8/12 bit (bit 5) selects the length of the data word. 

AC 5=0 12-bit mode selected 

AC 5 = 1 8-bit mode selected 

The DEN bit (bit 3) for RX28 indicates the density for the function to be performed (0 = single, 1 = 
double). The RX8E/RX28 will initiaHze into 12-bit mode. 

4 A 32 Error Code Register (Figure 4-5) - Specific error codes can be accessed by use of the read error 
code function (111) (Paragraph 4.1.4.9). The specific octal error codes are given in Paragraph 4.1.5. 



00 


01 


02 


03 


04 


05 


06 


07 


08 


09 


10 


11 



























NOT USED ERROR CODE 

Figure 4-5 Error Code Register Format (RX8E/RX28A) 

The maintenance bit (M bit) can be used to diagnose the RX8E interface under off-line and on-line 
conditions. The off-line condition exists when the BC05L-15 cable is disconnected from the RX02; the 
on-line condition exists when the cable is connected to the RX02. 

If an LCD lOT (I/O transfer) is issued with AC 4=1, the maintenance flip-flop is set. When the 
maintenance flip-flop is set, the assertion of RUN following XDR instructions is inhibited, and all 
data register transfers (XDR) are forced into the AC. The maintenance bit allows the interface register 
to be written and read for maintenance checks. The maintenance flip-flop is cleared by Initialize or by 
a Load Command lOT with AC 4 = 0. The following paragraphs describe more explicitly how to use 
the maintenance bit in an off-line mode. 

The contents of the interface buffer cannot be guaranteed immediately following the first Load Com- 
mand lOT, which sets the maintenance fiip-fiop. However, successive Load Command lOTs will guar- 
antee the contents of the interface register. The contents of the interface register can then be verified by 
using the XDR lOT to transfer those contents into the AC. 

4-5 



In addition, the maintenance flip-flop directly sets the skip flags, which will remain set as long as the 
maintenance flip-flop is set. Skipping on these flags as long as the maintenance flip-flop is set will not 
clear the flags. Setting and then clearing the maintenance flip-flop will leave the skip flags in a set 
condition. The skip lOTs can then be issued to determine whether or not a large portion of the 
interface skip logic is working correctly. 

With the maintenance flip-flop set, it can be determined if the interface is capable of generating an 
interrupt on the Omnibus. When the maintenance flip-flop is set, the done flag is set, and the interrupt 
enable flip-flop can be set by issuing an INTR lOT with AC bit 11 = 1. The combination of done and 
interrupt enable should generate an interrupt. 

The maintenance flip-flop can also be used to test the INIT lOT. The maintenance flip-flop is set and 
cleared to generate the flags, and INIT lOT is then executed. If execution of INIT lOT is internally 
successful, all of the flags and the interrupt enable flip-flop should be cleared if they were previously 
set. 

In the on-line mode, use of the maintenance bit should be restricted to writing and reading the inter- 
face register. The same procedure described to write and read the interface register in the off-line mode 
should be implemented in the on-Hne mode. Exiting from the on-line maintenance bit mode should be 
finalized by an initialize to the RX02. 

4133 RX2TA - RX Track Address (FIgwe 4«6) - This register is loaded to indicate on which of the 
77 (0-76) tracks a given function is to operate. It can be addressed only under the protocol of the 
function in progress (Paragraph 4.1.4). Bits 0-3 are unused and are ignored by the control. 

413,4 RX2SA - RX Sector Address (Figure 4-7) - This register is loaded to indicate on which of the 
26 (1-26) sectors a given function is to operate. It can be addressed only under the protocol of the 
function in progress (Paragraph 4.1.4). Bits 0-3 are unused and are ignored by the control. 

4.13,5 RX2DB - RX Data Buffer (Figure 4»8) - All information transferred to and from the floppy 
media passes through this register and is addressable only under the protocol of the function in prog- 
ress. The length of data transfer is either 8 or 1 2 bits, depending on the state of bit 5 of the command 
register when the Load Command lOT is issued (Paragraph 4.1.3.1). 

4.13.6 RX8E - RX Error and Status (Figure 4-9) - The RXES contains the current error and status 
conditions of the selected drive. This read-only register can be accessed by the read status function 
(101). The RXES is also available in the interface register upon completion of any function. The RXES 
is accessed by the XDR instruction. The meaning of the error bits is given below. 



00 01 02 03 04 05 06 07 08 09 10 11 



00 01 02 03 04 05 06 07 08 09 10 11 


















— ~ 











































^ 




^_ J 














N 
U 


OT 
SED 










0-114 


^ 


.V 


A-185a 




NOT 


USEI 


3 






1-32„ 


V 


A 1859 



Figure 4-6 RX2TA Format (RX8E/RX28) 



Figure 4-7 RX2SA Format (RX8E/RX28) 



00 01 02 03 04 05 06 07 08 09 10 11 



00 01 02 03 04 05 06 07 08 09 10 11 





































DRV 
RDY 


DD 








ID 




CRC 










^ 










12 Bl 
V10DE 


T 
E ON 


_Y 






i 


I OR 
^ODE 


12 8 


T 


M 


AT860 




NOT 


USED 




N( 


3T Ui 


5ED 


MA 1861 



Figure 4-8 RX2DB Format (RX8E/RX28) 



Figure 4-9 RXES Format (RX8E) 



4-6 



Bit No. Description 

1 1 CRC Error - The cyclic redundancy check at the end of the data field has indicated an error. 

The data must be considered invalid; it is suggested that the data transfer be retried up to 10 
times, as most data errors are recoverable (soft). 

9 Initialize Done - This bit indicates completion of the Initialize routine. It can be asserted 

due to RX02 power failure, system power failure, or programmable or bus Initialize. This 
bit is not available within the RXES from a read status function. 

5 Deleted Data (DD) - In the course of reading data, a deleted data mark was detected in the 

identification field. The data following will be collected and transferred normally as the 
deleted data mark has no further significance within the RX02. Any alteration of files or 
actual deletion of data due tp this mark must be accomplished by user software. This bit will 
be set if a successful or unsuccesful Write Deleted Data function is performed. 

4 Drive Ready - This bit is asserted if the unit currently selected exists, is properly supplied 

with power, has a diskette installed properly, has its door closed, and has a diskette up to 
speed. 

NOTE 1 
This bit is only valid for either drive when retrieved 
via a Read States function or for drive upon com- 
pletion of an Initialize. 

NOTE 2 
If the error bit was set in the RX2CS but error bits 
are not set in the RXES^ specific error conditions can 
be accessed via a read error register function. 

41.3.7 RX28 - RX Error and Status (Figure 4-10) - The RX2ES contains the current error and status 
conditions of the selected drive. This read-only register can be accessed by the read status function 
(101). The RX2ES is also available in the interface register upon completion of any function. The 
RX2ES is accessed by the XDR instruction. The meaning of the error bits is given below. 



00 


01 


02 


03 


04 


05 


06 


07 


08 


09 


10 


11 










DRV 
RDY 


DD 


DRV 
DEN 


DEN 
ERR 




ID 




CRC 



I 

RESERVED 



NOT USED RX02 



Figure 4-10 RX2ES Format (RX28) 



Bit No. Description 

1 1 CRC Error - The cycUc redundancy check at the end of the data field has indicated an error. 

The data must be considered invalid; it is suggested that the data transfer be retried up to 10 
times; as most data errors are recoverable (soft). 

10 Reserved. 

9 Initialize Done - This bit indicates completion of the Initialize routine. It can be asserted 

due to RX02 power failure, system power failure, or programmable or bus Initialize. This 
bit is not available within the RX2ES from a read status function. 



4-7 



Bit No. Description 

8 RX02 - This bit is asserted if an RX02 system is being used. 

7 DEN ERR - This bit indicates that the density of the function does not agree with the drive 

density. Upon detection of this error the control terminates the operation and asserts error 
and done. 

6 DRV DEN - This bit indicates the density of the diskette in the drive selected (0 = single, 1 

= double). 

5 Deleted Data (DD) - In the course of reading data, a deleted data mark was detected in the 

identification field. The data following will be collected and transferred normally, as the 
deleted data mark has no further significance within the RX02. Any alteration of files or 
actual deletion of data due to this mark must be accomplished by user software. This bit will 
be set if a successful or unsuccessful write deleted data function is performed. 

4 Drive Ready - This bit is asserted if the unit currently selected exists, is properly supplied 

with power, has a diskette installed properly, has its door closed, and has a diskette up to 
speed. 

NOTE 1 
This bit is only valid for either drive when retrieved 
via a read status function or for drive upon com- 
pletion of an Initialize. 

NOTE 2 
If the error bit was set in the RX2CS but error bits 
are not set in the RX2ES5 specific error conditions 
can be accessed via a read error code function. 

4.1.4 Function Code Description 

The RX8E/RX28 functions are initiated by means of the Load command described in Paragraphs 
4.1.2.1 and 4.1.2.2. The done flag should be tested and cleared with the SDN instruction in order to 
verify that the RX8E/RX28 is in the Done state prior to issuing the command instruction. Upon 
receiving a command instruction while in the Done state, the RX8E/RX28 enters the Not Done state 
while the command is decoded. Each of the eight functions summarized below requires that a strict 
protocol be followed for the successful transfer of data, status, and address information. The protocol 
for each function is described in the following sections. A summary table is presented below. 







AC 






Octal 


g 


9 


10 


Function 














Fill Buffer 


2 










Empty Buffer 


4 





1 





Write Sector 


6 





1 




Read Sector 


10 


1 








Not Used (RX8E), Set Density (RX28) 


12 


1 







Read Status 


14 


1 


1 





Write Deleted Data Sector 


16 


1 


1 




Read Error Register 



NOTE 
AC bit 1 1 is assumed to be in the above octal codes 
since AC bit 11 can be or 1. 



4-8 



41.4,1 Fill Buffer (000) - For RX8E this function is used to load the RX02 sector buffer from the 
host processor with 64 12-bit words if in 12-bit mode or 128 8-bit words if in 8-bit mode. For RX28 this 
function loads the sector buffer in 12-bit mode with 64 12-bit words for single density or 128 12-bit 
words for double density; in the 8-bit mode, the buffer is loaded with 128 8-bit bytes for single density 
or 256 8-bit bytes for double density. This instruction only loads the sector buffer. In order to complete 
the transfer to the diskette, another function, write sector, must be performed. The buffer may also be 
read back by means of the empty buffer function in order to verify the data. 

Upon decoding the fill buffer function, the RX02 will set the transfer request (TR) flag, signaling a 
request for the first data word. The TR flag must be tested and cleared by the host processor with the 
STR instructions prior to each successive XDR lOT (Paragraph 4.1.2.4). The data word can then be 
transferred to the interface register by means of the XDR lOT. The RX02 next moves the data word 
from the interface register to the sector buffer and sets the TR flag as a request for the next data word. 
The sequence above is repeated, until the sector buffer has been loaded (64 data transfers for 12-bit 
mode or 128 data transfers for 8-bit mode). After the 64th (or 128th) word has been loaded into the 
sector buffer, the RX2ES is moved to the interface register, and the RX02 sets the done flag to indicate 
the completion of the function. Therefore, it is unnecessary for the host processor to keep a count of 
the data transfers. Any XDR commands after Done is set will result in the RX2ES status word being 
loaded in the AC. The sector buffer must be completely loaded before the RX8E/RX28 will set Done 
and recognize a new command. An interrupt would now occur if Interrupt Enable were set. 



4J.4 J Empty Buffer (001) - This function moves the contents of the sector buffer to the host proces- 
sor. Upon decoding this function RX2ES bits are cleared and the TR flag is set with the first data word 
in the interface register. This TR flag signifies the request for a data transfer from the RX8E/RX28 to 
the host processor. The flag must be tested and cleared; then the word can be moved to the AC by an 
XDR command. The direction of transfer for an XDR command is controlled by the RX02. The TR 
flag is set again with the next word in the interface register. The above sequence is repeated until all 
words or bytes have been transferred, thus emptying the sector buffer. The done flag is then set after 
the RX2ES is moved in the interface register to indicate the end of the function. An interrupt would 
now occur if Interrupt Enable were set, 

NOTE 
The empty buffer function does mot destroy the con- 
tents of the sector buffer. 



4.L4.3 Write Sector (010) - This function transfers the contents of the sector buffer to a specific track 
and sector on the diskette. Upon decoding this function, the RX8E/RX28 clears the RX2ES and sets 
the TR flag, signifying a request for the sector address. The TR flag must be tested and cleared before 
the binary sector address can be loaded into the interface register by means of the XDR command. The 
sector address must be within the limits 1-328. 

The TR flag is set, signifying a request for the track address. The TR flag must be tested and cleared; 
then the binary track address may be loaded into the interface register by means of the XDR com- 
mand. The track address must be within the limits 0-1 14g. 

The RX02 tests the supplied track address to determine if it is within the allowable limits. If it is not, 
the RX2ES is moved to the interface register, the error and done flags are set, and the function is 
terminated. 



4-9 



If the track address is legal, the RX02 moves the head of the selected drive to the selected track, locates 
the requested sector, transfers the contents of the sector buffer and a CRC character to that sector, and 
sets Done. Any errors encountered in the seek operation will cause the function to cease, the RX2ES to 
be loaded into the interface register, and the error and done flags to be set. If no errors are encoun- 
tered, the RX2ES is loaded into the interface register and only the done flag is set. 

NOTE 
The write sector fiiiictioii does not destroy the con- 
teats of the sector buffer, 

4AAA Read Sector (Oil) - This function moves a sector of data from a specified track and sector to 
the sector buffer. Upon decoding this function, the RX8E/RX28 clears RX2ES and sets the TR flag, 
signifying the request for the sector address. The flag must be tested and cleared. The sector address is 
then loaded into the interface register by means of the XDR command. The TR flag is set, signifying a 
request for the track address. The flag is tested and cleared by the host processor and the track address 
is then loaded into the interface register by an XDR command. The legality of the track address is 
checked by the RX02. If illegal, the error and done flags are set with the RX2ES moved to the interface 
register and the function is terminated. Otherwise, the RX02 moves the head to the specified track, 
locates the specified sector, transfers the data to the sector buffer, computes and checks CRC for the 
data. If no errors occur, the done flag is set with the RX2ES in the interface register. If an error occurs 
anytime during the execution of the function, the function is terminated by setting the error and done 
flags with RX2ES in the interface register. A detection of CRC error results in RX2ES bit 1 1 being set. 
If a deleted data mark was encountered at the beginning of the desired data field, RX2ES bit 5 is set. 

4AA3 Set Media Density (100) for RX28 only - This function causes the entire diskette to be reas- 
signed to a new density. The density bit (bit 3 RX2CS) indicates the new density of the diskette. The 
control reformats the diskette by writing new data address marks (double or single density) and zero- 
ing out all data fields on the diskette. Before executing the command the control will look for a 
protective key word of 01001001 (ASCIFF). 

The control starts at sector 1, track and reads the header information, then starts a write operation, 
writing the new data address mark and data field as well as CRC characters. If the header information 
is damaged, the control will abort the operation and assert DONE and ERROR. 

This operation takes about 15 seconds and should not be interrupted. If for any reason the operation is 
interrupted, an illegal diskette has been generated which may have data marks of both densities. This 
diskette should again be completely reformatted. 

41.4.6 Maintenance Read Statiis (101) for RX28 only - This function updates the drive ready and 
drive density status of the selected drive, clears the INIT DONE bit, updates the Unit Sel, possibly sets 
the density error bit and leaves the remainder of the RX2ES unchanged. The drive density is updated 
by loading the head on the selected drive (without changing head and reading position) with the first 
header and data mark that randomly appears under the head. The control will then generate the 
appropriate number of shift pulses which will transfer the RX2ES (error and status) register over the 
interface. Upon completion of the RX2ES transfer, the control asserts Done to complete the oper- 
ation. 

41.4.7 Read Status (101) for RX8E only - Upon decoding this function, the RX02 moves the RXES 
to the RX8E interface register and sets the done flag. The RXES can then be read by the transfer data 
register (XDR) command. The bits are defined in Paragraph 4.1.3.6. 

NOTE 
The average time for this function is 250 ms. Exces- 
sive use of this function will result in substantially 
reduced throughput. 

4-10 



41.4.8 Write Deleted Data Sector (110) - This function is identical to the write data function except 
that a deleted data mark is written prior to the data field rather than the normal data mark (Paragraph 
1.5.3.2). RX2ES bit 5 (Deleted Data) will be set in the interface register upon completion of the 
function. 



4.1.4.9 Read Error Code Function (111) - The read error code function can be used to retrieve explicit 
error information upon detection of the error flag. Upon receiving this function, the RX02 moves an 
error code to the interface register and sets Done. The interface register can then be read via an XDR 
command and the code interrogated to determine which type of failure occurred (Paragraph 4.1.5). 

NOTE 
Care should be exercised in the use of this function. 
The program must perform this function before a 

read status because the error register is always modi- 
fied by a read status function. 



4.L4.10 Power Fail ~ There is no actual function code associated with power fail. When the RX02 
senses a loss of power, it will unload the head and abort all controller action. All status signals are 
invalid while power is low. 

When the RX02 senses the return of power, it will remove Done and begin a sequence to: 

1. Move drive 1 head position mechanism to track 0. 

2. Clear any active error bits. 

3. Read sector 1 of track 1 of drive into the buffer. 

4. Set Initialize Done bit of the RX2ES, after which Done is again asserted. 

There is no guarantee that information being written at the time of a power failure will be retrievable. 
However, all other information on the diskette will remain unaltered. 

INIT lOT is a method of aborting an incomplete function (Paragraph 4.1.2.7). 

4.L5 Error Recovery 



4.1.5.1 RX8E - There are two error indications given by the RX8E system. The read status function 
(Paragraph 4.1.4.7) will assemble the current contents of the RXES (Paragraph 4.1.3.6), which can be 
sampled to determine errors. The read error register function (Paragraph 4.1.4.9) can also be used to 
retrieve explicit error information. 

The results of the read status function or the read error register function are in the interface register 
when Done sets, indicating the completion of the function. The XDR lOT must be issued to transfer 
the contents of the interface register to the PDP-8's AC. 

NOTE 
A read status function is not necessary if the DRV 
READY bit is not going to be interrogated because 
the RXES is in the interface register at the com- 
pletion of every function. 



4-11 



The error codes for the read error register function are presented below. 

Octal 

Code Error Code Meaning 

0010 Drive failed to see home on Initialize. 

0020 Drive 1 failed to see home on Initialize. 

(K)30 Found home when stepping out 10 tracks for INIT 

0040 Tried to access a track greater than 77 

0050 Home was found before desired track was reached 

(K)70 Desired sector could not be found after looking at 52 headers (2 revolutions) 

0110 More than 40 ^s and no SEP clock seen 

0120 A preamble could not be found. 

0130 Preamble found but no I/O mark found within allowable time span 

0150 The header track address of a good header does not compare with the desired track. 

0160 Too many tries for an IDAM (identifies header) 

0170 Data AM not found in allotted time 

0200 CRC error on reading the sector from the disk. No code appears in the ERREG. 

0210 All parity errors 

0220 Self diagnostic error on Initialize 

0240 Density Error 

41.5.2 RX28 - There are two error indications given by the RX28 system. The read status function 
will assemble the current contents of the RX2ES which can be sampled to determine errors. The read 
error register function can also be used to retrieve explicit error information. 

The results of the read status function or the read error register function are in the interface register 
when Done sets, indicating the completion of the function. The XDR lOT must be issued to transfer 
the contents of the interface register to the PDP-8's AC. 

NOTE 
A read status function is not necessary if the DRV 
RDY bit is not going to be interrogated because the 
RX2ES is if! the interface register at the completion 
of efer y function* 

The error codes for the read error register function are presented below. 

Octal 

Code Error Code Meaning 

(X)10 Drive failed to see home on Initialize. 

(X)20 Drive 1 failed to see home on Initialize. 

WHO Tried to access a track greater than 76 

0050 Home was found before desired track was reached. 

(X)70 Desired sector could not be found after looking at 52 headers (2 revolutions). 

01 10 More than 40 iis and no SEP clock seen 

0120 A preamble could not be found. 

0130 Preamble found but no ID mark found within allowable time span 

0150 The header track address of a good header does not compare with the desired track. 

0160 Too many tries for an IDAM (identifies header) 

0170 Data AM not found in allotted time 

0200 CRC error on reading the sector from the disk 

0220 R/W electronics failed maintenance mode test. 

0240 Density error 

0250 Wrong key word for Set Media Density command 

4-12 



4.L6 RX8E Programming Examples 



41,6 J Write/Write Deleted Data/Eead Functions - Figure 4-1 1 presents a program for implement- 
ing a write, write deleted data, or a read function with interrupts turned off (lOF). The first 3 steps 
preset the PTRY, CTRY, and STRY retry counters, which are set at 10 retries but can be changed to 
any number. Starting at RETRY, the program tests for 8- or 12-bit mode, type of function, and drive. 
Once the command is loaded, the program waits in a loop for the controller to respond with transfer 
request (TR). When TR is set, the sector address is loaded and the AC is cleared. The program loops 
while waiting for the controller to respond with another TR. When TR is reset, the track address is 
loaded and the AC is cleared again. The program loops to wait for the Done condition. 



When the done flag is set, the program checks for an error condition, indicated by the error flag being 
set. If the AC=OWO, the error is a seek error; if bit 1 1 of the AC is set, the error is a CRC error. Error 
status from the RXES is saved and tested to determine the error (Paragraph 4.1.3.6). The RXES will 
not include the select drive ready bit. If a parity error is detected, the program increments and tests the 
PTRY retry counter. If a parity error persists after 10 tries, it is considered a hard error. If 10 retries 
have not occurred, a branch is made to RETRY and the sequence is repeated. 



After a parity test, the program tests to see if the CRC error bit is set. If a CRC error is detected, the 
program increments and tests the CTRY retry counter. If a CRC error persists after 10 retries, it is 
considered a hard error. If 10 retries have not occurred, a branch is made to RETRY and the sequence 
repeated. 



A seek error is assumed if neither a CRC nor a parity error is detected. An Initialize (INIT) instruction 
is performed (Paragraph 4.1.2.8). During a write or write deleted data function, the sector buffer must 
be refilled because INIT will cause sector 1 of track 1 of drive to be read, which will destroy the 
previous contents of the sector buffer. The instruction sequence for a fill buffer function is not included 
in Figure 4-11, but is presented in Figure 4-13. After the system has been initialized, the program 
increments and tests the STRY retry counter. If a seek error persists after 10 tries, it is considered a 
hard error. If 10 retries have not occurred, a branch is made to RETRY and the sequence repeated. 



4J J.2 Empty Buffer Fiinctioii - Figure 4-12 shows a program for implementing an empty buffer 
function with interrupts turned off (lOF). The first instruction sets the number of retries at 10. A 2 is 
set in the AC to indicate an Empty Buffer command and the command is loaded. When TR is set, the 
program jumps to EMPTY to transfer a word to the BUFFER location. A jump is made back to loop 
to wait for another TR. This process continues until either 64 words or 128 bytes have been emptied 
from the sector buffer. When Done is set, the program tests to see if the error bit is set. If the error bit is 
set, the program retries 10 times. If the error persists, a hard parity error is assumed, indicating a 
problem in the interface cable. 



4.1.6.3 Fill Buffer Fiinctioii - Figure 4-13 presents a program to implement a fill buffer function. It is 
very similar to the empty buffer example. 

4-13 



6701 


lCD»6701 


6702 


XOR«6702 


6703 


STR56703 


6704 


SER»5704 


6705 


SDN»6705 


6 706 


!MTR=6736 


6707 


p^IT = 6707 



1 /PROGRAMMING E^^AMPLES FQR ^hE RX8/RX01 F'LEXIBLE DISKETTE 

2 / 

3 /THE FOLLOWING ARE RX01 |0T CODE DEFINITIONS 

4 / 

5 /THE STANDARD IQT DEVICE CODE IS 670- 

6 / 

/lOT TO LOAD THE COMMAND. (ACJ IS TH| COMMAND 
/lOT TO LOAD OR READ TwE TRANSFER REGISTER 
/lOT TO SKIP QN A TRANSFER REQUEST FLAG 
/IQT TO SKIP ON AN ERROR FLAG 

il 6705 SDN*6705 /lOT TO SKIP ON THE DONE FLAG 

12 6706 !MTR=6736 / {AC) = INTERRUPT ENABLE OFF/ (AC) « 1 MEANS ON 

i3 6707 p^IT = 6707 /IQT TO iNlTfiiLIAE THE RXS/RXSl SUBSVSTEM 

14 / 

^5 /THE FOLLOWING IS A PROGRAHMING EXAMPLE OF THE PROTOCOL REQUIRED 

16 / 

,7 /TO WRITE, WRITE DELETED OATa, OR REAU AT 3ECToR '♦S" (THE CONTENTS OF PROGRAM 

18 / 

19 /^OCaTION SECTOR? OF TRACK "T" (THE CONTENTS OF PROGRAM i.0CAT|ON TRACK) 

20 / 

21 /IN 8 OR 12 BIT MODE 

22 / 

?3 0230 1254 START, TAD KMl0 / "13 

2^ 0231 3255 OCA PTRy /PARITY lETRy COUNTER 

25 0202 1254 TAO KMi0 

26 0233 3236 OCA CTRY /CRC RET^y COUNTER 

27 0204 1234 TAO KM10 

28 0205 3297 OCA STRy /SEEK R£?RT COUNTER 

29 / 

30 /WRITE, WRITE DELETED DATA, OR READ 

31 / 

32 0206 1260 RETRY, TAO MODE /0 |F 12«B|T, 100 |F 9«BlT 

33 0207 1261 TAD COMMAND / 4 JP WRITE, 14 If WRITE DELETED 

34 /OATi, 0^ 6 IF READ 

35 0212 1262 TAO UNIT / 2 \f UNIT 0, 20 |F UNIT 1 

36 0211 6701 LCD /|0T 67X1 TO LOAD THE COMMAND 

37 / 

38 /WAIT FOR THE TRANSFER REQUEST Fi_AG THEN TRANSFER THE SECTOR ADDRESS 

39 / 

40 0212 6703 STR /|01 67X3 Tq 

41 0213 5212 JMP ,-1 /WAIT FQi^ TR&NSFER REQUEST FLAG 

42 0214 1263 TAD SECTOR / 1 TO 32(0CTAL) 

43 0213 6702 XQR /lOT TO LOAD SECTOR 

44 0216 7200 CLA /CLA BECAUSE lOT XDR DOESN'T 

45 / 

46 /-Akil FOR THE TRANSFER REQUEST FLAG THEN TRANSFER THE TRACK ADDRESS 

47 / 

48 0217 6703 STR /|0T 67X1 TO 

49 0220 5217 JMP ,-1 /HAJT FOU TRANSFER REQUEST 

50 0221 1264 TAO TRACK / 3 TO 114(0CTAL) 

51 0222 6702 XQR /lOT TO LOAD TRACK 

52 0223 7200 CL* /CLA BECAUSE IQT XDR DOESN'T 

53 /THE SECTOR AND TRACK ADDRESSES HAVE BEEN TRaNSFERRLO TO THE RX31 VU THE XDR lOT 

54 / 

55 /HA|T FOR THE OONE FLAG AND CHECK FQR ANV ERRORS 

56 / 

57 /IF THE FUNCTION HAS COMPLETED SUCCESSFULLT (NO ERROR FLAG) THEN HALT 

58 / 

59 0224 6705 SPN /|0T 67X3 TO 

60 0225 5224 JHP ,-1 /WAIT FQH DONE FlAQ 

61 0226 6704 SER /lOT 67X4 SAMPLES ERROR FLAG 

62 0227 7402 HLT / OK » COMPLETED 

63 / 

64 /THE ERROR FLAG IS SET 

65 / 

66 /THE CONTENTS OF THE TRANSFER REGISTER IS THE ERRO« STATUS 

67 / 

68 /IF TRANSFER REGISTER BITS 10, AnO 11 « THEN SOME TYPE 0^ SEEk ERRQR HaS 0CCURE0# 

69 /IF TRANSFER REGISTER 8|T n = 1 THEN A CRC ERROR MAS OCCU^EO, 

70 /IF TRANSFER REGISTER BIT 10 s 1 THEN A PARITY ERROR HAS OCCURED 

71 / 

72 0230 6702 XQR /GET CONTENTS 0^ TR {ERROR STATUS) 

73 0231 3263 OCA ASTaTUS /ANO SAVE 

74 0232 7305 CLL ClA 1 AC RAL / 2 

75 0233 0265 ANO aSTaTUS /TEST FQS PaS|TY ERROR 

76 0234 7650 SNA CLA /SKIP IF RARJTy ERROR 

77 0235 5241 JMP TcRC /NOT 4 PARITY ERROR - MAYBE CRC 

78 / 

79 /A PARITY ERRqR HAS OCCUREO 

80 / 

31 /INCREMENT AND TEST THE PARITY ERROR RETRY CqUnTER PRoSR&h LOCATION " ^TRY " 

32 / 

83 /ANO RETRY TM£ " COmHANO " UNTIt IHl PARITY ERRQR RECOVERS 

84 / 

35 /QR UNTIL THE PTRY COUNTER OVERFlOWS TO 

36 / 

87 0236 2255 ISZ PTRY 

88 0237 5206 JMP RETRY /RETRY THE COMHAND 

89 024-3 7402 HLT /HARD PAS|TY ERROR 

90 / 

91 /THl ERROR FLAG IS SET BUT THE ERROR IS NOT A PARITY ERROR 
9 2 / 

93 /TEST FOR A CRC ERRqR 

94 / 

95 0241 7301 ^CRC, CLl Ct* lAC / 1 

96 0242 J265 ANO ASTATUS /TEST fO^ A CRC ERROR 

97 0243 765a SNA CLA /SKIP |F A C«C ERROR 

98 0244 5250 JMP SEEK /NOT A C«C - MUST BE A SEEK 



Figure 4-11 RX8E Write/ Write Deleted Data/Read Example (Sheet 1 of 2) 

4-14 



99 /A CRC ERROR HAS OCCURED 

100 / 

101 /INCREHENT AND Test the CRC ERROR ReTHY counter program location " CTRY " 

102 / 

103 /AND RETRY ThE COHHAND UNTIL ThE CRC ERROR RECOVERS 

104 / 

105 /OR UNTIL The CTRY counter OVERFLOWS TO 

106 / 

107 0245 2236 !S2 CTRY 

10B i246 5206 UMF RETRY /RETRY THE COMMAND 

139 0247 7402 HLT /HARD CRC ER«OR 

110 ■' / 

111 /THE ERROR FLAG IS SET 

112 / 

113 /THE ERROR IS CN0T3 A PARITY ERROR AND IS CNOTJ A CRC ERRQR 

114 / 

115 /THEREFORE IS MUST BE A SEEK ERROR 
115 / 

117 / (CONTENTS OF THE TRANSFER REGISTER aiTS 10, AND 11 8 0) 

iia / 

119 0250 6707 SEEK, INH /lOT 67X7 To INITIIlUE 

120 / 

121 /INCREMENT AND TEST ThE SEEK ERROR RETRY COUNTER PROGRAM LOCATION " STRY " 

122 / 

123 /AND RETRY ThE COMMAND UNTIL ThE SEEK ERROR RECOVERS 

124 / 

125 /OR UNTIL The CTRY COUNTER OVERFLOWS TO 

126 / 

127 0251 2257 ISi STRy 

128 0252 3206 JM? RETRY /RETSY THE COMMAND 

129 0253 7402 HL? /HARD SEEK ESROR 

130 /THE FOLLOWING PROGRAM LOCATIONS ARE REFERENCED WITHIN TMIS EXAMPLI 

131 / 

132 0254 7770 KHl@i «l® 

133 / 

134 /THE FOLLOWING 3 PROGRAM LOCATIONS ARE THE ERROR RETSY COUNTERS 

135 / 

136 0253 0300 PTRY, /PARl?Y ERRQS RETRY COUNTER 

137 0256 0000 CTRy, /CRC ERROR RITRV COUNTER 

138 0257 3300 STRY, /SEEK ERROR RETRY COUNTER 

139 / 

140 /PROGRAM LOCATION " MODE " CONTAINS A @ IF 12-@|T MODE, OR 

141 /CONTAINS A 105? IF 8-SIT MODE 

142 / 

143 0260 0000 HOOE, / OR 130 

144 / 

145 /PROGRAM LOCATION " COMMAND " CONTAINS ThE COMMAND TO 9E ISSUED VIA ThC lCO IQT 

146 / 

147 /WRITE {4)i WRITE OElETED DATA (l4), QR READ (6), OR EhPTY BUFFER (2) 

148 / 

149 0261 iJ000 CQMHANOi / 4, 1,4, qR |, QR 2 

150 / 

151 /PROGRAM LOCATION " UNfT " CONTAiNS THE UNiT DESiCNATjON 

152 / 

153 /UNiT (0), OR UNiT 1 {205 

154 / 

155 §262 0000 UNIT, / 0, OR 20 

156 / 

157 /PROGRAM LOCATION " SECTOR « CONTAINS THE SECTOR ADDRESS (1 TQ 32 OCTAL) 

158 / 

159 0263 0200 SECTORi ^ / 1 TO 32 OCYAt 

160 / 

161 /PROGRAM LOCATION " TRACK " CONTAINS THE TRACK ADDRESS CS Tq 114 OCTAlJ 

162 / 

163 0264 0000 TRACK* Z / 3 TO 114 OCTAL 

164 / 

165 /PROGRAM LOCATION " ASTaTUS " CONTAINS THE CONTENTS Of TME TRANSFER REGISTER 

166 / 

167 /AT THE DETECTION OF AN ERROR (ERROR FlaG « 1) WHICH CORRESPONDS Tq THC 

168 / 

169 /ERROR STATUS 

170 / 

171 / « IF SEEK ERROR, 1 IF CRC ERROR. 2 |F PARITY ERROR 

172 / 

173 0263 3000 ASTATUSi /STATUS AT ERROR 



Figure 4-11 RX8E Write/Write Deleted Data/Read Example (Sheet 2 of 2) 



4-15 



220 /THE rOLlOWlNG IS A PROGRAMMING EKAMPUe OF PROTOCOU REQUIRED TO 

229 / 

230 /EMPTY THE SECTOR BUFFER OF 64 12«BIT WORDS (12 SIT MODE), OS 

231 / 

232 /EMPTY THE SECTOR BUFFER OF 128 S«BIT BYTES (@ BfT MOD!:) 

233 / 

234 0312 1254 EENTRY, TAD KMi0 / S TRYS TO EMPTY ThE SECTOR iUFFER 

235 0313 3255 DCA PTRy /PARITY CR^OS RETRY COUNTER 

236 0314 1377 ESETuP, TAD (BUFFER«1) /PROGRAMS OaTA BUFFER 

237 0315 3010 OCA Ai0 /AUTO INDEX (REGISTER 10 

238 0316 1260 TAD MODE / i If lf«Bl?, 100 IF 8 BIT 

239 0317 1261 TAD COHMANO / 2 MEANS EMPTY BUFFER 

240 0320 6701 LCD /lOT TO ISSUC THE COMMAND 

241 / 

242 /WAIT FOR A TRANSFER REQUEST FLAG BEFQWE TRANSFERRINS OATa Tq ThE PROGRAMS 

243 / 

244 /QATA BUFFER FROM ThE RX31 SECTOR BUFFER 

245 / 

246 /WAIT FOR A DONE FLAG TO |NOiCATE THE COMPlETjON QF THE EMPTY BUFFfR COMMAND Pi|OR TO 

247 / 

248 /TESTING THE ERROR FlAG 

249 / 

250 0321 6703 ELOOP* STR /TEiT FO^I TR FLAG 

251 0322 7410 SK^ /TR NOT SET, TEST fPOR DONE FLAG 

252 0323 5333 JMP EM^TY /TR FLAG SET 

253 0324 6705 SON /TEST FOS DONE FLAG 

254 032§ §274 JMF btuuF /NOT T^i 0^ DONE YCT 

255 / 

256 /THE DONE ^L^G iS SET 

257 / 

258 /TEST For Any errors (ONl"^ error possible is a PARITY ERROR) 

259 / 

260 0326 6704 SER /TEST FQ^ THE ERRQR FLAG 

261 0327 7402 NLT /NO ERRORS - OK 

262 / 

263 /INCREMENT AND TEST THE PARITY ERROR RETRY PRQGRAM LOCATION " PTRY " 

264 / 

265 /AND RETRY THE COMMAND UNTIl THE ERROR RECOVER! 

266 / 

267 /OR UNTIL THE PTRY COUNTER OVERFLOWS TO 

268 / 

269 0330 2255 ISi ^TRY 

270 0331 5314 JMF ESETUP /RETRY TQ EMPTY TH£ SECTOR BUFFER 

271 0332 7402 HLT /HARD PAilTY ERROR 

272 / 

273 /THE TRANSFER REQUEST FLAG IS SET 

274 / 

275 /TRANSFER DATA TO THE PROGRAMS DATA BUFFER FROM THE RX01 SECTOR BUFFER 

276 / 

277 0333 6702 EMPTY, XQR /FRQM TH? RX0i SECTOR BUFFER 

278 0334 3410 OCA I A10 /TO THE PROGRAMS DATA BUFFER 

279 0335 5321 JHP ELOOP /LOOP UNTIL THE DONE FLAG SETS 

280 0377 0377 

3400 PAGE 

281 /THE FOLLOWING PROGRAM LOCATIONS ARE RESERVED FOR THE PROGRAMS DATA BUFFER 

282 / 

283 0400 0000 BUFFER, 

284 0600 ®BUFrER*200 

285 i 



Figure 4-12 RX8E Empty Buffer Example 



4-16 



174 






175 






176 






177 






178 






179 






180 




0010 


181 






182 


0266 


1234 


183 


0267 


3255 


184 


0270 


1377 


185 


0271 


3010 


186 


0272 


1260 


187 


i273 


6701 


188 






189 






190 






191 






192 






193 






194 






195 






196 






197 


0274 


6703 


198 


0271 


7410 


199 


0276 


5306 


200 


0277 


6705 


201 


0300 


5274 


222 






203 






204 






205 






206 






207 


0301 


6704 


208 


0302 


7402 


209 






210 






211 






212 






213 






214 






2l5 






216 


§303 


2255 


217 


§304 


5270 


218 


i30S 


7402 


219 






220 






221 






222 






223 






224 


0306 


1410 


225 


0307 


6702 


226 


0310 


7200 


227 


0311 


5274 



/THE FOUUOWING IS A PROGRAMMING E«AMPt.E OF PROTOCOL REQUIRED TO 
/ 

/FILL THE SECTOR BUFFER WITH 64 l2-eiT WORDS (12 BIT MODI). 8R 
/ 

/FILL THE SECTOR BUFFER WITH 128 8-BIT BYTES (8 ilT hQOE) 

/ 

A10»10 

/ 

FENTRY, TAD Kh10 / 8 TRYS TO riLL THE SECTOR BUFFER 

DCA PTRY /PARITY ERSOt RETRY COUNTER 

SETUP# TAD (BUFFER-i) /PROGRAMS OATA BUFFER 

OCA Aie /AUTO IN9EX REGISTER i0 

TAO MODE / If I2«il?, 100 IF 8 BIT 

LCD /lOT TO ISSUE THE COMMAND 

/ 

/WAIT FOR A TRANSFER REQUEST Fi.AG BEFQRE TRANSFERRING DA?A F^OM THE PROGRAMS 

/ 

/QATA BUFFER TO THE RX0X SECTOR BUFFER 

/ 

/WAIT FOR A DONE FLAG TO INDICATE THE COMPLETION OF THE FILL BUFFER COMMAND PRIOR TO 

/ 

/TESTING THE ERROR FLAG 

/ 

LOOP, STR /TEST FOR TR FLAG 

SKF /TR NOT lET, TEST fOR DONE FLAG 

JMP FILL /TR FLAG SET 

SON /TEST rOi DONE F^AC 

UMP LOOP /NOT Tt, OR 50NE YfT 

/ 

/THE DONE FLAG IS SET 

/ 

/TEST FOR ANY ERRORS (ONLY ERROR POSS|BlE IS A PARITY ERRqR) 

/ 

SE« /TEiT FO^ THE ERROR FI.AG 

HLT /NO ERRORS - OK 

/ 

/INCREMENT AND TEST THE PARITY ERROR HETRY PROGRAM LOCATION " PTRY « 

/ 

/AND RETRY THE COMMAND UNTR ThE ERROR RECOVERS 

/ 

/QR UNTIL The PTRY COUNTER OVERFLOWS TO 

/ 

iSi PTRY 

jM^ SETyP /RETRY TO FILL THE SECTOR BUFFER 

HLT /HARD ^AilTY ERROR 

/ 

/THE TRANSFER REQUEST FLAG IS SET 

/ 

/TRANSFER DATA rRQM ThE PRQcRAMS DaTa BUffER Tq ThE RX@l SECTOR BUfpER 

/ 

Fill. tad I A10 /VIA AUTQ index register 10 

XOR /TO THE 1X01 SECTOR BUFFER 

CL* /CLA BECAUSE lOT XOR DOESN'T 

UM^ LOOP /LOOP UNTIL THE DONE FLAG SETS 



Figure 4-13 RX8E Fill Buffer Example 



41.7 RX28 Programmiiig Examples 

Figures 4-14, 4-15, and 4-16 are programming examples for write, write deleted data or read functions, 
for fill buffer functions, and for empty buffer functions, respectively. These examples are very similar 
to the RX8E programming examples described in Paragraph 4.1.6. Basically, there are two differences 
between the IIX8E and RX28 examples. First, for the RX28 when a command is transferred in the 8- 
bit mode of operation, it is transferred in two 8-bit words using an XDR to transfer the second 
command word (see location 0225 in Figure 4-14); second, for the RX28, there is no parity error check 
as there is in the RX8E; instead there is a density error check. 



4-17 



1 /P'»DSRftMlN5 EXAMPLES P0« 1^*1 RJfZS/S FlEXlStE DISKETTE 

2 / 

5 /TME FDtLOwINS ARf «X0l lOT C03E ngFlNlTlQ^IS 

a / 

5 /THE STANOiRO lOT DEVIEE C30E IS b75» 

b / 

7 iT2l LCOb b70l /IDT T3 tOAO THE c3"«aND, (AC) IS THE CQMHANO 

e ^72? XPUb fc7P2 /I3T T3 uO&O OR WgAQ THE TRANSPE^t RESTSTEI? 

q 6735 STi»s 6703 /I3T T3 SKI? ON TRANSFER REQUEST PlAS 

la b73« SERs b7Pia /I3T T3 SKT? ON ERROR FLAG 

U b735 S0*J8 67s»5 /I3T T3 StJ^ PN DONE FLAG 

52 b73b TmTRb 675*6 /(ftC)a2 IMTEbruPT ENABLE DFF/(AC)8l M|An3 ON 
13 b727 Tt^ITs 6707 /I3T T3 INITJAUIZ? THE RX SUSSTSTEh 

H / 

15 /T'iE F3LL0«slN3 IS A PRQGRA^IMG ESA-^PlE OF THE PROTOCOL REQUIRED 

ib / 

17 /T3 dtlTg, WRITE DELETED O&Ta, OR READ AT SECTOR "S" (THE CONTENTS OF PROGRAM 

18 / 

19 /1.3CATI0N "SECTOR") OF TRACK ^T" (THE CONTENTS OF PROGRA'' LOCATION 

?e / 

?1 /"TRftC<"> TN 8 0^ I? SIT H30E. 

a? / 

23 3230 s??*?! 

?a ?!235» tgbb START, TAn <m12 /GET RETRY CONSTANT 

2S 0281 527^1 OCA CtRT /SET UP CRC RETRY COUNT 

2b 3232 I2bb TAfi <m10 

27 f.2?'3 3271 OCA StR* /SET yP SEEK HETRY COj^T 

2S / 

29 /i«RlTE, WRITE DELETED DATA. 3R REA3 

30 / 

31 diZa b735 SON /m&ke SuRE DRIVE READY FOR US 

32 ^aas sgaa jmp ,,1 /if not wait 

33 ?23b 12^ RETRY, TAD *loDE /» IF 12»I3IT HOOE, 103 IF g-STT MoPE 
3o 0227 S27a Tad FyNCUN /GET FUNCTION CODE 

55 fiaii" 1275 TAP DRivEP /GET DRIVE PARAMETERS} UNIT, S, 

3b /DENSITY 

37 6321} J?7b DCA CO'^*'AN0 /SAWg ENTfRE COMHANQ 

3» 7>il3 l27b TAP CO^'HanD /GET COmMaMD 

39 i"<213 {»72l LCD /L3A0 COHmaND REGISTER 

Os^ P21S 127b T&D CQ'^^ianO /get CQHHaVD 

41 ^215 3247 AND <iia /siAS IT 8»SIT MODE 

5? 02lb M52 SNA /!? YE3 SKIP ANO 00 8-3IT PROTOCOL 

93 ?ei7 522fa JMP ^AlTTR /I? 12»eiT DONE LCD PR3T0C0L 

Hi 0223 7i3b CLL RTL /GET UPPER « SITS OF 

85 ^ii\ JUb RTu /COMMAND w3RD TO L0».'ER 

Hb 5^222 77!3« RAL /8 BITS OF AC 

07 0223 fe783 STR /»<AlT FOR A TRANSFER REQUEST 

a? 022a 5223 jMg ,„i /LOOP UNTfL TR, 

aq ^225 b7a2 xnR /Givg SECOND COhmand w3Rn 

50 / 

51 /WAIT PUR THAmSFEq request FtA3 TMgM TRANSFER SECTOR A30RESS 
5? / 

53 »2?fe !>733 i».AfTTsj, STR /T3T Tf) SKIP UN TRANSFER REQUEST 
5ft P227 522b JHP .-I /L30P UNTIL T«, 

55 v^iii' i?T7 TAP Sector /i to 32 octal) 

5b ^23t b7(S2 inR /L3A0 the SECTOR 

57 ?23? 7?(5? CLA /CLEAR AC 

5i / 

59 /rtAIf ?0R TRANSFER REQUEST FlaS fwgN TRANSFER TRACK ADDRESS 

b0 / 

bj ^253 b7?5 STB /S<IP ON TRANSFER REQUEST 

b? <«23fl S?S3 JMB ,^1 /L'lOP UNTIL TM 

b3 ^255 13a? TAP TiiAC* /^ To H« (OCTAL) 

ba 725b b7?2 KDR /l3Ao THt TRACK 

bS i'2!7 7j?!2 CLA /CLEAR AC 

bb / 

b7 /T-4F CJ^^'ANO 9R3T5C3L HAS 3E£W CD*<PLET6n, ^0*1 

bP / 

b9 /«Air fns oo^g AMI C^ECk F3R E'R^RS 

7k^ I 

T\ 5523^ b735 SON /13T TO S<IP ON OONE FL'AG 

72 VigS! 5?a^ JMP ,.1 /L30P UnTil OUNE 

73 vt?iJ? b73a 3ER /I3T TO SxIP ON ERROR FLAG 
N ?!285 7a3g MLT /NO ERRORS SO HALT 

75 / 

7b /T-if E?ROR PLA5 Is SET 

77 / 

Tp /HE F-*ROW STATUS IS L>TCATFO In! THf TRANSFER REGISTER 

79 / 

I't IX^ STATUS s I 1-KiH CRC ERR09 3CCUREP 

^I /I^ STATUS « 2? Tm£v OE^iSITY flROR dCCURtO 

92 /!*■ 5T4TUS a 3 T-^r** SFEx ERRDR OCCJRED 

93 / 

9a isgaa b732 XOR /GET CONTg<^TS OF TRANSFER REGISTER 

95 /STATUS AT OONE 

8b j;23S 5321 OCA AsTaT'JS /AVO SAVE IT 

S7 ?2ab 72131 lAC /-^ASK FOR CRC ERROR BIT 

36 i?s237 asai AND A5TATUS /IF AC NOT EQUAL TO ZERO CRC 

89 <?25{» 7|,52! SNA C^A /ERROR OCCJREO SO SKIP 

'iis Z25i 5?55 J^^P 3e^S|T i\f &c e 3 THg^j CHECK FQB oENSITY ERRROR 

H ?252 22'^ ISZ CtRY /<EEP COUNT OF RETRIES IF s 13 THEN SKIP 

R2 ^253 523b Jmp R|TRY t\f RETRIES -sl^ THEN 03 IT AGaIm 

95 ^25a 7932 hlT /halt 

Figure 4-14 RX28 Write/ Write Deleted Data/Read Example 

(Sheet 2 of 2) 



4-18 



95 /T«4f E^ROH WAS ^3t A C^IC 83 CMEC? PfQR WRUi^S OEKtSITY. IP OE»jSITY ESROR 

96 / 

97 /D3ES EXIST TmEM hAuT, IF TMIS ESRDR OCCURS IT COULO JJST hAv^S 

Qo / 

/8EE*' 3EC&U8E «E F3*IG0T TO SIT T><E •'IGHT nENSITY In TmE COmhavD *loRn 

/ 

/09 IT COULO BE The wROMS TlSKETTg rtas BEE"* INSERTED IM THE O^IVE OR 

/ 

/IT CnUlO BE SOME 3TMER ^Eft33s SJT WE SHCiguD «<N0^ wh&T CAUSED IT 

/ 



/ 

/T-^E E*«OR **UST -IaVE BEE^ A SEEK ERROR IF ^E GOT THIS PAR, 



98 
99 

lag! 

123 
I0a 
las /9EP3RE »«E PRDCElO 

07 / 

08 P25«5 ridJ DE^SIT, CLA ClI- UC RTL /AC b a 

39 0256 Tal2 RTR /AC a 20, «1ASK F0» QEmSITy E1.-J0R 

185 0257 3521 AND AS^ATuS /l^ STATUS WO^D IP SET SKIP 

ll ^Shgi 7«93 9ZA /IP NOT DENSITV ERROR MUST 8E SEES ERROR 

1? B261 yii^i MJ.T /MftUT WITH DENSITY ERROR BIT SET IN AC 

13 

U 

15 f 

16 /I5SJE AN INITIALIZE TO DRIVE 30 tiE START PROM TRACS S 

117 / 

118 /A^D T^IY &SATN 

119 / 

I2i^ ?2b? 6727 SEEK, I^JfT /lOT TO INITIALIZE Rt 

121 02bl ag'l ISI 3T«Y /SEEP COUnT OF SEEK ER90RS 

122 02ia S2i6 JMP !|gT^V /RETRY COM*IAS!t) i0 TI^ES 
125 S'2i5 'aaa MLT /THEN HALT 

12a / 

125 /CONSTANTS USED Sy Tn|5 C05F 

126 / 

127 ia266 'T'2 KHl^, »li 

128 82iT 2122 Kia?i, l^ff? 
29 / 

3p /E«R3R RETRY cOU'^TERS 

3l / 

3? 02T?. iJid^ CT3Y. t^ /C9C ERROR WETRY COUNTER 

33 ^?^l 3a2Z ST^Y, I' /SEF-H ERMnR RETRt CDJ^JTER 

5Q 02T2 8S22 fTRY, /FILL AND EMPTY BJFFE^ RfTYM COi^^Tf" 

35 / 

/P^OSR*'^ LOCATION "'^OOE" CT^TaJnS ?! IF I2-9IT MQDt , OR li^*i IF d-:llT m^joE 



/ 

/LOCATION "FUMCUNI" CONTalNS a IF WRITF, 1« IF wRfTE 5ElETET OATi, 
/». tr aFfth Fil<jrTTn>J 



136 

137 

15b «!2T5 aa2? '^fJSE 

139 

18? 

581 /b IF READ PlNCTIoM 

192 / 

IflJ ^27a 32!?^ FiiMCJN, n 

194 / 

1S5 /LlC&TIDN "QRIVE"" "^AS BIT ASSIGM^EMTS 

1«6 / 

107 / V'B JNIT 'J^ SInSLE 5fMSITY 

lae / 2S»8 JvIT 1 SINSLE lEsSTTY 
/ a0S»e JnIT i?! DOUBLE JE'JSIfY 

15C^ / fl2^» J^rr I "SOUSLE 3I^*SITY 

I5i / 

152 £2^5 2222 DHlvEP, ^ 

53 / 

5a /lSTATIH'j "Cn^MAM') is /*HfRF The assEmplfU command is STORED 

155 / 

I5b !S2'h 272? CO-^waN^, S? 

57 / 

56 /L3riT£0N "SECTO?" '«JST BE 1 T3 I? JCTAl 

159 / 

IbZ 4127? 2313? SECTOR, ^ 

h\ f 

62 /LOCATION "TRACK" •'JST BE Tk To Iia OCTAL 

163 / 

I6a 7S?i? ?a2? Tt;AC<, ^ 
1(>5 
16b 

167 . - - . . __ _ 

168 /REGISTER «mEs "Sn^E" IS SET 



/ 

/L3C4TinN SASTATJ'^" TS USEl Tn STORE THE CONTENTS OF HE STATjS 
/REGISTER IF AN ErR'JR OCCURS. TME STATUS IS IN ThE TRA'-iSFFfc' 



^3'>l 2322 ASTaTjS, ? 



Figure 4-14 RX28 Write/Write Deleted Data/Read Example 
(Sheet 2 of 2) 



4-19 



m 






172 






m 






Ifa 






11^5 




aaif 


lU 






If? 


S33a 




178 


0333 




l"» 


0334 




1B0 


Bin 




181 


338|> 




132 


8337 




195 


9)313 




19« 


asu 




1S5 


§312 




iSb 


0313 




16T 


S«31a 




IBe 


?!S15 




16«) 


0316 




190 


?317 




191 


Qii/ 




19? 


0321 




193 


P32? 




19a 


f»323 




195 


5!32a 




19t> 


0325 




197 


BS2b 




I9e 






199 






S^K 






2it 






Iti 






?35 






asa 






225 






idb 






?a7 


;«327 




??8 


?!33r 




239 


«S5t 




21f 


^332 




?li 


?J15 




Hi 






113 






2U 






215 






Hb 






in 


?3Sa 


!>785 


?ie 


?5 35 


F8?2 


219 






?2? 






221 






Hi 






213 






22a 






225 






22t> 


S'ilb 


22^2 


227 


fc357 


53««» 


iib 


Pi38f' 


M32 


229 






2 Si-, 






231 






232 






233 






23s 


?3ai 


lau 


235 


2382 


1722 


23b 


f«383 


7233 


237 


®3aa 


5S27 



TAR 


(SUFFgsJ^I) 


OCft 


Ali 




TAD 


M3DE 


T40 




SUIvEP 


OCA 




CD'^'^ANO 


tAD 




Cq-^manO 


LCD 






T&fi 




Cd'^'iano 


&Nn 




<f ad 


SNA 


cu* 




JMS9 




I.03P 


TAn 




CO'^^'AMO 


CtL 


fft 




btl 






fJAL 






ITS 






JMP 




..1 


SOS 






tLA 







/TMf F31.L0WINB IS A PR0e!?&^HlN3 EXAMPLE Fq PROTOCOL RE3UIRE0 TO 

/ 

/FILL 7HE SECfOH SJ^^FES 

AiaslP 

/ 

FE^Tty, TAD K*«1P / S TMYS TO FitL TmE SErToR Su^f^E^ 

OCA ETRV /fiiROW RET«¥ COU^TgR 

8ETU», TaO (5UFFg^«|) /PROGRAMS OATa BUFFER 

/AJTO TNOEK RESISTFR 10 
/0 IF 12-8IT, 100 IF 8 RIT 
/r,ET DENSITY 

/STORE &SSE>49i.|D CQMNftNn 
/GET COMMAND TD AC 
/ISSUE COHHAK'o TO RX 

/gct saved co^i^a^o 

/*4as< for 8-bit «o0e 

/ff 6-8it mode set do b-mooe p»«otocul 

/IF 12«BIT HODI GO STRAIShT TO ^ILL LOOP 

/GET SAVED COlMANO k^O^O 

/GET a MSB'S (SITS M,l,2,3) OF 

/C3MMAKID WORD 00w»J TO ThE 

/a LSB's CBiTs 8,9,ia,n) of aC 

/I3T TO 5«IP OV TRiK'SFER READY 
/|F TR NOT SET LDOP UMTJL IT HOES 
/ISSUE SECOND CO'^MA^j:) wfiRo 
/CLEAR THE ftC 4^1 DO FILL LOOP 

/ 

/WAIT FOR A TRANSFER RESUEST F^SS BF-FORf- T^ANSFfRWI NG JiTi FRQM ThE PROGRAMS 

/ 

/DATA iSuFFfR TO ThE RS3| SfCTD^ lUFFER 

/ 

/^klT s^na 4 n3ME Fi.45 TD I^nfCATE the COMRLETION of the PILL auFFfW CD^-^ANa P-JjfH 

/ 

/TESTING THF ESR3R FLAG 

/ 

L03P, 5TR /TEST FOR TR FuAG 

SKP /TR *40T SET, TEST FOR OO^E ^LAG 

JHP FILL /TR FLAT, SET 

SON /TEST FOR DOME FLAG 

JMP L30P /mST TR, OR OO^E YET 

/ 

/T-4E fjONi Ft,&3 IS SET 
/ 

/TEST FOR ANV ERRriRS 
/ 

SfeR /TEST FOR THE EW^DR F,_Af, 

NLT /»<3 ERRORS « 0< 

/ 

/I^iC^E'<ENT AND TEsT ThE ER^IO* ^IETRY PHUGNa"^ i^UCATIO^ "ETRY" 
/ 

/A^if) RETRY The CStflA^n j^TTL T«4E ERROR RECOVERS 
/ 

/O^ JnTIl the ETiv COU«^TEH Os/F^FLD^sS TO i 
/ 

ISf ETRY 

JHP SETu9 /RETRY TO FILL THE SECTOR SUFFE"^ 

"^LT /hard parity E^iROR 

/ 

/THF TRANSFER RE3jEST F1.AG IS SET 
/ 

/T?A^5FER DATA F^0*< THE ^RDG^^A'^S OftfA BUFFER TO THE RX01 SECTOR iU^^EB 
/ 
FILL. T&o I AJ« /VIA 4'JTO I^OEiC REGISTER |0 

«0R /TO THE RX01 SECTOR sjjFfEr 

CL& /CL* BECAUSE UT XD* DOESN'T 

JMP LDOP /tDOP U^iTlL The OOnE FL*5 SETS 



Figure 4-15 RX28 Fill Buffer Example 



4-20 









/T"4E 


rSllOwlNS IS A PRQSRAMHI 


N5 EXAMPLE OF PROTOCOL RE8UlRfO TO 








/ 




















/E«PTv TNg SECTOR lyrrgR 












?3«5 




fENT^y, TAD 


K*«IS 








/ B TRY3 TO EMPTV THE SECTOR BUFFER 




0386 






OCA 


ETi»Y 








/ERROR RETRY COUNTER 




HSiT 




ESITJP, TAO 


(BUFFft-n 








/P'^OSRAMS OATA BUFFER 




03Se 






OCA 


Ali 








/AJTO INDEX RESISTER |0 




8351 






TAR 


MODE 








/ a IF 12.8IT, 100 IF 8 BIT 




0333 






TAO 


FUNCJn 








/ 2 HEANS E»^PTY BUFFER 




@35l 






TAO 


ORIVEP 








/GET DENSITY 




83Sa 






OCA 


CO'^'^AWO 








/STORE ASSEMBLED COWHAND 




0335 






TAO 


CO'^'IA^D 








/SET COMMAND T3 AC 




P>336 






LCD 










/ISSUE COMMAND TO RX 




§337 






TAO 


C0'^*'&N0 








/SET SAVED COMMAND 




03i?. 






AND 


<i33 








/MASK FOR 6«SIT MODE 




03b| 






SNA 


ClA 








/|F a-8lT MODE SET DO 8«iMoOE PROTOCOL 




03^2 


577b* 




JHP 


EtOOP 








/IF le-BIT MOOS SO STRAIShT TO EMPTY LOOP 




03&3 






TAO 


C0''*'*N0 








/GET SAVED COMMAND WORD 




03M 






CLL 


^Tl 








/SIT 4 MSB'S (BITS 0,1,2,3) OF 




03b5 






STL 










/C3MMAN0 wORO DOWN TO TmE 




03i6 






iAL 










/a LSB'S (BITS S,9,10,U) O'^ AC 




i)3fe7 






ST8I 










/I3T TO SKIP O'^ TRANSFER READY 




03^0 






JMP 


,»1 








/IF TR NOT SET LOOP UnTU IT DOES 




0371 






IDS 










/ISSUE SECOND COMMAND «nRD 




03Tg 






CLA 










/CL€A» THE AC AND 00 E^P^Y LOOP 




03T3 


577b» 




JMP 


Ei.QO^ 








/GET OVER TO NEXT PASF 




03T& 




















P377 


3430 


P*SE 




















/ 




















/w&lT 


FOU 4 


TiANSFE^ i^EOUEST 


FL*S 


§£FO»fi TRANSFERRING 3ATA TO ThE PRORRAMS 








/ 




















/0&T& 


SUFFgS 


FRc* TNf ^xai 


SEcTOfi 


SUFFER 








/ 




















/^AI? 


fon k 


ODME FLAG TO I^OICftTE 


THE COMP!.£TION OF Th£ EhpTV SuFFER cni«ftNO PklO 








/ 




















/TISTIMG TH! 


E^939 FlaS 










0«30 




EL 30^ 


, Bin 










/TEST FOR TR FLAG 




0a3i 






S«P 










/TR NOT SET, TEST pOR OfiMF ^LAG 




iaa? 






JHP 


mPTf 








/TR FLAG SET 




04^3 






SON 










/TEST FOR DONE FLAG 




093a 






JMP 


£lQO«» 








/n3T TR, OR OO'^E YET 






/T-8E 


n3»^E FLAG IS SET 
















/ 




















/TEST 


FOS ANV ER«qRS 
















/ 
















0a2S 


i>7aa 




SE3 










/TEST FOR THE ERROR ^il^r. 




i^ib 


7832 




HLT 










/NO E«RORS « 3< 








/ 




















/I^C 


EiENT AN5 TEsT THE gR?0? 


^ETRV 


PBOGRA'^ LOCATID^J "gTRV 








/ 




















/A'JO 


«»ETI?Y THE C3MX&ND UNTit 


T^E 


ERROR RECOVERS 








/ 




















/ni jsjflt THE ET?y Cau^TgH 


O^E'FLO<iS 


TU ^ 








/ 
















jsaa? 


g777' 




tsz 


ETS7 












aai;^ 


577s,' 




JMP 


ESETJ? 








/RETRY TO EMPTY THf SECTOR BUFFER 




?4il 


792!2 




HUT 










/HARD ERROR 








/ 




















/TME 


TiANSfTES ^E3ul3T Fl&S 


IS 


SET 












/ 




















/TtA'iSFEB DATA 73 T^g Pf?0G9A^ 


S DATA 


BUFFER FROM THE Rx31 SECTf^R BUFFER 








/ 
















@ai2 


1722 


EMPT* 


, t09 










/PROM THE RX^l SECTOR 8UFFEP 




aais 


3U3 




OCA 


1 All 








/TO THE PROGRAMS DATA PuFFfH 




i^ie 


5120 




jmp 


eloop 








/LOOP UNTIL THE nONE FLAG SETS 
























S5?6 


ai«7 


















0577 


3272 




!»A58 


















/TME 


F3LlOt^lNS ?»!?0S«?A*5 LOC 


iTfOMS 


iRE 


RESERVED FDR THE PROGRAMS DATA BUFFER 








/ 
















fs&ae 


aa^0 


BU^FE^, ?! 
















12S0 




*8UFFE-^*902 


















S 













Figure 4-16 RX28 Empty Buffer Example 



4-21 



4.i.8 Restrictions and Programming Pitfalls 

A set of 11 restrictions and programming pitfalls for the RX8E is presented below. 

1. When performing the following sequence of instructions, interrupts must be off. 

SKP 
JMP 

SDN 

JMP 



(done) 
^ (fill or empty buffer) ^^— 

If interrupts are not off, the following sequence of events will occur. Assume interrupts are 
enabled and the RX8E issues an interrupt request just before the SDN instruction; the SDN 
instruction will be executed as the last legal instruction before the processor takes over. 
However, since the done flag is cleared by the SON instruction, the processor will not find 
the device that issued the interrupt. 

2. The program must issue an SER instruction to test for errors following an SDN instruction. 



3. For maximum data throughput for consecutive writes or reads in 8-bit mode, interleave 
every three sectors; in 12-bit mode, interleave every two sectors. (This of course depends on 
program overhead.) 

4. When issuing the lOT XDR at the end of a function to test the status, the instruction AND 
377 must be given because the most significant bits (0-3) contain part of the previous com- 
mand word. 

5. If an error occurs and the program executes a read error register function (111) (Paragraph 
4.1 .4.9), a parity error may occur for that command. The error code coming back would not 
be for the original error in which the read error register function was issued, but for the 
parity error resulting from the read error register function. Therefore, check for parity error 
with the read status function (101) before checking for errors with the read error register 
function (111). 



6. The SEL DRV RDY bit is present only at the time of the read status function (101) for 
either drive, or at completion of an Initialize for drive 0. 

7. It is not necessary to load the drive select bit into the command word when the command is 
Fill Buffer ((WO) or Empty Buffer (001). 

8. Sector Addressing: 1-26 or 1-328 (No sector 0) 
Track Addressing: 0-76 or 1-1 Hg 

9. If a read error register function (111) is desired, the program must perform this function 
before a read status function (101), because the content of the error register is always modi- 
fied by a read status function. 

4-22 



10. The instructions STR, SDN, SER also clear the respective flags after testing so that the 
software must store these flags if future reference to them is needed after performing one of 
these instructions. 

11. Excessive use of the read status function (101) will result in drastically decreased throughput 
because a read status function requires between one and two diskette revolutions or about 
250 ms to complete. 



42 RXll AND RXVll PROGRAMMING INFORMATION 

This section describes device registers, register and vector address assignments, programming specifi- 
cations, and programming examples for the RXll and RXVll interfaces. 

All software control of the RXl 1/RXVl 1 is performed by means of two device registers: the command 
and status (RXCS) register and a multipurpose data buffer (RXDB) register. These registers have been 
assigned bus addresses (Paragraph 4.2.1) and can be read or loaded, with certain exceptions, using any 
instruction referring to their addresses. 

The RX02, which includes the mechanical drive(s), read/write electronics, and mCPU controller, con- 
tains all the control circuitry required for implied seeks, automatic head position verification, and 
calculation and verification of the CRC; it has a buffer large enough to hold one full sector of diskette 
data (128 8-bit bytes). Information is serially passed between the interface and the RX02. 



A typical diskette write sequence, which is initiated by a user program, would occur in two steps: 

1. Fill Buffer - A command to fill the buffer is moved into the RXCS. The Go bit (Paragraph 
4.2.2.1) must be set. The program tests for transfer request (TR). When TR is detected, the 
program moves the first of 128 bytes of data to the RXDB. TR goes false while the byte is 
moved into the RX02. The program retests TR and moves another byte of data when TR is 
true. When the RX02 sector buffer is full, the Done bit will set, and an interrupt will occur if 
the program has enabled interrupts. 

2. Write Sector - A command to write the contents of the buffer onto the disk is issued to the 
RXCS. Again the Go bit must be set. The program tests TR, and when TR is true, the 
program moves the desired sector address to the RXDB. TR goes false while the RX02 
handles the sector address. The program again waits for TR and moves the desired track 
address to the RXDB, and again TR is negated. The RX02 locates the desired track and 
sector, verifies its location, and writes the contents of the sector buffer onto the diskette. 
When this is done, an interrupt will occur if the program has enabled interrupts. 

A typical diskette read occurs in just the reverse way: first locating and reading a sector into the buffer 
(read sector) and then unloading the buffer into core (empty buffer). In either case, the content of the 
buffer is not valid if Power Fail or Initialize follows a fill buffer or read sector function. 



4.2.1 Register and Vector Addresses 

The RXCS register is normally assigned Unibus address 177170 and the RXDB register is assigned 
Unibus address 177172. The normal BR priority level is 5, but it can be changed by insertion of a 
different priority plug located on the interface module. The vector address is 264. 

4-23 



4.2.2 Register Description 

42.2.1 RXCS - Command and Status ( 177170) - Loading this register while the RX02 is not busy and 
with bit 0= 1 will initiate a function as described below and indicated in Figure 4-17. Bits 0-4 are write- 
only bits. 



15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 



FUNCTION 



ERROR 



NOT USED 



TR 



RX 

INIT 



DONE 

INT UNIT 

ENB SEL 



GO 



Bit No. 



1-3 



8-13 
14 



Figure 4-17 RXCS Format (RXll, RXVll) 

Description 

Go - Initiates a command to RX02. This is a write-only bit. 

Function Select - These bits code one of the eight possible functions listed below and de- 
scribed in Paragraph 4.2,3. These are write-only bits. 



Code 

000 
001 
010 

on 

100 
101 

no 
111 



Function 

Fill Buffer 

Empty Buffer 

Write Sector 

Read Sector 

Not used 

Read Status 

Write Deleted Data Sector 

Read Error Register 



Unit select - This bit selects one of the two possible disks for execution of the desired 
function. This is a write-only bit. 

Done - This bit indicates the completion of a function. Done will generate an interrupt when 
asserted if Interrupt Enable (RX2CS bit 6) is set. This is a read-only bit. 

Interrupt Enable - This bit is set by the program to enable an interrupt when the RX02 has 
completed an operation (Done). The condition of this bit is normally determined at the time 
a function is initiated. This bit is cleared by Initialize and is a read/write bit. 

Transfer Request - This bit signifies that the RXll or RXVl 1 needs data or has data avail- 
able. This is a read-only bit. 

Unused 

RX Initialize - This bit is set by the program to initialize the RXll or RXVll without 
initializing all devices on the Unibus. This is a write-only bit. 

CAUTION 
Loading the lower byte of the RXCS will also load 
the upper byte of the RXCS. 



4-24 



15 



Upon setting this bit in the RXCS, the RXll or RXVll will negate Done and move the 
head position mechanism of drive 1 (if two are available) to track 0. Upon completion of a 
successful Initialize, the RX02 will zero the error and status register, set Initialize Done, and 
set RXES bit 7 (DRV RDY) if unit is ready. It will also read sector 1 of track 1 on drive 0. 

Error - This bit is set by the RX02 to indicate that an error has occurred during an attempt 
to execute a command. This read-only bit is cleared by the initiation of a new command or 
an Initialize (Paragraph 4.2.6). 



4.2.2,2 RXDB - DMa Buffer Register (177172) - This register serves as a general purpose data path 
between the RX02 and the interface. It may represent one of four RX02 registers according to the 
protocol of the function in progress (Paragraph 4.2.3). 

This register is read/write if the RX02 is not in the process of executing a command; that is, it may be 
manipulated without affecting the RX02 subsystem. If the RX02 is actively executing a command, this 
register will only accept data if RXCS bit 7 (TR) is set. In addition, valid data can only be read when 
TR is set, 

CAUTION 
Violation of protocol in maiiipiilation of this register 
may cause permanent data loss, 

4.2,23 RXTA - RX Track Address (Figure 4«-18) ~ This register is loaded to indicate on which of the 
77 (114g) tracks a given function is to operate. It can be addressed only under the protocol of the 
function in progress (Paragraph 4.2.3). Bits 8-15 are unused and are ignored by the control. 



15 


14 


13 


12 


11 


10 


09 


08 


07 


06 


05 


04 


03 


02 


01 


00 
















,___™„ 















! 





NOT USED 



0-114, 



Figure 4-18 RXTA Format (RXl i/RXV! I) 

4.2.2,4 RXSA ™ RX &ctor Address (Figure 4«19) - This register is loaded to indicate on which of the 
26 (328) sectors a given function is to operate. It can be addressed only under the protocol of the 
function in progress (Paragraph 4.2.3). Bits 8-15 are unused and are ignored by the control. 



15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 














































L ) 








f^OT 


USED 












1-32s 







Figure 4--19 RXSA Format (RXl 1/RXVl 1) 

4.2.2,5 EXDB - EX Data Byffer (Figure 4-20) - All information transferred to and from the floppy 
media passes through this register and is addressable only under the protocol of the function in prog- 
ress (Paragraph 4.2.3). 



15 


14 


13 


12 


11 


10 


09 


08 


07 


06 


05 


04 


03 


02 


01 


00 



































Figure 4-20 RXDB Format (RXl 1/RXVI 1) 



4-25 



42,2,6 RXES - RX Error and Status (Figure 4-21) - This register contains the current error and 
status conditions of the drive selected by bit 4 (Unit Select) of the RXCS. This read-only register can be 
addressed only under the protocol of the function in progress (Paragraph 4.2.3). The RXES content is 
located in the RXDB upon completion of a function. 



15 


14 


13 


12 


11 


10 


09 


08 


07 


06 


05 


04 


03 


02 


01 


00 
























DEN 
ERR 










I 








J 


1 

UNIT 




1 
DD 








1 
ID 


1 






NOT USED 






CRC 



RDY DEN 



Figure 4-21 RXES Format (RXl I, RXVl I) 



RXES bit assignments are: 

Bit No, Description 

CRC Error - A cyclic redundancy check error was detected as information was retrieved 

from a data field of the diskette. The RXES is moved to the RXDB, and Error and Done are 
asserted. 



Initialize Done ~ This bit is asserted in the RXES to indicate completion of the Initialize 
routine which can be caused by RX02 power failure, system power failure, or programmable 
or Unibus Initialize. 



Density Error - This bit is asserted to indicate the density of the function in progress does 
not match the drive density. Upon detection of this error the control terminates the oper- 
ation and Error and Done are asserted. 

NOTE 
Bits 4 and 5 are asserted for the occtirreiice of double 
density wheii the system is RXOl -compatible. 



Drive Density - This bit indicates the density of the diskette in the drive selected. When 
asserted, double density is indicated. 



Deleted Data Detected - During data recovery, the identification mark preceding the data 
field was decoded as a deleted data mark (Paragraph 1.5.3.2). 



4-26 



7 Drive Ready - This bit is asserted if the unit currently selected exists, is properly supplied 
with power, has a diskette installed correctly, has its door closed, and has a diskette up to 
speed. 

NOTEl 
The drive ready bit is only valid when retrieved via a 
read status function or at completion of Initialize 
when it indicates status of drive 0. 

NOTE 2 
If the error bit was set in the RXCS but error bits are 
not set in the RXES^ specific error conditions can be 
accessed via a read error register function (Para- 
graph 423,7), 

8 Unit Select -» Drive is selected if this bit is '*0"; drive I is selected if this bit is a "1." 

4.2.3 Function Codes 

Following the strict protocol of the individual function, data storage and recovery on the RXll and 
RXVl 1 occur with careful manipulation of the RXCS and RXDB registers. The penalty for violation 
of protocol can be permanent data loss. 

A summary of the function codes is presented below: 



000 


Fill Buffer 


001 


Empty Buffer 


010 


Write Sector 


oil 


Read Sector 


100 


Not used 


101 


Read Status 


110 


Write Deleted Data Sector 


111 


Read Error Register 



The following paragraphs describe in detail the programming protocol associated with each function 
encoded and written into RXCS bits 1-3 if Done is set. 

4.2.3.1 Fill Buffer (000) - This function is used to fill the RX02 buffer with 128 8-bit bytes of data 
from the host processor. Fill buffer is a complete function in itself; the function ends when the buffer 
has been filled. The contents of the buffer can be written onto the diskette by means of a subsequent 
write sector function, or the contents can be returned to the host processor by an empty buffer func- 
tion. 

RXCS bit 4 (Unit Select) does not affect this function since no diskette drive is involved. When the 
command has been loaded, RXES, OUT, and Done are cleared. When the TR bit is asserted, the first 
byte of the data may be loaded into the data buffer. The control then clears TR and after supplying the 
appropriate number of shift pulses to store the data, again asserts TR. The same TR cycle will occur as 
each byte of data is loaded. The RX02 counts the bytes transferred; it will not accept less than 128 
bytes and will ignore those in excess. Any read of the RXDB during the cycle of 128 transfers is 
ignored by the RXl 1/RXVl 1. When the complete buffer has been filled, the control asserts Done. 

4.2.3.2 Empty Buffer (001) - This function is used to empty into the interface the buffer of the 128 
data bytes loaded from a previous Read Sector or Fill Buffer command. This function will ignore 
RXCS bit 4 (Unit Select) and negate Done. For this function, TR and shift pulses are generated in the 
same manner as for the fill buffer but the buffer is emptied. 



4-27 



When TR sets, the program may unload the first of 128 data bytes from the RXDB. Then the 
RX 1 1/RXVl 1 again negates TR. When TR resets, the second byte of data may be unloaded from the 
RXDB, which again negates TR. Alternate checks on TR and data transfers from the RXDB continue 
until 128 bytes of data have been moved from the RXDB. Done sets, ending the operation. 

NOTE 
The empty buffer function does not destroy the con- 
tents of the sector buffer. 



4.233 Write Sector (010) - This function is used to locate a desired track and sector and write the 
sector with the contents of the internal sector buffer. The initiation of this function clears TR and 
Done. 

When TR is asserted, the program must move the desired sector address into the RXDB, which will 
negate TR. When TR is again asserted, the program must load the desired track address into the 
RXDB, which will negate TR. If the desired track is not found, the RXll/RXVll will abort the 
operation, move the contents of the RXES to the RXDB, set RXCS bit 15 (Error), assert Done, and 
initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set. 

TR will remain negated while the RX02 attempts to locate the desired sector. If the RX02 is unable to 
locate the desired sector within two diskette revolutions, the RXl 1/RXVl 1 will abort the operation, 
move the contents of the RXES to the RXDB, set RXCS bit 15 (Error), assert Done, and initiate an 
interrupt if RXCS bit 6 (Interrupt Enable) is set. 

If the desired sector is successfully located, the RXl 1/RXVl 1 will write the 128 bytes stored in the 
internal buffer followed by a 16-bit CRC character that is automatically calculated by the RX02. The 
RXl 1/RXVl 1 ends the function by asserting Done and initiating an interrupt if RXCS bit 6 (Interrupt 
Enable) is set. 

NOTE 1 
The contents of the sector buffer are not valid data 
after a power loss has been detected by the RX02. 
The write sector function, however, will be accepted 
as a valid function, and the random contents of the 
buffer will be written, followed by a valid CMC. 

NOTE 2 
The write sector function does not destroy the con- 
tents of the sector buffer. 



4.23,4 Read Sector (Oil) - This function is used to locate a desired track and sector and transfer the 
contents of the data field to the mCPU controller sector buffer. The initiation of this function clears 
RXES, Done, and OUT. 

When TR is asserted, the program must load the desired sector address into the RXDB, which will 
negate TR. When TR is again asserted, the program must load the desired track address into the 
RXDB, which will negate TR. 

If the desired track is not found, the RXl 1/RXVl 1 will abort the operation, move the contents of the 
RXES to the RXDB, set RXCS bit 15 (Error), assert Done, and initiate an interrupt if RXCS bit 6 
(Interrupt Enable) is set. 

4-28 



TR and Done will remain negated while the RX02 attempts to locate the desired track and sector. If 
the RX02 is unable to locate the desired sector within two diskette revolutions after locating the 
presumably correct track, the RXl 1/RXVl 1 will abort the operation, move the contents of the RXES 
to the RXDB, set RXCS bit 15 (Error), assert Done, and initiate an interrupt if RXCS bit 6 (Interrupt 
Enable) is set. 

If the desired sector is successfully located, the control will attempt to locate a standard data address 
mark or a deleted data address mark. If either mark is properly located, the control will read data from 
the sector into the sector buffer. 

If the deleted data address mark was detected, the control will assert RXES bit 6 (DD). As data enters 
the sector buffer, a CRC is computed, based on the data field and CRC bytes previously recorded. A 
non-zero residue indicates that a read error has occurred. The control sets RXES bit (CRC Error) 
and RXCS bit 15 (Error). The RXl 1/RXVl 1 ends the operation by moving the contents of the RXES 
to the RXDB, sets Done, and initiates an interrupt if RXCS bit 6 (Interrupt Enable) is set. 

423.5 Read Status ( 101) ™ The RX 1 1/RXVl 1 will negate RXCS bit 5 (Done) and begin to assemble 
the current contents of the RXES into the RXDB. RXES bit 7 (Drive Ready) will reflect the status of 
the drive selected by RXCS bit 4 (Unit Select) at the time the read status function was given. All other 
RXES bits will reflect the conditions created by the last command. RXES may be sampled when 
RXCS bit 5 (Done) is again asserted. An interrupt will occur if RXCS bit 6 (Interrupt Enable) is set. 
RXES bits are defined in Paragraph 4.2.2.6. 

NOTE 
The average time for this ftinetloi is 250 ms. Exces- 
sive use of this function will result in substantially 
reduced throughputs 

42.3.6 Write Sector with Deleted Data (110) - This operation is identical to function 010 (write 
sector) with the exception that a deleted data address mark precedes the data field instead of a stand- 
ard data address mark (Paragraph 1.5.3.2). 

4.2.3.7 Read Error Code Function (111) - The read error code function can be used to retrieve explicit 
error information provided by the ^CPU controller upon detection of the general error bit. The func- 
tion is initiated, and bits 0-6 of the RXES are cleared. Out is asserted and Done is negated. The 
controller then generates the appropriate number of shift pulses to transfer the specific error code to 
the interface register and completes the function by asserting Done. The interface register can now be 
read and the error code interrogated to determine the type of failure that occurred (Paragraph 4.2.6). 

NOTE 
Care should be exercised in the use of this function, 
since under certain conditions^ erroneous error infor« 
mation may result (Paragraph 4.2.5). 

42.3.8 Power Fail - There is no actual function code associated with Power Fail. When the RX02 
senses a loss of power, it will unload the head and abort all controller action. All status signals are 
invalid while power is low. 

When the RX02 senses the return of power, it will remove Done and begin a sequence to: 

1. Move drive 1 head position mechanism to track 0. 

2. Clear any active error bits. 

3. Read sector 1 of track 1 of drive into the sector buffer. 

4. Set RXES bit 2 (Initialize Done) (Paragraph 4.2.2.6) after which Done is again asserted. 

5. Set Drive Ready of the RXES according to the status of drive 0. 

4-29 



There is no guarantee that information being written at the time of a power failure will be retrievable. 
However, all other information on the diskette will remain unaltered. 

A method of aborting a function is through the use of RXCS bit 14 (RX Initialize). Another method is 
through the use of the system Initialize signal that is generated by the PDP-1 1 RESET instruction, the 
console START key, or system power failure. 

4.2.4 Programming Examples 

4.2.4.1 Read Data/Write Data - Figure 4-22 presents a program for implementing a write, write 
deleted data, or a read function, depending on the function code that is used. The first instructions set 
up the error retry counters, PTRY, CTRY, and STRY. The instruction RETRY moves the command 
word for a write, write deleted data, or read into the RXCS. 

The set of three instructions beginning at the label IS moves the sector address to the RXl 1/RXVl 1 
after transfer request (TR), which is bit 7, has been set. The three instructions beginning at the label 2S 
move the track address to the RXl 1/RXVl 1 after TR has been set. The group of instructions begin- 
ning at the label 3$ looks for the done flag to set and checks for errors. 

An error condition, indicated by bit 15 setting, is checked beginning at ERFLAG. If bit is set, a CRC 
error has occurred, and a branch is made to CRCER. If a parity error has occurred, a branch is made 
to PARER. If neither of the above occurs, a seek error is assumed to have occurred and a branch is 
made to SEEKER, where the system is initialized. In the case of a write function, the sector buffer is 

refilled by a JMP to FILLBUF. In the case of a read function, a JMP is made to EMPBUFF. 

In each of the PAR, CRC, and SEEK routines, the command sequence is retried 10 times by decre- 
menting the respective retry counter. If an error persists after 10 tries, it is a hard error. The retry 
counters can be set up to retry as many times as desired. 

NOTE 
A fill buffer frniction is performed before a write 
function, and an empty buffer fpiiction is performed 
after a read fimction* 

4.2.4.2 Empty Buffer Function - Figure 4-23 shows a program for implementing an empty buffer 
function. The first instruction sets the number of error retries to 10, The address of the memory buffer 
is placed in register RO, and the Empty Buffer command is placed in the RXCS. Existence of a parity 
error is checked starting at instruction 3S. If a parity error is detected, the Empty Buffer command is 
loaded again. If an error persists for 10 retries, the error is considered hard. 

If no error is indicated, the program looks for the transfer request (TR) flag to set. The error flag is 
retested if TR is not set. Once TR sets, a byte is moved from the RXl 1/RXVl 1 sector buffer to the 
core locations of BUFFER. The process continues until the sector buffer is empty and the Done bit is 
set. 

4,2 A3 Fill Byffer Fiinctioii - Figure 4-24 presents a program to implement a fill buffer function. It is 
very similar to the empty buffer example. 

4.2.5 Restrictioiis and Prograinmiiig Pitfalls 

A set of restrictions and programming pitfalls for the RXl 1/RXVl 1 is presented below. 

1. Depending on how much data handling is done by the program between sectors, the min- 
imum interleave of two sectors may be used, but to be safe a three-sector interleave is recom- 
mended. 



4-30 



2 










3 










4 










5 










6 




177170 






7 




177172 






8 




177172 






9 




177171 






li 




177172 






11 










12 










13 










14 










15 










16 


0ii00i 


012767 


177770 


000320 


i? 


00i§06 


212767 


177770 


010314 


18 


000114 


012767 


177770 


000310 


19 










20 










21 










22 










23 










24 










25 










26 










27 










28 


000i22 


016767 


J00306 


177140 


29 










30 










31 










32 


000030 


1097$? 


177134 




33 


000034 


00177S 






34 


000036 


116767 


OJ0274 


177126 


35 










36 










37 










38 


000044 


1@S767 


177120 




39 


000053 


S8l77f 






40 


000052 


U6767 


.'30262 


177112 



.A§S 

IPROGRAHMINC EXAMPLES TOR THE SXli/RXil rtExIILE DISKETTE 

I 

J THE foLlOWlNC IS THE SXll ST&ND&flO DEVISE ABOrESS AND VECTqS ADO^CSS 

I 



RXCS8l77l7g 
RX0B8i77l7a 
RXSA9l77i72 
RXTA8i77|72 
RXES817717I 
J 



COHHANO ST&TUS RCSISTER 
DATA SUrrES REGISTER 
SECfOB ADDRESS REClSTEl 
TRACK ADDRISS RCSISTCR 
CRflO^ ITATUS RC61STER 



JTHE fOLLOS^INS IS A PROORANMINC IXAM?|.| flf THE PHQToCOt REOUlRED 

jTO WRITE. WRITE DELETED OATa, OS REaO AT lEgTOR "I" «THE CONTENTS Of PR06PlA« 

{LOCATION SECTOR) OF TRACK "T" {THE CONTENTS Or PR06RAN LOCATION TRACK) 



HqV i-lS. PTRY 
HOV S-li, CTRr 
MOV i-li, STRY 



; PARITY RETilY CnUNTER 

; CSC Hfnit eouNTiR 

I SEEK RETRY COUNT|f| 



JHRITE, WRITE DELETED DATA, qR ^CAO 

J 

1 eiTS 4 THRU I 0^ PRgSHAM LoCATIqN CqNHAND gQNTAlN TH| fUNCTloN 

J 

3 BIT 4 e 1 HEANS UNIT 1 ( s i HIAMf UNIT f) 

I 

i BITS 3 THRU 1 li THE Command I 4 s yilTE, 14 s MRITE deleted data, S 8 READ} 

J 

RETRY! MQV CQHHAND, «XCS ; UNIT * (MRlTEi NRITl DELETED OATA, Qfi 8EA0) 
i 

;HAiT For the tr&nsfeh request flag then transfer the sector adoreis 

i 

ii: Tsra RXCS ; 

iEO IS 

HOVS SECTOR, RXSA ; LOAD SrcTOS aDORCSS 
i 

JMAIT FQn THE TRANSFER REQUEST FlAC THEN TRANSFER THE TRACK AQBRCSS 
i 

2S: 



TEST FftR TME TRANSFER iSQUlST FLAG 

SES UNTIL THE TRANSFER REQUEfT FLAG SETS 



TSTB RXCS 

aea 21 

MOVB TRACK, RXTa 



TEST FftR THE TRANIFER REQUEST FLAG 

S£8 UNTIL fHE TR&NSFCR REQUEST FLaS SETS 

LOAD ^SaCK AOOREIS 



51 
52 
54 
55 
56 
57 
58 
§9 



68 

69 



72 
73 



75 
76 



82 
83 

85 
86 
8? 
88 
89 

91 

92 

93 

94 

95 

96 

97 

98 

99 

100 

101 

102 

103 

104 

105 

106 

107 

108 

109 



000060 
000066 
000070 

030174 
000076 



000106 
030110 
000116 



032767 .'00040 177102 

001774 

005767 177074 

001001 

2^0000 



032767 0^0003 177064 

001414 

2'52767 030002 177034 

001404 



THE SECTOR AND TRACK AOOrCSSES *^AVE gEEN TRiNSf^ERREO Tq THE R^ll 
HSAIT FgR THE QqHZ FLAS ANO CWECK f Qn ANY EiRo^S 

IF THE Function has cqnpleteo succesi^uily (Nq errqr flaG) then halt 

3S1 



ilT ^OqNESIT, RXCS 
BEO 3S 
TST RXCS 

9NE ERFLAa 
HALT 

iTME ERROR FLAG IS SET 



THE CONTENTS or THE MKES IS THE EiRoR STaTuI 



TEST Fqr tmI DoNI FLAG 
lEQ UNTIL THE DONE FLAG SETS 
TEST FOR TWE ERROR Flag 
SNC IF AN IRROR MAS SCSUtEO 
OK 9 COMPLSTEO 



IF THE RXES 8|TS 1 AND s THEN SO^^E TYPE qF SECk EiRoR OCCURED 
IF THE RXES 8IT i « 1 THEN A CRC CRRO^ NAS OCCUREO 
IF THE RXES in 1 « 1 ^HEN A UARITy ERROR HAS OCCUREO 



ERFLAGi 9IT ^3, RXES 
BE9 SEEK 
BIT #2, RXES 

BE9 CRC 



TEST FOR CiC AND PARITY ERSQ^S 

NOT A tARlTY OR CRC CHUSTJ gC A SEEK 

TEST FOR PARITY IRRQR 

NOT A Parity error chust] s£ a crc 



A PARITY ERROR MAS OCCUREO 

increment and TCI? THE PARITY ERRQR RET^Y CgUNTER PROSRAH LOCATIgN - pTRY 

ANO RETRY THE " QO^»&m " UNTfL THE PARITY IRRqR RECOVERS 

qR UNTIL THE pTRY COUNTER OVERFLOWS T© I 



000121 
000124 

000126 



009267 j:!@202 
001336 



INC PTRY 
8NE RETRY 

HALT 



^EfRY THE COMHAN0 
HA80 PARITY ERROR 



;A CRC ERROR WAS QCCUHEO 

J INCREMENT AND TEST THE CRC ERRQR ^ETRY COUNTER pRoCRAM LOCATION 

; 

JANO RETRY THE CoM^ANO UNTIL Tw| CRC ERROR RECOVERS 

J 

I OR UNTIL THE CTRY CqUNTER QVESFloMS TO i 



000130 
000134 
0001 36 



005267 
201332 

000000 



CRCl 



INC CTRY 
BNE RETRY 
HALT 



RETRY The 50MMAND 
Mia5 CRC ERROR 



THE ERROR FLAG IS SET 

THE ERROR IS CNqT] A PARITY ERRsR AND IS CNqT] A CRC ERRO^ 
THEREFORE IT MUST BE A SEEK EiRoR 
(STATE 0^ RXC5 ilTS i ANO 1 ARE f> 
000140 012767 040000 177022 SEEK: Mqv #INIT, RXCS ; INITIALIiE 

INCREMENT AND TEST THE SEEK ERRqR RETRY COUNTER PROGRAM LoCATIqN * STRY " 
AND RETRY THE CoMMANQ UNTIL THE SEEK ERRoR ^ECoVERS 
qR until the CTRY COUNTER OVERFLOWS Tq @ 



000146 
000152 
000154 



003267 000160 
001323 



INC STRY 
BNE RETRY 

HALT 



; RETRY THE gOHMANO 
; HARD SEEK ERROR 



Figure 4-22 RXl 1/RXVl I Write/ Write Deleted Data/Read Example 



4-31 



160 








161 








162 








163 








164 


00i242 


312767 


177770 


165 


009250 


312700 


0^)0342 


166 


000254 


316767 


000054 


167 








160 








169 








170 








171 








172 








173 








174 








175 








176 


000262 


109767 


176702 


177 


000266 


001014 




178 


000270 


332767 


0.10040 


179 


000276 


001771 




180 








181 








182 








163 








164 








185 


00030i 


009767 


176664 


186 


000304 


001001 




187 


000306 


000000 




188 








189 








190 








191 








192 








193 








194 








195 


000310 


J05267 


^30012 


196 


300314 


301353 




197 


J30316 


300000 




198 








199 








200 








2^1 








202 








203 


000320 


116730 


176646 


204 


000324 


000736 




206 








207 








208 


200326 


200000 




209 


000330 


kJ30000 




210 


300332 


;}2»0000 




211 








2l2 








213 








214 








2l5 








216 


000334 


000000 




2l7 








218 








2l9 








220 


000336 


000000 




221 








222 








223 








224 


000340 


000000 




225 








226 








227 








228 




030040 




229 




340000 




230 




300342 




231 




300542 




232 




300001 





176706 



176672 



;THE rOULOWINC IS A PROGRAMMING t^kHPH OF P^OTOcOl. PIC9UIRE0 TO 

jEMpry THE SECTOR auFTER 0^ i28 S-9IT iYTES 
I 



000056 EENTRY! MqV «'XS, PTRY 
ESETUPl MOV UBUFFER* H0 

MOV COMMAND, RXCS 



8 TRYS TO EMPTY THE SECTqR BUFFER 
PROHCRAMS QATA iUFFES 
ISSUE THE eOMMANO 



I 



WAIT FqR a TRANSFER REQUEST F|.AG SEFqUE TRANSFERRING DATA TO THE PROGRAMS 

DATA BUFFER rPoN THE RX0i SECTQR SUFFER 

jwAiT fqr a Done flag tq indicate the completion qf the emfty iu^fer co^^and 
jpRloR tq testin q the error ^IkO 



i 

ElOOP' TSTB RXCS 
HMl tMPTY 

BIT fOONEBiT, RS{CS 
BES ELOOP 

J 



TEST FgR THANSFER REQUEST FLAG 

INE IF TRANSFER REQUfST FLAG IS SET 

TEST FQR D9NE FLAG 

8E8 UNTIL THE DONE Ff^AG SET| 



THE DONE FLAG IS SET 

TEST FqR any errors <0NLY ERRoR POSSIBLE IS A PARITY fRRoR) 

TST RXCS 

@NE II 

HALT ; NO ERRORS « OK « COMPLETE 

ilNCFEMENT AND TEST THE PARITY E^RoR RCT^Y PigGRAM LoCATIqN " pTRY 

jAND RETRY THE CoMMaNO UNTIL THE ERRoR RECOVERS 

I 

;0R UNTIL THE PTRY CUNTER OVERFLOWS Tq 



IS: 



INC PTRY 

BNE ESETUP 
HALT 



RETRY TO EMPTY THE SfCTQ^ BUFFER 
MARD PARITY ERROR 



;THE TRANSFER REQUEST FLAG IS SET 

{ 

{TRANSFER DATA Tq THE PHQGRAM OaTA SU^^ER FipM THE RKil SECTq^ BUFFER 

EMPTYl HqVB RXDBi f(H0)* 
BR ELOOP 

JTHE FOLLOWING 3 PROGRAM LOCATIONS AR| THE EtRQR RETRY COUNTERS 



PARITY ERROR RETRY COUNTER 
CRC ER^OR iETRY COUNTER 
SEEK E^ROR RETRY COUNTER 



J 

CQMMANOl 

} 

jPRqCRAM LOCATION 



PTRY: 

ctry; 

STRy; 
I 
PROGRAM LOCATION " CQMHAND " CONTAINS THE CQMMANO TO BE ISSUED VIA THE LCD IqT 

WRITE H), WRITE DELETED DATA Cl4), Qn nt^Q (6), QR EMPTY BUFFER (25 

; 4, 14, 6, SR 2 * CGO BIT 1 8 15 

SECTOR " CONTAINS TH£ SESTqR ADDRESS (I Tq 32 OCTAL) 

SECTOR! ; 1 TO 3t OCTAL 

J 

sPRqGRAH location •* THACK » CONTAINS THE TRACK ADDRESS CI Tq 114 OCTAL) 

TRACKI J I TO %i^ OSTAL 

PROGRAM EQUIVALENTS 

DONEB|Ts40 
INIT»40000 
BUFFERS, 

,iBuFFER*200 

• END 



Figure 4-23 RX 1 1 /RX V 1 1 Empty Buffer Example 



4-32 



Ill 

112 
113 
114 
115 
116 
117 
118 
119 
120 
121 
122 
123 
124 
125 
126 
127 
128 
129 
130 
131 
132 
133 
134 
135 
136 
137 
138 
139 
140 
141 
142 
143 
144 
145 
146 
147 
148 
149 
150 
151 
152 
153 
154 
155 
156 
157 
158 



0iil56 012767 
000164 012700 
000170 016767 



000176 109767 

000202 001414 

000204 032767 

000212 001771 



000214 309767 
000220 001001 
000222 000000 



000224 005267 
000230 001355 
000232 000000 



300234 113067 
000240 000716 



THE rOLUOWlNC IS A PHOQRaHMINC CXAMfl^E or THE PROTOCOL REQUIRED TO 

FILL THE SECTOR BUFTER WITH 128 8-BlT BVTES 

NOTE! THE DATA Tq r m THE SCCTQR IU^FCR CAN BE ASSEMBLED IN CORE IN THE 
EVEN ADDRESSES BYTES Qf 128 WORDS OR IN BOTH BYTES Of 64 WORDS 



177773 000142 FENTRY; MQV #»10, PTRY 



000342 

030140 176772 



176766 

000040 176756 



176750 



SETUP! MOV «sBUFrER, R0 

MOV COMHAND, HXCS 



S TRYS TO riLL THE SECTOR SUFFER 
PROGRAMS DATA BUFFER 
ISSUE THE COMMAND 



WAIT FOR A TRANSFER REQUEST F^AS iEFQRE TRANSFERRING DATA FSQM THE PROGRAMS 
DATA BUFFER TQ THE RX01 SECTOR SUFFER 

WAIT FOR A DONE FlaT Tq INDICATE THE CO'^PLETIoN 0^ THE FJLL BUFFER COMMAND 
PRIOR Tq TESTING THE ERROR FLAG 



LQOPJ TSTB RMCS 
nf^'l FILL 

SIT iOONEilT, RXCS 
iEQ LOOP 



TEST Fqr TSANSrER REQUEST fLAG 
IEQ IF TRANSFER REQUfST FLAG SET 
TEST FOR THE DONE FLAG 
IEQ UNTIL THE DONE FLAG SETS 



jTNE DONE FLAG IS SET 

}?EST FgR ANY ERRQRS ^oNLY ERRqR PQSSI^LC IS A PARITY ERRqR) 

TST RXCS 
8NE II 

HALT ; NO ERRORS « ok « COHPlETE 

I 
INCREMENT AND TEST THE PARITY ERROR RETHY P^qCRAM LOCATION ' 

AND RETRY THE CoHMANP UNT JL THE ERRqR RECOVERS 

OR UNTIL THE PTRY COUNTER OVERFLOWS fO I 



PTRY 



11: 



INC PTRY 
INE SETUP 

HALT 



RETRY TO FILL THE SECTOR BUFFER 
HARD PARITY ERROR 



176732 



THE TRANSFER REQUEST FLAG IS SET 

TRANSFER DATA FRQH THE PRQCRAMS OATa BUFFER Tq THf RXil SECTQR BUFFER 

fill: MqVB f<R0)*, HXOB , PRqGRAHS data BUFFER IS 64 WORDS IN LENGTH 
BR LOOP 



Figure 4-24 RXl 1/RXVl 1 Fill Buffer Example 



2. If an error occurs and the program executes a read error code function (1 1 1), a parity error 
may occur for that command. The error status would not be for the error in which the read 
error code function was originally required. 

3. The DRV SEL RDY bit is only updated at the time of a read status function (101) for both 
drives, and after an Initialize, depending on the status of drive 0. At the termination of any 
other functions it reflects the drive status of the last Read Status or Initialize command. 

4. It is not required to load the Drive Select bit into the RXCS when the command is Fill 
Buffer (000) or Empty Buffer (010). 

5. Sector Addressing: 1-26 (No sector 0) 
Track Addressing: 0-76 

6. A power failure causing the recalibration of the drives will result in a Done condition, the 
same as finishing reading a sector. However, during a power failure, RXES bit 2 (Initialize 
Done) will set. Checking this bit will indicate a power fail condition. 

7. Excessive use of the read status function (101) will result in drastically decreased through- 
put, because a read status function requires between one and two diskette revolutions or 
about 250 ms to complete. 



4-33 



4.2e6 Error Recovery 

There are two error indications given by the RXll/RXVIl system. The read status function (Para- 
graph 4.2.3,5) will assemble the current contents of the RXES (Paragraph 4.2.2.6), which can be 
sampled to determine errors. The read error code function (Paragraph 4.2.3.7) can also be used to 
retrieve explicit error information. The RXl 1/RXVl 1 interface register can be interrogated to deter- 
mine the type of failure that occurred. A list of error codes follows. 

NOTE 
A read status function Is not necessary If the DRV 
RDY bit is not going to be interrogated becayse the 
MX2ES is in the interface register at the compietion 
of every ftmction. 

Octal 

Code Error Code Meaning 

(X)10 Drive failed to see home on Initialize 

0020 Drive 1 failed to see home on Initialize 

0040 Tried to access a track greater than 77 

0050 Home was found before desired track was reached 

0070 Desired sector could not be found after looking at 52 headers (2 revolutions) 

01 10 More than 40 /xs and no SEP clock seen 

0120 A preamble could not be found 

0130 Preamble found but no ID mark found within allowable time span 

0140 CRC error on what appeared to be a header. Error is not asserted 

0150 The header track address of a good header does not compare with the desired track 

0160 Too many tries for an I DAM (identifies header) 

0200 CRC error on reading the sector from the disk 

0220 R/W electronics failed maintenance mode test 

0240 Density Error 

43 RX2I1 AND RXV21 PROGRAMMING INFORMATION 

This section describes device registers, register and vector address assignments, programming specifi- 
cations, and programming examples for the RX211 and RXV21 interfaces. 

All software control of the RX211/RXV21 is performed by means of two device registers: the com- 
mand and status register (RX2CS) and a multipurpose data buffer register (RX2DB) which have been 
assigned bus addresses and can be read or loaded. 

The RX02 contains all the control circuitry required to read from and write on the disk and to calcu- 
late and verify the CRC. It has a buffer large enough to hold one full sector of diskette data (128 or 256 
8-bit bytes). Information is serially passed between the interface and the RX02. 

A typical diskette write sequence, which is initiated by a user program, would occur in two steps: 

Fill Buffer - A command to fill the buffer is moved into the RX2CS. The Go bit must be set. The 
program tests for TR. When TR is detected, the program moves the desired word count into the 
RX2DB. TR goes false while the word count is moved to the RX02. The program retests TR and 
moves the bus address into the RX2DB. The device now requests bus mastership and DMA's one data 
word at a time into the RX2DB and shifts it across the RX02 data bus serially one 8-bit byte at a time 
into the sector buffer. When the word count register overflows (if necessary, the RX02 control zero- 
fills the remainder of the sector buffer) the Done bit is set, and an interrupt will occur if the program 
has enabled interrupts. 

4-34 



Write Sector - A command to write the contents of the sector buffer onto the disk is moved into the 
RX2CS. The program tests TR and when TR is set, moves the desired sector address to the RX2DB. 
TR remains false while the sector address is shifted to the RX02 control. The control retests TR and 
when it is again set, moves the desired track address register to the RX2DB. Again TR is negated. The 
RX02 locates the desired track and sector and compares the diskette density against the assigned 
function density and writes the contents of the sector buffer onto the disk if the densities agree. When 
the write operation is completed, the Done bit is set and an interrupt will occur if the program has 
enabled interrupts. 

A typical disk read operation occurs in the reverse order. First, the desired track and sector are located 
and the contents of the sector are read into the sector buffer (read sector). Then the contents of the 
sector buffer is unloaded into memory (empty buffer). In either case, the contents of the sector buffer 
are not valid if either a Power Fail or Initialize follows a fill buffer or read sector function. 

43.1 Register and Vector Addresses 

The RX21 1/RXV21 use two registers for communicating with the host computer: the command and 
status register (RX2CS) normally assigned bus address 177170 and the data buffer register (RX2DB) 
normally assigned bus address 177172. The vector address is 264. 

43.2 Register Description 

43.2.1 RX2CS ~" Command and Status (177170) - Loading this register while the RX02 is not busy 
and with bit 0=1 will initiate a function as described below and indicated in Figure 4-25. 





15 


14 


13 12 


11 


10 


09 


08 


07 


06 


05 


04 


03 02 01 


00 






RX 

INIT 


EXT 
ADDR 








DEN 


TR 








FUNCTION 


GO 


E 


1 

RRO 


R 




1 

RX02 










1 

INTR 
ENB 






1 

UN! 
SEL 


r 





DONE MA-WQ6 

Figure 4-25 RX2CS Format RX2I 1/RXV21 

Bit No. Descrlptioii 

Go - Initiates a command to RX02. This is a write-only bit. 

1-3 Function Select - These bits code one of the eight possible functions described in Paragraph 

4,3.3 and listed below. These are write-only bits. 



Code 



Function 



000 


Fill Buffer 


001 


Empty Buffer 


010 


Write Sector 


oil 


Read Sector 


100 


Set Media Density 


101 


Read Status 


110 


Write Deleted Data Sector 


111 


Read Error Code 



Unit select - This bit selects one of the two possible disks for execution of the desired 
function. This bit is readable only when Done is set, at which time it indicates the unit 
previously selected. This is a read/write bit. 



4-35 



5 Done - This bit indicates the completion of a function. Done will generate an interrupt when 
asserted if Interrupt Enable (RX2CS bit 6) is set. This is a read-only bit. 

6 Interrupt Enable - This bit is set by the program to enable an interrupt when the RX02 has 
completed an operation (Done). The condition of this bit is normally determined at the time 
a function is initiated. This bit is cleared by Initialize and is a read/write bit. 

7 Transfer Request - This bit signifies that the RX21 1/RXV21 needs data or has data avail- 
able. This is a read-only bit. 

8 Density - This bit determines the density of the function to be executed. This bit is readable 
only when Done is set, at which time it indicates the density of the function previously 
executed. This is a read/write bit. 

9-10 Reserved for future use. Must be written as a zero. 

1 1 RX02 ■" This bit is set by the interface to inform the programmer that this is an RX02 

system. This is a read-only bit. 

12-13 Extended address - These bits are used to declare an extended bus address. These are write- 
only bits. 

14 RX211/RXV21 Initialize - This bit is set by the program to initialize the RX211/RXV21 

without initializing all devices on the Unibus. This is a write-only bit. 



CAUTION 

Loading the lower byte of the RX2CS will also load 
the ypper byte of the RX2CS, 

Upon setting this bit in the RX2CS, the RX21I/RXV21 will negate Done and move the 
head position mechanism of both drives (if two are available) to track 0. Upon completion 
of a successful Initialize, the RX02 will zero the error and status register, and set Initialize 
Done. It will also read sector 1 of track 1 on drive into the buffer. 

15 Error - This bit is set by the RX02 to indicate that an error has occurred during an attempt 

to execute a command. This read-only bit is cleared by the initiation of a new command or 
an Initialize. 



43.2.2 RX2DB - Data Byffer Register (177172) - This register serves as a general purpose data path 
between the RX02 and the interface. It may represent one of six RX02 registers according to the 
protocol of the function in progress (Paragraph 4.3.3). 



This register is read/write if the RX02 is not in the process of executing a command; that is, it may be 
manipulated without affecting the RX02 subsystem. If the RX02 is actively executing a command, this 
register will only accept data if RX2CS bit 7 (TR) is set. In addition, valid data can only be read when 
TR is set. 



CAUTION 
Violation of protocol in manipylation of this register 
may cause permanent data loss. 



4-36 



43.23 RX2TA - RX Track Address (Figure 4-26) - This register is loaded to indicate on which of the 
1 14g (0-76io) tracks a given function is to operate. It can be addressed only under the protocol of the 
function in progress (Paragraph 433). Bits 8-15 are unused and are ignored by the control. 



15 


14 


13 


12 


11 


10 


09 


08 


07 


06 


05 


04 


03 


02 


01 


00 




































114,H 



Figure 4-26 RX2TA Format (RX21 1/RXV2!) 

43.2,4 RX2SA - RX Sector Address (Figure 4-27) - This register is loaded to indicate on which of the 
32g (l-26io) sectors a given function is to operate. It can be addressed only under the protocol of the 
function in progress (Paragraph 4.3.3). 



15 


14 


13 


12 


11 


10 


09 


08 


07 


06 


05 


04 


03 


02 


01 


00 






































NOT USED 



1 32, 



Figure 4-27 RX2SA Format (RX21 1/RXV21) 

43.2.5 RX2WC - RX Word Count Register (Figure 4-28) - For a double density sector the maximum 
word count is 128io. For a single density sector the maximum word count is 64|o. If a word count is 
beyond the limit for the density indicated, the control asserts Word Count Overflow (bit 10 of 
RX2ES). This is a write-only register. The actual word count and not the 2's complement of the word 
count is loaded into the register. 

lb 14 13 12 n 10 09 08 07 00 05 04 03 02 01 00 



'ZI^^~'=^^=^^II1 
















128,.. 



Figure 4-28 RX2WC Formal (RX21 1/RXV21) 

4.3.2,6 RX2BA - RX Bys Address Register (Figure 4-29) - This register specifies the bus address of 
data transferred during fill buffer, empty buffer, and read definitive error operations. Incrementation 
takes place after a memory transaction has occurred. The RX2BA, therefore, is loaded with the ad 
dress of the first data word to be transferred. This is a 16-bit, write-only register (Paragraph 4.3.3). 



15 


14 


13 


12 


11 


10 


09 


08 


07 


06 


05 


04 


03 


02 


01 


00 



























,„ 









Figure4-29 RX2BA and RX2DB Formal (RX2I I/RXV21) 

4.3.2.7 RX2DB - RX Data Byffer (Figure 4-29) - All information transferred to and from the floppy 
media passes through this register and is addressable only under the protocol of the function in prog- 
ress (Paragraph 4.3.3). 



4-37 



432M RX2ES - RX Error and Status (Figure 4-30) - This register contains the current error and 
status conditions of the drive selected by bit 4 (Unit Select) of the RX2CS. This read-only register can 
be addressed only under the protocol of the function in progress (Paragraph 4 J. 3). The RX2ES is 
located in the RX2DB upon completion of a function. 



15 


14 


13 


12 


11 


10 


09 


08 


07 


06 


05 


04 


03 


02 


01 


00 


V 


V— 
\0T USEC 




NXf^^ 




L»_ 


r— J 


L— 




DRV 


h 




DRV 






RX 




■"""^ 










1 




RDY 




DEN 


AC LO 1 


1 






wc 


UNIT DD 


DEN !D 


CRC 












OVFL 




SEL 










ERR 




i 

RESERVED 



RESERVED 

Figure 4-30 RX2ES Format (RX21 i/RXV2r) 



RXES bit assignments are: 

Bit Nii« Description 

CRC Error ~ A cyclic redundancy check error was detected as information was retrieved 

from a data field of the diskette. The data collected must be considered invalid. The RX2ES 
is moved to the RX2DB, and Error and Done are asserted. It is suggested that the data 

transfer be retried up to 10 times, as most errors are recoverable (soft). 

2 Initialize Done - This bit is asserted in the RX2ES to indicate completion of the Initialize 
routine which can be caused by RX02 power failure, system power failure, or programmable 
or bus Initialize. 

3 RX AC LO - This bit is set by the interface to indicate a power failure in the RX02 sub- 
system. 

4 Density Error - This bit indicates that the density of the function in progress does not match 
the drive density. Upon detection of this error the control terminates the operation and 
asserts Error and Done, 

5 Drive Density - This bit indicates the density of the diskette in the drive selected (indicated 
by bit 8). The density of the drive is determined during read and write sector operations. 

6 Deleted Data ■-• This bit indicates that in the course of recovering data, the '^deleted data'' 
address mark was detected at the beginning of the data field. The Drv Den bit indicates 
whether the mark was a single or double density deleted data address mark. The data follow- 
ing the mark will be collected and transferred normally, as the deleted data mark has no 
further significance other than to establish drive density. Any alteration of files or actual 
deletion of data due to this mark must be accomplished by user software. 

7 Drive Ready - This bit indicates that the selected drive is ready if bit 7= 1 and all conditions 
for disk operation are satisfied, such as door closed, power okay, diskette up to speed, etc. 
The RX02 may be presumed to be ready to perform any operation. This bit is only valid 
when retrieved via a read status function or initialize. 

8 Unit Select - This bit indicates that drive is selected if bit 8=0. This bit indicates the drive 
that is currently selected. 

10 Word Count Overflow - This bit indicates that the word count is beyond sector size. The fill 
or empty buffer operation is terminated and Error and Done are set. 

1 1 Nonexistent Memory Error - This bit is set by the interface when a DMA transfer is being 
performed and the memory address specified in RX2BA is nonexistent. 



4-38 



4.3.3 Function Codes 

Following the strict protocol of the individual function, data storage and recovery on the 
RX21 1/RXV21 occur with careful manipulation of the RX2CS and RX2DB registers. The penalty for 
violation of protocol can be permanent data loss. 

A summary of the function codes is presented below: 



000 


Fill Buffer 


001 


Empty Buffer 


010 


Write Sector 


oil 


Read Sector 


100 


Set Media Density 


101 


Read Status 


110 


Write Deleted Data Sector 


111 


Read Error Code 



The following paragraphs describe in detail the programming protocol associated with each function 
encoded and written into RX2CS bits 1-3 if Done is set. 

4J.3 J Fill Buffer (OOO) - This function is used to fill the RX02 data buffer with the number of words 
of data specified by the RX2WC register. Fill buffer is a complete function in itself: the function ends 
when RX2WC overflows, and if necessary, the control has zero-filled the remainder of the buffer. The 
contents of the buffer may be written on the disk by means of a subsequent Write Sector command or 
returned to the host processor by an Empty Buffer command. If the word count is too large, the 
function is terminated, Error and Done are asserted, and the Word Count overfiow bit is set in 
RX2ES. 

To initiate this function the RX2CS is loaded with the function. Bit 4 of the RX2CS (Unit Select) does 
not affect this function since no disk operation is involved. Bit 8 (Density) must be properly selected 
since this determines the word count limit. When the comm.and has been loaded, the Done bit (RX2CS 
bit 5) goes false. When the TR bit is asserted the RX2WC may be loaded into the data buffer register. 
When TR is again asserted, the RX2BA may be loaded into the RX2DB. The data words are trans- 
ferred directly from memory and when RX2WC overflows and the control has zero-filled the remain- 
der of the sector buffer, if necessary, Done is asserted ending the operation. If bit 6 RX2CS (Interrupt 
Enable) is set, an interrupt is initiated. Any read of the RX2DB during the data transfer is ignored by 
the interface. After Done is true the RX2ES is located in the RX2DB register. 

4.3.3.2 Empty Buffer (001) - This function is used to empty the contents of the internal buffer 
through the RX21 1/RXV21 for use by the host processor. This data is in the buffer as the result of a 
previous Fill Buffer or Read Sector command. 

The programming protocol for this function is identical to that for the Fill Buffer command. The 
RX2CS is loaded with the command to initiate the function. (This function will ignore bit 4 RX2CS, 
Unit Select). RX2CS bit 8 (Density) must be selected to allow the proper word count limit. When the 
command has been loaded, the Done bit (RX2CS bit 5) goes false. When the TR bit is asserted, the 
RX2WC may be loaded into the RX2DB. When TR is again asserted the RX2BA may be loaded into 
the RX2DB. The RX211/RXV21 assembles one word of data at a time and transfers it directly to 
memory. Transfers occur until word count overflow, at which time the operation is complete and 
Done goes true. If bit 6 RX2CS (Interrupt Enable) is set, an interrupt is initiated. After Done is true, 
the RX2ES is located in the data buffer register. 

4.3.3.3 Write Sector (010) - This function is used to locate a desired sector on the diskette and fill it 
with the contents of the internal buffer. The initiation of the function clears RX2ES, TR, and Done. 



4-39 



When TR is asserted, the program must load the desired sector address into RX2DB, which will drop 
TR. When TR is again asserted, the program must load the desired track address into the RX2DB, 
which will drop TR. TR will remain unasserted while the RX02 attempts to locate the desired sector. 
The diskette density is determined at this time and is compared to the function density. If the densities 
do not agree, the operation is terminated; bit 4 RX2ES is set, RX2ES is moved to the RX2DB, Error 
(bit 15 RX2CS) is set, Done is asserted, and an interrupt is initiated, if bit 6 RX2CS (Interrupt Enable) 
is set. 

If the densities agree but the RX02 is unable to locate the desired sector within two diskette revolu- 
tions, the interface will abort the operation, move the contents of RX2ES to the RX2DB, set Error (bit 
15 RX2CS), assert Done, and initiate an interrupt if bit 6 RX2CS (Interrupt Enable) is set. 

If the desired sector has been reached and the densities agree, the RX21 1/RXV21 will write the 128io 
or 64io words stored in the internal buffer followed by a CRC character which is automatically calcu- 
lated by the RX02. The RX211/RXV21 ends the function by asserting Done and if bit 6 RX2CS 
(Interrupt Enable) is set, initiating an interrupt. 

CAUTION 
The conterits of the sector buffer are not valid data 
after a power loss has been detected by the RX02. 
However, write sector will be accepted as a valid in- 
struction and the (random) contents of the buffer will 
be written, followed by a valid CRC. 

NOTE 

The contents of the sector buffer are not destroyed 
during a write sector operation. 

4.3.3.4 Read Sector (Oil) - This function is used to locate the desired sector and transfer the contents 
of the data field to the internal buffer in the control. This function may also be used to retrieve rapidly 
(5 ms) the current status of the drive selected. The initiation of this function clears RX2ES, TR, and 
Done. 

When TR is asserted the program must load the desired sector address into the RX2DB, which will 
drop TR. When TR is again asserted, the program must load the desired track address into the 
RX2DB, which will drop TR. 

TR and Done will remain negated while the RX02 attempts to locate the desired sector. If the RX02 is 
unable to locate the desired sector within two diskette revolutions for any reason, the RXV21/RX21 1 
will abort the operation, set Done and Error (bit 15 RX2CS), move the contents of the RX2ES to the 
RX2DB, and if bit 6 RX2CS (Interrupt Enable) is set, initiate an interrupt. 

If the desired sector is successfully located, the control reads the data address mark and determines the 
density of the diskette. If the diskette (drive) density does not agree with the function density the 
operation is terminated and Done and Error (bit 1 5 RX2CS) are asserted. Bit 4 RX2ES is set (Density 
Error) and the RX2ES is moved to the RX2DB. If bit 6 RX2CS (Interrupt Enable) is set, an interrupt 
is initiated. 

If a legal data mark is successfully located, and the control and densities agree, the control will read 
data from the sector into the internal buffer. If a deleted data address mark was detected, the control 
will set bit 6 RX2ES (DD). As data enters the internal buffer, a CRC is computed based on the data 
field and the CRC bytes previously recorded. A non-zero residue indicates that a read error has oc- 
curred and the control sets bit RX2ES (CRC error) and bit 15 RX2CS (Error). The RX21 1/RXV21 
ends the operation by asserting Done and moving the contents of the RX2ES into the RX2DB. If bit 6 
RX2CS is set, an interrupt is initiated. 



4-40 



If the desired sector is successfully located, the densities agree, and the data is transferred with no CRC 
error, Done will be set and if bit 6 RX2CS (Interrupt Enable) is set the RX211/RXV21 initiates an 
interrupt. 



4.33,5 Set Media Density (100) - This function causes the entire diskette to be reassigned to a new 
density. Bit 8 RX2CS (Density) indicates the new density. The control reformats the diskette by writ- 
ing new data address marks (double or single density) and zeroing all of the data fields on the diskette. 



The function is initiated by loading the RX2CS with the command. Initiation of the function clears 
RX2ES and Done. When TR is set, an ASCII "f (1 1 1) must be loaded into the RX2DB to complete 
the protocol. This extra character is a safeguard against an error in loading the command. When the 
control recognizes this character it begins executing the command. 



The control starts at sector 1 , track and reads the header information, then starts a write operation. If 
the header information is damaged, the control will abort the operation. 

If the operation is successfully completed, Done is set and if bit 6 RX2CS (Interrupt Enable) is set an 
interrupt is initiated. 



CAUTION 
This operation takes about 15 seconds and should not 
be interrupted. If for any reason the operation is in- 
terrupted^ ae illegal diskette has been generated 
which may have data marks of both densities. This 
diskette should again be completely reformatted. 



4.33.6 Maintenance Read Status (101) - This function is initiated by loading the RX2CS with the 
command. Done is cleared. The Drive Ready bit (bit 7 RX2ES) is updated by counting index pulses in 
the control. The Drive Density is updated by loading the head of the selected drive and reading the first 
data mark. The RX2ES is moved into the RX2DB. The RX2CS may be sampled w^hen Done (bit 5 
RX2CS) is again asserted and if bit RX2CS (Interrupt Enable) is set, an interrupt will occur. This 
operation requires approximately 250 ms to complete. 



4.3.3.7 Write Sector with Deleted Data (110) - This operation is identical to function 010 (write 
sector) with the exception that a deleted data address mark is written preceding the data rather than 
the standard data address mark. The Density bit associated with the function indicates whether a 
single or double density deleted data address mark will be written. 



4.3.3.8 Read Error Code (111) - The read error code function implies a read extended status. In 
addition to the specific error code a dump of the control's internal scratch pad registers also occurs. 
This is the only way that the word count register can be retrieved. This function is used to retrieve 
specific information as well as drive status information depending upon detection of the general Error 
bit. 



4-41 



The transfer of the registers is a DMA transfer. The function is initiated by loading the RX2CS with 
the command and then Done goes false. When TR is true, the RX2BA may be loaded into the RX2DB 
and TR goes false. The registers are assembled one word at a time and transferred directly to memory. 



Register Protocol 



Word 1<7:0> Definitive Error Codes 

Word 1<15:8> Word Count Register 

Word 2<7:0> Current Track Address of Drive 

Word 2< 15:8> Current Track Address of Drive 1 

Word 3<7:0> Target Track of Current Disk Access 

Word 3<15:8> Target Sector of Current Disk Access 

Word4<7> Unit Select Bit 

Word4<5> Head Load Bit 

Word 4<6> <4> Drive Density Bit of Both Drives 

Word 4<0> Density of Read Error Register Command 

Word 4< 15:8 > Track Address of Selected Drive 



For DMA interfaces the controller status soft register is sent to the interface at the end of the command. The 
four status bits are included in an 8-bit word. Unit Select = bit 7, Density of Drive 1 = bit 6, Head Load = bit 
5, Density of Drive = bit 4, Density of Read Error Register Command = bit 0. 



tThe Track Address of the Selected Drive - Error is only meaningful on a code 150 error. The register contains 
the address of the cylinder that the head reached on a seek error. 



When the RX02 senses the return of power, it will remove Done and begin a sequence to: 



1. Move each drive head position mechanism to track 

2. Clear any active error bits 

3. Read sector 1 of track 1, on drive 

4. Assert Initialize Done in the RXES. 



Upon completion of the power up sequence, Done is again asserted. There is no guarantee that infor- 
mation being written at the time of a power failure will be retrievable; however, all other information 
on the diskette will remain unaltered. 



4.33.9 RX02 Power Fail - When the RX02 control senses a loss of power within the RX02, it will 
unload the head and abort all controller action. The RXAC L line is asserted to indicate to the 
RX211/RXV21 that subsystem power is gone. The RX211/RXV21 asserts Done and Error and sets 
the RXAC L bit in the RX2ES. 



4-42 



4.3.4 Error Recovery 

There are two error indications given by the RX211/RXV2i system. The maintenance read status 
function (Paragraph 4.3.3.6) will assemble the current contents of the RX2ES which can be sampled to 
determine errors. The read error code function (Paragraph 4.3.3.8) can also be retrieved for explicit 
error information. The RX21 1/RXV21 interface register can be interrogated to determine the type of 
failure that occurred. The error codes and their meaning are listed below. 

Octal 

Code Error Code Meaning 

0010 Drive failed to see home on Initialize. 

0020 Drive 1 failed to see home on Initialize. 

(K)40 Tried to access a track greater than 76 

(X)50 Home was found before desired track was reached. 

0070 Desired sector could not be found after looking at 52 headers (2 revolutions). 

01 10 More than 40 jjls and no SEP clock seen 

0120 A preamble could not be found. 

0130 Preamble found but no ID mark found within allowable time span 

0150 The header track address of a good header does not compare with the desired track. 

0160 Too many tries for an IDAM (identifies header) 

0170 Data AM not found in allotted time 

0200 CRC error on reading the sector from the disk. No code appears in the ERREG. 

0220 R/W electronics failed maintenance mode test. 

0230 Word count overflow 

0240 Density Error 

0250 Wrong key word for set media density command 

4.3.5 RXlll/RXVllProgramming Examples 

4.3.5.1 Write/Fill Buffer 

Figure 4-31 illustrates a program to write data on a disk by performing write and fill buffer sub- 
routines. Initially, the write subroutine tests to see if there is an error from the last operation. If there is 
an error, a branch is made and the write subroutine is not performed; otherwise a jump is made to the 
fill buffer subroutine. (Before data can be written the RX02 sector buffer must be filled.) The Fill 
Buffer command is set, the density (single or double) is set, and the command is loaded in the 
RX02/RXCS. After a TR is received, the word count (for either 128 or 256 bytes of data) is loaded in 
the RX02/RXDB. After another TR is received, the starting address where data will be retrieved from 
memory is loaded in the RX02/RXDB. The RX02 controller fills the sector buffer with the number of 
bytes indicated then the RX02 controller sets the Done bit. (If an Error is detected, the Error bit is set 
in the RXCS and the program halts.) The program returns to the write subroutine, the drive is selected, 
the write command and interrupt enable are set, the density is set, and the command is loaded in the 
RX02/RXCS. There is a wait for TR, then the sector address is loaded in the RX02/RXDB; there is 
another wait for TR and the track address is loaded in the RX02/RXDB, The data loaded in the sector 
buffer is written by the RX02 controller on the selected drive (disk) at the selected track and sector. 
While the controller writes the data, the program waits for an interrupt (which signifies the completion 
of write data) to occur in order to return to the main program. 



4-43 



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4-44 



4.3.5.2 Read/ Empty Buffer 

Figure 4-32 illustrates a program to read data from the disk by performing read and empty buffer 
subroutines. The drive to be read is selected, the read command and interrupt enable are set, the 
density is set, and the command is loaded in the RX02/RXCS. There is a wait for TR and then the 
sector address is loaded in the RX02/RXDB; there is another wait for TR, and the track address is 
loaded in the RX02/RXDB, While the RX02 controller reads data from the selected location on the 
selected disk into the RX02 sector buffer, the program waits for an interrupt to occur and then there is 
a jump to the empty buffer subroutine. The empty buffer command is set, the density is set, and the 
command is loaded into the RX02/RXCS. After a TR is received, the word count is loaded into the 
RX02/RXDB; there is another wait for TR and the address in memory where the data is to be stored is 
loaded into the RX02/RXDB. The data is emptied from the sector buffer by the RX02 controller, and 
when the buffer is emptied, there is a return to the main program. 



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Figure 4-32 RX21 1/RXV21 Read/Empty Buffer Example 



4-45 



RX02 FLOPPY DISK SYSTEM Reader's Comments 

USER'S GUIDE 
EK-RX02-UG-001 

Your comiiieiits and suggestions will help us in our continuous effort to improve the quality and usefulness of our 
publications. 



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