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Personal Computer 
Hardware Reference 
Library 



Technical 
Reference 

Options and Adapters 



Volume 2 



Revised Edition (AprU 1984) 

The following paragraph does not apply to the United Kingdom or any country where such 
provisions are inconsistent with local law: International Business Machines Corporation 
provides this manual "as is," without warranty of any kind, either expressed or implied, 
including, but not limited to the particular purpose. IBM may make improvements and/or 
changes in the product(s) and/or the program(s) described in this manual at any time. 

This product could include technical inaccuracies or typographical errors. Changes are 
made periodically to the information herein; these changes will be incorporated in new 
editions of the publication. 

It is possible that this material may contain reference to, or information about, IBM 
products (machines or programs), programming, or services that are not announced in 
your country. Such references or information must not be construed to mean that IBM 
intends to announce such IBM products, programming, or services in your country. 

Products are not stocked at the address below. Requests for copies of this product and for 
technical information about the system should be made to your authorized IBM Personal 
Computer dealer. 

The following paragraph applies only to the United States and Puerto Rico: A Reader's 
Comment Form is provided at the back of this publication. If the form has been removed, 
address comments to: IBM Corp., Personal Computer, P.O. Box 1328-C, Boca Raton, 
Florida 33432. IBM may use or distribute any of the information you supply in any way it 
believes appropriate without incurring any obUgations whatever. 

© Copyright International Business Machines Corporation 1981, 1982, 1983, 1984 



Federal Communications Commission 
Radio Frequency Interference Statement 



Warning: The equipment described herein has been certified 
to comply with the limits for a Class B computing device, 
pursuant to Subpart J of Part 15 of the FCC rules. Only 
peripherals (computer input/output devices, terminals, 
printers, etc.) certified to comply with the Class B limits may 
be attached to the computer. Operation with non-certified 
peripherals is likely to result in interference to radio and TV 
reception. If peripherals not offered by IBM are used with the 
equipment, it is suggested to use shielded grounded cables 
with in-line filters if necessary. 

CAUTION 

The product described herein is equipped with a grounded 
plug for the user's safety. It is to be used in conjunction with 
a properly grounded receptacle to avoid electrical shock. 



m 



IV 



Personal Computer 
Hardware Reference 
Library 



IBM Monochrome 
Display and Printer 
Adapter 



6361511 



Contents 



Introduction 1 

Monochrome Display Adapter Function 1 

Description 1 

Programming Considerations 5 

Specifications 9 

Printer Adapter Function 11 

Description 11 

Programming Considerations 13 

Specifications 17 

Logic Diagrams 19 



ui 



IV 



Introduction 



The IBM Monochrome Display and Printer Adapter has two 
functions. The first is to provide an interface to the IBM 
Monochrome Display. The second is to provide a parallel 
interface for the IBM Printers. We will discuss this adapter by 
function. 



Monochrome Display Adapter Function 



Description 

The IBM Monochrome Display and Printer Adapter is designed 
around the Motorola 6845 CRT Controller module. There are 
4K bytes of RAM on the adapter that are used for the display 
buffer. This buffer has two ports to which the system unit's 
microprocessor has direct access. No parity is provided on the 
display buffer. 

Two bytes are fetched from the display buffer in 553 ns, 
providing a data rate of 1.8M bytes/second. 

The adapter supports 256 different character codes. An 8K-byte 
character generator contains the fonts for the character codes. 
The characters, values, and screen characteristics are given in "Of 
Characters, Keystrokes, and Colors" in your Technical Reference 
system manual. 

This adapter, when used with a display containing P39 phosphor, 
does not support a Ught pen. 

Where possible, only one low-power Schottky (LS) load is 
present on any I/O slot. Some of the address bus lines have two 
LS loads. No signal has more than two LS loads. 



Monochrome Adapter 1 



Characteristics of the adapter are: 

Supports 80-character by 25 -line screen 

Has direct-drive output 

Supports 9-PEL by 14-PEL character box 

Supports 7-PEL by 9-PEL character 

Has 18 -kHz monitor 

Has character attributes 



2 Monochrome Adapter 



The following is a block diagram of the monochrome display 
adapter portion of the IBM Monochrome Display and Printer 
Adapter. 



Processor 
Address 


(12) 










Memory 
Address 
Multiplexer 






(1 


1) 




(10) 
1 f 




(10) 








2K Memory 

Character 

Code 




2K Memory 
Attribute 




Data 

Bus 

Gating 


(8) 






t 


Processor 
Data 




(8) 








B[ 






^ 


Character 






DO-7 






* 


Clock 


^ 






(8) 


Octal 
Latch 




Octal 
Latch 








MA 
























^ 








y 


f 




\ 






MC6845 
CRTC 




f 






Character 
Generator 




Attribute 
Decode 


AO 

Chip 
Select 




RA 


(4) 






^ 


f 


DOTCLK 


^ 




" ' w 


f 






Shift 
Register 




^ 


Video 

Process 

Logic 


Signals 


^ 




w 








Serial 


Dots 






HSYNC, VSYNC, 


w 
CURSOR, DISPEN^ 






w 










Clock 










\ 



Monitor 
Direct Drive 
Outputs 



IBM Monochrome Display Adapter Block Diagram 



Monochrome Adapter 3 



4 Monochrome Adapter 



Programming Considerations 

The following table summarizes the 6845 controller module's 
internal data registers, their functions, and their parameters. For 
the IBM Monochrome Display, the values must be programmed 
into the 6845 to ensure proper initialization of the display. 









IBM Monochrome 


Register 


Register 


Program 


Display 


Number 


File 


Unit 


(Address in hex) 


RO 


Horizontal Total 


Characters 


61 


R1 


Horizontal Displayed 


Characters 


50 


R2 


Horizontal Sync Position 


Characters 


52 


R3 


Horizontal Sync Width 


Characters 


F 


R4 


Vertical Total 


Character Rows 


19 


R5 


Vertical Total Adjust 


Scan Line 


6 


R6 


Vertical Displayed 


Character Row 


19 


R7 


Vertical Sync Position 


Character Row 


19 


R8 


Interlace Mode 





02 


R9 


Maximum Scan Line 
Address 


Scan Line 


D 


R10 


Cursor Start 


Scan Line 


B 


R11 


Cursor End 


Scan Line 


C 


R12 
R13 


Start Address (H) 
Start Address (L) 




00 
00 






R14 


Cursor (H) 




00 




R15 


Cursor (L) 




00 




R16 
R17 


Reserved 
Reserved 








-- 





To ensure proper initialization, the first command issued to the 
IBM Monochrome Display and Printer Adapter must be sent to 
the CRT control port 1 (hex 3B8), and must be a hex 01, to set 
the high-resolution mode. If this bit is not set, the system unit's 
microprocessor's access to the adapter must never occur. If the 
high-resolution bit is not set, the system unit's microprocessor will 
stop running. 

System configurations that have both an IBM Monochrome 
Display and Printer Adapter, and an IBM Color/Graphics 
Monitor Adapter, must ensure that both adapters are properly 
initialized after a power-on reset. Damage to either display may 
occur if not properly initialized. 



Monochrome Adapter 5 



The IBM Monochrome Display and Printer Adapter supports 256 
different character codes. In the character set are alphanumerics 
and block graphics. Each character in the display buffer has a 
corresponding character attribute. The character code must be an 
even address, and the attribute code must be an odd address in 
the display buffer. 



7 


6 


5 


4 


3 


2 




1 

























7 6 5 4 3 2 10 




BL 


R 


G 


B 


1 


R 


G 


B 















































Character Code 
Even Address (M) 



Attribute Code 
Odd Address (M + l) 



Foreground 
Intensity 
Background 
Blink 



The adapter decodes the character attribute byte as defined 
above. The blink and intensity bits may be combined with the 
foreground and background bits to further enhance the character 
attribute functions listed below: 



Background 


Foreground 




RGB 


RGB 


Function 








Non-Display 





1 


Underline 





1 1 1 


White Character/Black Background 


1 1 1 





Reverse Video 



The 4K display buffer supports one screen of the 25 rows of 80 
characters, plus a character attribute for each display character. 
The starting address of the buffer is hex BOOOO. The display 
buffer can be read using direct memory access (DMA); however, 
at least one wait state will be inserted by the system unit's 
microprocessor. The duration of the wait state will vary, because 
the microprocessor/monitor access is synchronized with the 
character clock on this adapter. 



6 Monochrome Adapter 



Interrupt level 7 is used on the parallel interface. Interrupts can 
be enabled or disabled through the printer control port. The 
interrupt is a high-level active signal. 

The following table breaks down the functions of the I/O address 
decode for the adapter. The I/O address decode is from hex 3B0 
through hex 3BF. The bit assignment for each I/O address 
follows: 



I/O Register 




Address 


Function 


3B0 


Not Used 


3B1 


Not Used 


3B2 


Not Used 


383 


Not Used 


3B4 


6845 Index Register 


3B5 


6845 Data Register 


3B6 


Not Used 


3B7 


Not Used 


3B8 


CRT Control Port 1 


3B9 


Reserved 


3BA 


CRT Status Port 


3BB 


Reserved 


3BC 


Parallel Data Port 


3BD 


Printer Status Port 


3BE 


Printer Control Port 


3BF 


Not Used 



I/O Address and Bit Map 



Monochrome Adapter 7 



Bit 




Number 


Function 





+ High Resolution Mode 


1 


Not Used 


2 


Not Used 


3 


+ Video Enable 


4 


Not Used 


5 


+ Enable Blink 


6,7 


Not Used 



6845 CRT Control Port 1 (Hex 3B8) 



Bit 
Number 


Function 



1 
2 
3 


+ Horizontal Drive 

Reserved 

Reserved 

+ Black/White Video 



6845 CRT Status Port (Hex 3BA) 



8 Monochrome Adapter 



Specifications 



Monochrome 

Display 

connector 




At Standard TTL Levels 







Ground 




1 








Ground 




2 










Not Used 


3 




IBM 






Not Used 


4 


IBM 


Monochrome 






Not Used 


5 


Monochrome 
Display and 


Display 




+ intensity 




6 


Printer Adapter 






+ Video 




7 








+ Horizontal 




8 








- Vertical 




9 






^ 











Note: Signal voltages are 0.0 to 0.6 Vdc at down level and + 2.4 to 3.5 
Vdcathigh level. 

Connector Specifications 



Monochrome Adapter 9 



10 Monochrome Adapter 



Printer Adapter Function 



Description 

The printer adapter portion of the IBM Monochrome Display and 
Printer Adapter is specifically designed to attach printers with a 
parallel-port interface, but it can be used as a general 
input/output port for any device or application that matches its 
input/output capabilities. It has 12 TTL-buffer output points, 
which are latched and can be written and read under program 
control using the microprocessor In or Out instruction. The 
adapter also has five steady-state input points that may be read 
using the microprocessor's In instructions. 

In addition, one input can also be used to create a microprocessor 
interrupt. This interrupt can be enabled and disabled under 
program control. A reset from the power-on circuit is also ORed 
with a program output point, allowing a device to receive a 
'power-on reset' when the system unit's microprocessor is reset. 

The input/output signals are made available at the back of the 
adapter through a right-angle, printed-circuit-board-mounted, 
25 -pin, D-shell connector. This connector protrudes through the 
rear panel of the system unit or expansion unit, where a cable may 
be attached. 

When this adapter is used to attach a printer, data or printer 
commands are loaded into an 8-bit, latched, output port, and the 
strobe line is activated, writing data to the printer. The program 
then may read the input ports for printer status indicating when 
the next character can be written, or it may use the interrupt Hne 
to indicate "not busy" to the software. 

The output ports may also be read at the card's interface for 
diagnostic loop functions. This allows faults to be isolated to the 
adapter or the attaching device. 



Monochrome Adapter 1 1 



The following is a block diagram of the printer adapter portion of 
the Monochrome Display and Printer Adapter. 



Bus Buffer 



Data Latch 



Trans- 
ceiver 

DIR 



\4^ 



AEN. 



Command 
Decoder 



Reset 



DIR 



Read 
Data 



> Enable 



8 



#— ► 



Write Data 



Write Control 



Read Status 



Read 
Control 



Bus 
Buffers 



^ Enable 



Enable 



Clock 



25-Pin D-Shell 
Connector 



O.C. 
Drivers 



Control 
Latch 



^ Clock 



> Cl€ 



Printer Adapter Block Diagram 



SLCT IN 

STROBE 

AUTO 

FDXT 

INlf 



ERROR 

SLCT 

PE 

ACK 
BUSY 



12 Monochrome Adapter 



Programming Considerations 

The printer adapter portion of the IBM Monochrome Display and 
Printer Adapter responds to five I/O instructions: two output 
and three input. The output instructions transfer data into 2 
latches whose outputs are presented on pins of a 25 -pin D-shell 
connector. 

Two of the three input instructions allow the system unit's 
microprocessor to read back the contents of the two latches. The 
third allows the system unit's microprocessor to read the real-time 
status from a group of pins on the connector. 

A description of each instruction follows. 



IBM Monochrome Display & 
Printer Adapter 


Output to address hex 3BC 


Bit 7 
Pin 9 


Bite 
Pin 8 


Bit 5 
Pin 7 


Bit 4 
Pin 6 



The instruction captures data from the data bus and is present on 
the respective pins. Each of these pins is capable of sourcing 2.6 
mA and sinking 24 mA. 

It is essential that the external device does not try to pull these 
lines to ground. 



IBM Monochrome Display & 
Printer Adpater 



Output to address hex 3BE 



Bit 4 

IRQ 
Enable 



This instruction causes the latch to capture the five least 
significant bits of the data bus. The four least significant bits 
present their outputs, or inverted versions of their outputs, to the 



Monochrome Adapter 13 



respective pins as shown in the previous figure. If bit 4 is written 
as a 1, the card will interrupt the system unit's microprocessor on 
the condition that pin 10 changes from high to low. 

These pins are driven by open-collector drivers pulled to +5 Vdc 
through 4.7 kfl resistors. They can each sink approximately 7 mA 
and maintain 0.8 volts down-level. 



IBM Monochrome Display & 
Printer Adapter 



Input from address hex SBC 



This instruction presents the system unit's microprocessor with 
data present on the pins associated with the output to hex 3BC. 
This should normally reflect the exact value that was last written 
to hex SBC. If an external device should be driving data on these 
pins at the time of an input (in violation of usage ground rules), 
this data will be ORed with the latch contents. 



IBM Monochrome Display & 
Printer Adapter 



Input fronn address hex 3BD 



This instruction presents the real-time status to the system unit's 
microprocessor from the pins as follows. 



Bit? 


Bite 


Bits 


Bit 4 


Bits 


Bit 2 


Bit 1 


BitO 


Pin 1 1 


Pin 10 


Pin 12 


Pin 13 


Pin 15 


- 


- 


- 



IBM Monochrome Display & 
Printer Adapter 



Input from address hex 3BE 



14 Monochrome Adapter 



This instruction causes the data present on pins 1, 14, 16, 17, and 
the IRQ bit to be read by the system unit's microprocessor. In 
the absence of external drive appUed to these pins, data read by 
the system unit's microprocessor will match data last written to 
hex 3BE in the same bit positions. Notice that data bits 0-2 are 
not included. If external drivers are dotted to these pins, that 
data will be ORed with data applied to the pins by the hex 3 BE 
latch. 



Bit 7 


Bite 


Bit 5 


Bit 4 

IRQ 
Enable 

Por = 


Bit 3 


Bit 2 
Pin 16 

Por = 


Bit 1 


BitO 
Pin 1 

Por=1 


Pin 17 
Por=:1 


Pin 14 
Por=1 



These pins assume the states shown after a reset from the system 
unit's microprocessor. 



Monochrome Adapter 15 



16 Monochrome Adapter 



Specifications 




At Standard TTL Levels 
Signal 
Name 



Printer 



- Strobe 



+ Data Bit 



+ Data Bit 1 



+ Data Bit 2 



+ Data Bit 3 



+ Data Bit 4 



+ Data Bit 5 



+ Data Bit 6 



+ Data Bit 7 



- Acknowledge 



+ Busy 



+ P. End (out of paper) 



+ Select 



- Auto Feed 



- Error 



- Initialize Printer 



- Select Input 



Ground 



Connector Specifications 



Adapter 
Pin Number 



10 



11 



12 



13 



14 



15 



16 



17 



18-25 



IBM 

Monochrome 
Display and 
Printer 
Adapter 



Monochrome Adapter 17 



18 Monochrome Adapter 



ISHT6I 



(SHT 3) +1/0 READY - 
(SHT9) +IR0 7- 



DECOUPLING CAPACITORS 



IC1 5C1 



:•••:= 0.047 AfF 



o 

I 
t 



r U60 



"H 



ISHT 2.4.81 


r 


ISHT 2.4.8) 


o 


(SHT 2.4.81 
(SHT 2.4.8) 


(TQ 




*^t 




n 


[SHT 2.4) 
(SHT 2.4) 


o 


(SHT 2.4) 


^M% 


(SHT 2.4) 
(SHT 2.4) 


&5 


(SHT 2.4) 


GTQ 


(SHT 2) 
[SHT 2) 
(SHT 4) 


&5 


[SHT 4) 
(SHT 4) 
(SHT 4) 
(SHT 4) 


5 


[SHT 4.6) 





»-L 



-HflEMW 


[SHT 3.4) 


-MEIVIR 


(SHT 4.6) 


-low 


[SHT 2.4.8) 


-lOR 


(SHT 4.6,8) 


PRESET 


[SHT 2.3.5) 


-RESET 


(SHT 3.5.7.8 


I/O CLOCK 


(SHT 4) 



Monochrome Display Adapter (Sheet 1 of 10) 



o 



s 

o 

f 

B 

I 



, 74LS157 



ISHT 1) 
(SHT 1) 
ISHT 1) 
ISHT t) 

ISHT II 
ISHT II 
ISHT 1) 
ISHT II 
ISHT 31 

ISHT 1| 
ISHT II 
ISHT 1) 
ISHT 1) 



ISHT 61 

ISHT 1) 
ISHT 41 
ISHT 1 1 

ISHT 6) 

ISHT 31 



ISHT 31 



ISHT1) +RESET 




6.10] 

I 

6.101 



Monochrome Display Adapter (Sheet 2 of 10) 



ISHTll+RESET 



I 
I 

I 
I 



O 

^ 



K> 




ISHT 7) 
(SHT 4.5) 



ISHT 51 
(SHT 10) 



ISHT 2.6) 



(SHT 2) 
ISHT 5.10) 
(SHT 2) 



ISHT 6) 
(SHT 1) 



(SHT 7.10) 
ISHT 10) 



-CLR VIDEO (SHT 5.7.10) 

-CURSOR OLY (SHT 5) 

-DISPEN OLY (SHT 7) 

+DISPEN OLY (SHT 7) 

+CURSORDLY (SHT 5) 

+HSYNC DLY |SHT 4.7) 

+VSYNC DLY (SHT 5,7) 



Monochrome Display Adapter (Sheet 3 of 10) 






O 

o 

3 

n 

> 

t 



ISHT 1) 
(SHT 1) 
(SHT 1) 

(SHT U 
(SttT 1) 

ISHT n 
IS«T 1J 
ISHT 1) 

ISHT I] 
ISHT 1 1 
ISHT ]] 



ISHT 1) 
ISHT n 
ISHT 1) 
ISHT 1) 



ISHT 1) 
ISHT 3) 




ISHT 81 
ISHT Z| 
ISHT 3) 
ISHT 7) 



■ROGATEAT |SHT 6| 



■CPUMSEL ISHT 3) 
•OATAGATE |SHT 6) 



ISHT 6) 
ISHT 6} 
ISHT 6r 
(SHT 61 



Monochrome Display Adapter (Sheet 4 of 10) 



2 

O 
S 

o 

I 
i 

> 






bJ 

Ui 



ISHT 1) PRESET 

(SHT 31 +VSYNC DLY 



ISHT 7) -ENABLE BLINK 



ISHT 3) +CURSOR DLY 

ISHT 7| +ENABLE BLINK 
ISHT 3) -CURSOR DLY 



ISHT 21 AT7 

ISHT 7) +VIDEO ENABLE 
ISHT 3] +CCLK 



ISHT 1) 
ISHT 3) 
ISHT 4) 

ISHT 31 



(SHT 31 
ISHT 2) 

I 

ISHT 2) 




B&W VIDEO ISHT 71 



Monochrome Display Adapter (Sheet 5 of 10) 






o 
s 
o 

I 



(SHI) +AEN- 

(SH 1) -lOR- 

(SH 1) -MEMR- 

ISH31 DATAGATE- 

|SH 2) CCO- 



(SH4) -RDGATECC- 
ISH3) -WE- 



74LS32 _ 

Jmoo>" 



n^zg 



X '<] 



rDIR 
U23 



(SH 2,4.7,8,9) 
(SH 2.4.8.9) 
(SH 2.4.7.9) 
(SH 2.4,8.9) 
(SH 2.8.9) 
(SH 2.7.8.9) 
|SH 2,8,9) 
(SH 2.8.9) 



Monochrome Display Adapter (Sheet 6 of 10) 



(SHT8I 


BOO 


ISHTB) 


802 


ISHT8) 


803 


(SHT81 


805 


ISHT4) 


-SEL1 


(SHT 11 


-RESET 



I (81 

(SHT 5) I IF) 

(SHT 5) +ALPHADOTS 

(SHT 3) -OISPENOLY 





(SHT 3) 


+HSYNC OLY 




(SHT 3) 


+VSYNC DLY 


2 


(SHT 3) 


-JUMPER 


1 


(SHT 51 
(SHT 3) 

(SHT tOl 
(SHT 10) 


+8/W VIDEO 
DOTCLK 

LCC7 
LCC6 






> 


(SHT 3) 


-CLR VIDEO 


(SHT 10) 


LCC5 


1 


(SHT 10) 
ISHT31 


CGEN BITO 
+DISPEN DLY 










(SHT 5) 
(SHT 5] 



Monochrome Display Adapter (Sheet 7 of 10) 



© 

a 
o 
o 

o 

s 

> 






ISHEET 6) BOO 
(SHEET 6) BOl 
(SHEET 61 BD2 
(SHEET 6) 603 
(SHEET 6) B04 
(SHEET 61 B05 
(SHEET 61 BD6 
(SHEET 6) B07 




(SHEET 1) BA3 
(SHEET 1) BA2 



(SHEET 4) +GRP0CD 



Monochrome Display Adapter (Sheet 8 of 10) 



yPATAO 



s 

o 

I 
i 

I 



(SHEET 81 / 



(SHEET 8) 
(SHEET 8) 



25-PIN < 
D-SHELL 1 
CONNECTOR 



(SHEET 8) 
(SHEET 8( 



(SHEET 8) 
(SHEET 8) 



(SHEET 81 
(SHEET 8) 



-PIN 15 - 
-PIN 13 - 
-PIN 12 - 

-PIN 10 ^ 

-PIN 11 - 

■STROBE 



^74LS04 



8 74LS02 



ITjt 



74LS125 
74LS125 



S (SHEET 6) 



/ 



Monochrome Display Adapter (Sheet 9 of 10) 



-a 



00 

o 
s 
o 

f 

i 



§- 






(SHT 21 
(SHT 2) 
ISKT 2) 



(SHT 21 
(SHT 3) 

(SHT 31 
ISHT 31 
(SHT 31 



(SHT 51 
(SHT 31 
(SHT 31 DOTCLK 




C GEN BITO (SHT 7| 



LCC7 (SHT 71 

LCC6 (SHT 71 
LCC5 (SHT 71 



Monochrome Display Adapter (Sheet 10 of 10) 



Personal Computer 
Hardware Reference 
Library 



IBM Color/Graphics 
Monitor Adapter 



6361509 



Contents 



Description 1 

Controller 5 

Mode Set Register 5 

Display Buffer 5 

Character Generator 5 

Timing Generator 6 

Composite Color Generator 6 

Alphanumeric Mode 6 

Graphics Modes 9 

Basic Operations 12 

Programming Considerations 15 

Programming the Mode Control and Status Register 15 

Programming the 6845 CRT Controller 15 

Color-Select Register 18 

Mode-Control Register 19 

Mode- Control Register Summary 20 

Status Register 20 

Sequence of Events for Changing Modes 21 

Memory Requirements 22 

Specifications 23 

Logic Diagrams 27 

Index Index-1 



IV 



Description 



The IBM Color/Graphics Monitor Adapter is designed to attach 
to the IBM Color Display, to a variety of television-frequency 
monitors, or to home television sets (user-supplied RF modulator 
is required for home television sets). The adapter is capable of 
operating in black-and-white or color. It provides three video 
interfaces: a composite- video port, a direct-drive port, and a 
connection interface for driving a user-supplied RF modulator. A 
light pen interface is also provided. 

The adapter has two basic modes of operation: alphanumeric 
(A/N) and all-points-addressable (APA) graphics. Additional 
modes are available within the A/N or APA graphics modes. In 
the A/N mode, the display can be operated in either a 40-column 
by 25 -row mode for a low-resolution monitor or home television, 
or in an 80-column by 25-row mode for high-resolution monitors. 
In both modes, characters are defined in an 8-wide by 8-high 
character box and are 7 -wide by 7 -high, double dotted characters 
with one descender. Both uppercase and lowercase characters are 
supported in all modes. 

The character attributes of reverse video, blinking, and 
highlighting are available in the black-and-white mode. In the 
color mode, 16 foreground and 8 background colors are available 
for each character. In addition, blinking on a per-character basis 
is available. 

The monitor adapter contains 16K bytes of storage. As an 
example, a 40-column by 25-row display screen uses 1000 bytes 
to store character information and 1000 bytes to store 
attribute/color information. This means that up to eight screens 
can be stored in the adapter memory. Similarly, in an 80-wide by 
25-row mode, four display screens can be stored in the adapter 
memory. The entire 16K bytes of storage in the display adapter 
are directly accessible by the processor, which allows maximum 
program flexibility in managing the screen. 

In A/N color modes, it is also possible to select the color of the 
screen's border. One of 16 colors can be selected. 



Color/ Graphics Monitor Adapter 1 



In the APA graphics mode, there are two resolutions available: a 
medium-resolution color graphics mode (320 PELs by 200 rows) 
and a high-resolution black-and-white graphics mode (640 PELs 
by 200 rows). In the medium-resolution mode, each picture 
element (PEL) may have one of four colors. The background 
color (Color 0) may be any of the 16 possible colors. The 
remaining three colors come from one of the two 
program-selectable palettes. One palette contains 
green/red/brown; the other contains cyan/magenta/ white. 

The high-resolution mode is available only in black-and-white 
because the entire 16K bytes of storage in the adapter is used to 
define the on or off state of the PELs. 

The adapter operates in nohinterlace mode at either 7 or 14 MHz, 
depending on the mode of the operation selected. 

In the A/N mode, characters are formed from a ROS character 
generator. The character generator contains dot patterns for 256 
different characters. The character set contains the following 
major groupings of characters. 

• 16 special characters for game support 

• 15 characters for word-processing editing support 

• 96 characters for the standard ASCII graphics set 

• 48 characters for foreign-language support 

• 48 characters for business block-graphics support (for the 
drawing of charts, boxes, and tables using single and double 
lines) 

• 16 selected Greek characters 

• 15 selected scientific-notation characters 

The color/graphics monitor function is on a single adapter. The 
direct-drive and composite-video ports are right-angle mounted 
connectors on the adapter, and extend through the rear panel of 



2 Color/ Graphics Monitor Adapter 



the system unit. The direct-drive video port is a 9-pin, D-shell, 
female connector. The composite-video port is a standard female 
phono jack. 

The display adapter uses a Motorola 6845 CRT Controller device. 
This adapter is highly programmable with respect to raster and 
character parameters. Therefore, many additional modes are 
possible with programming of the adapter. 

On the following page is a block diagram of the Color/Graphics 
Monitor Adapter. 



Color/Graphics Monitor Adapter 3 



4;^ 

n 


Processor 

Address 

1^ 


Address 
Latch 










Display 
Buffer 
(16K Bytes) 






input 
Buffer 


^ 




Proc 


Bssor 


© 


Processor 
Data 


f 


y 


f 

) 


% — t '— 


Data 










k 

1 


f 






►^ 




i 


Output 
Latch 
















I 




I 






6845 

CRT 

Controller 


-> 


Address 
Latch 






Data 
Latch 


Data 
Latch 










^ 










§ 


< 


y> 














A 


k 


i 


^ 


Graphics 
Serializer 




►n 




^ 


• w 




-> 


























Character 
Generator 
ROM 


^ 


Alpha 
Serializer 


Color 
Encoder 


-►R 












w 


W 


1 ► 


->G 




Palette/ 
Overscan 
















-►B 






w 


-►1 




1 


^ Horizontal 










^ 




^ 


f 

^ 


i 


^ Vertical 










Composite 

Color 

Generator 






Model 
Control 




Timing 
Generator 
& Control 




w\ 


-► 




w 




W 

















Color/Graphics Monitor Adapter Block Diagram 



Controller 

The controller is a Motorola 6845 Cathode Ray Tube (CRT) 
Controller. It provides the necessary interface to drive the 
raster-scan CRT. 



Mode Set Register 

The mode set register is a general-purpose, programmable, I/O 
register. It has I/O ports that may be individually programmed. 
Its function in this adapter is to provide mode selection and color 
selection in the medium-resolution color-graphics mode. 



Display Buffer 

The display buffer resides in the processor-address space, starting 
at address hex B8000. It provides 16 bytes of dynamic 
read/ write memory. A dual-ported implementation allows the 
processor and the graphics control unit access to this buffer. The 
processor and the control unit have equal access to this buffer 
during all modes of operation, except in the high-resolution 
alphanumeric mode. In this mode, only the processor should have 
access to this buffer during the horizontal-retrace intervals. 
While the processor may write to the required buffer at any time, 
a small amount of display interference will result if this does not 
occur during the horizontal-retrace intervals. 



Character Generator 

A ROS character generator is used with 8K bytes of storage that 
cannot be read from or written to under program control. This is 
a general-purpose ROS character generator with three character 
fonts. Two character fonts are used on the Color/Graphics 
Monitor Adapter: a 7 -high by 7 -wide double-dot font and a 
7-high by 5-wide single-dot font. The font is selected by a 
jumper (P3). The single-dot font is selected by inserting the 
jumper; the double-dot font is selected by removing the jumper. 



Color/ Graphics Monitor Adapter 5 



Timing Generator 

This generator produces the timing signals used by the 6845 CRT 
Controller and by the dynamic memory. It also solves the 
processor/graphic controller contentions for access to the display 
buffer. 



Composite Color Generator 

This generator produces base-band-video color information. 



Alphanumeric Mode 

Every display character position in the alphanumeric mode is 
defined by two bytes in the regen buffer (a part of the monitor 
adapter), not the system memory. Both the Color/Graphics 
Monitor Adapter and the Monochrome Display and Printer 
Adapter use the following 2-byte character-attribute format. 



Display-Character Code Byte 



Attribute Byte 



6 



The following table shows the functions of the attribute byte. 



Attribute Function 


Attribute Byte 


Normal 

Reverse Video 
Nondisplay (Black) 
Nondisplay (White) 


7 


6 5 4 


3 


2 1 


B 


RGB 


1 


RGB 


FG 


Background 


Foreground 


B 
B 
B 
B 




1 1 1 



1 1 1 


1 
1 
1 
1 


1 1 1 




1 1 1 



I = Highlighted Foreground (Character) 
B = Blinking Foreground (Character) 



6 Color/Graphics Monitor Adapter 



The definitions of the attribute byte are in the following table. 



7 6 5 4 3 2 10 



B R G B I RGB 



-^ Foreground Color 

--► Intensity 

-^ Background Color 

~>- Blinking 



In the alphanumeric mode, the display can be operated in either a 
low-resolution mode or a high-resolution mode. 

The low-resolution alphanumeric mode has the following features: 

• Supports home color televisions or low-resolution monitors. 

• Displays up to 25 rows of 40 characters each. 

• Has a ROS character generator that contains dot patterns for 
a maximum of 256 different characters. 

• Requires 2,000 bytes of read/ write memory (on the adapter). 

• Has an 8 -high by 8 -wide character box. 

• Has two jumper-controlled character fonts available: a 7 -high 
by 5 -wide single-dot character font with one descender, and a 
7 -high by 7 -wide double-dotted character font with one 
descender. 

• Has one character attribute for each character. 

The high-resolution alphanumeric mode has the following 
features: 

• Supports the IBM Color Display or other color monitor with 
direct-drive capability. 

• Supports a black-and-white composite-video monitor. 

• Displays up to 25 rows of 80 characters each. 



Color/Graphics Monitor Adapter 7 



• Has a ROS display generator that contains dot patterns for a 
maximum of 256 characters. 

• Requires 4,000 bytes of read/ write memory (on the adapter). 

• Has an 8-high by 8-wide character box. 

• Has two jumper-controlled character fonts available: a 7-high 
by 5 -wide single-dot character font with one descender, and a 
7-high by 7-wide double-dot character font with one 
descender. 

• Has one character attribute for each character. 

The Color/Graphics Monitor Adapter will change foreground and 
background colors according to the color value selected in the 
attribute byte. The following figure shows the color values for 
the various red, green, blue, and intensity bit settings. 



R 


G 


B 


1 


Color 














Black 








1 





Blue 





1 








Green 





1 


1 





Cyan 


1 











Red 


1 





1 





Magenta 


1 


1 








Brown 


1 


1 


1 





White 













Gray 








1 




Light Blue 





1 







Light Green 





1 


1 




Light Cyan 


1 










Light Red 


1 





1 




Light Magenta 


1 


1 







Yellow 


1 


1 


1 




White (High Intensity) 



Note: Not all Monitors recognize the intensity (I) bit. 



8 Color/Graphics Monitor Adapter 



Graphics Modes 

The Color/Graphics Monitor Adapter has three graphics modes: 
low-resolution, medium-resolution, and high-resolution color 
graphics. However, only medium- and high-resolution graphics 
are supported in ROM. The following figure shows these modes. 



Mode 


Horizontal 


Vertical 


Number of Colors Available 




(PELS) 


(Rows) 


(Includes Background Color) 


Low Resolution 


160 


100 


16 (Includes black-and-white) 


Medium 


320 


200 


4 Colors Total 


Resolution 






1 of 1 6 for Background and 
1 of Green, Red, or Brown or 
1 of Cyan, Magenta, or White 


High Resolution 


640 


200 


Black-and-white only 



Low-Resolution Color/ Graphics Mode 

The low-resolution mode supports home televisions or color 
monitors. This mode, not supported in ROM, has the following 
features: 

• Contains a maximum of 160 PELs by 100 rows, with each 
PEL being 2-high by 2-wide. 

• Specifies 1 of 16 colors for each PEL by the I, R, G, and B 
bits. 

• Requires 16,000 bytes of read/write memory on the adapter. 

• Uses memory-mapped graphics. 



Medium-Resolution Color/ Graphics Mode 

The medium-resolution mode supports home televisions or color 
monitors. It has the following features: 

• Contains a maximum of 320 PELs by 200 rows, with each 
PEL being 1-high by 1-wide. 



Color/ Graphics Monitor Adapter 9 



• Preselects 1 of 4 colors for each PEL. 

• Requires 16,000 bytes of read/ write memory on the adapter. 

• Uses memory-mapped graphics. 

• Formats 4 PELs per byte in the following manner: 



7 6 


5 4 


3 2 


1 


CI CO 


C1 CO 


C1 CO 


CI CO 


First 

Display 

PEL 


Second 
Display 
PEL 


Third 

Display 

PEL 


Fourth 
Display 
PEL 



• Organizes graphics storage into two banks of 8,000 bytes, 
using the following format: 



Memory 
Address 
(in hex) 

B8000 



B9F3F 



BAOOO 



BBF3F 



BBFFF 



Function 



Even Scans 
(0,2,4,. ..198) 
8,000 bytes 



Not Used 



Odd Scans 
(1,3,5.. .199) 
8,000 Bytes 



Not Used 



Address hex B8000 contains the PEL instruction for the 
upper-left corner of the display area. 



10 Color/ Graphics Monitor Adapter 



Color selection is determined by the following logic: 



01 


CO 


Function 





1 
1 




1 



1 


Dot takes on the color of 1 of 1 6 preselected background colors 
Selects first color of preselected Color Set 1 or Color Set 2 
Selects second color of preselected Color Set 1 or Color Set 2 
Selects third color of preselected Color Set 1 or Color Set 2 



CI and CO select 4 of 16 preselected colors. This color 
selection (palette) is preloaded in an I/O port. 

The two color sets are: 



Color Set 1 


Color Set 2 


Color 1 is Green 
Color 2 is Red 
Color 3 is Brown 


Color 1 is Cyan 
Color 2 is Magenta 
Color 3 is White 



The background colors are the same basic 8 colors defined for 
low-resolution graphics, plus 8 alternate intensities defined by 
the intensity bit, for a total of 16 colors, including black and 
white. 



High-Resolution Black-and- White Graphics Mode 

The high-resolution mode supports color monitors. This mode 
has the following features: 

• Contains a maximum of 640 PELs by 200 rows, with each 
PEL being 1-high by 1-wide. 

• Supports black-and-white only. 

• Requires 16,000 bytes of read/ write memory on the adapter. 

• Addressing and mapping procedures are the same as 
medium-resolution color/graphics, but the data format is 
different. In this mode, each bit in memory is mapped to a 
PEL on the screen. 



Color/ Graphics Monitor Adapter 1 1 



Formats 8 PELs per byte in the following manner: 



First Display PEL 
Second Display PEL 
Third Display PEL 
Fourth Display PEL 
Fifth Display PEL 
Sixth Display PEL 
Seventh Display PEL 
Eighth Display PEL 



7 


6 


5 


4 


3 


2 


1 






Basic Operations 

In the alphanumeric mode, the adapter fetches character and 
attribute information from its display buffer. The starting address 
of the display buffer is programmable through the CRT 
controller, but it must be an even address. The character codes 
and attributes are then displayed according to their relative 
positions in the buffer. The following addresses will produce an 
"AB" in the upper-left corner of a 40 by 25 screen and an "X" in 
the lower-right corner. 



(Even) 

Starting 

Address 



Last 
Address 



Memory 
Address 
(in hex) 

B8000 
B8001 
B8002 
B8003 



B87CE 
B87CF 



Display Buffer 



Character Code A 


Attribute A 


Character Code B 


Attribute B 




Character Code X 


Attribute X 



(Example of a 40 by 25 Screen) 




Video Screen 



12 Color/ Graphics Monitor Adapter 



The processor and the display control unit have equal access to 
the display buffer during all of the operating modes, except the 
high-resolution alphanumeric mode. During this mode, the 
processor gains access to the display buffer during the vertical 
retrace time. If it does not, the display will be affected with 
random patterns as the microprocessor is using the display buffer. 
In the alphanumeric mode, the characters are displayed from a 
pre-stored ROM character generator that contains the dot 
patterns for all of the display able characters. 

In the graphics mode, the displayed dots and colors, up to 16K 
bytes, are fetched from the display buffer. 



Color/ Graphics Monitor Adapter 13 



14 Color/Graphics Monitor Adapter 



Programming Considerations 



Programming the Mode Control and Status 
Register 

The following I/O devices are defined on the Color/ Graphics 
Monitor Adapter. 



Hex 












Address 


A9 A8 A7 A6 A5 


A4 A3 A2 A1 


AG 


Function of Register 


3D8 







110 





Mode Control Register (DO) 


3D9 







110 


1 


Color Select Register (DO) 


3DA 







110 1 





Status Register (D1) 


3DB 







110 1 


1 


Clear Light Pen Latch 


3DC 







1110 





Preset Light Pen Latch 


3D4 




1 


1 z z 





6845 Index Register 


3D5 







1 z z 


1 


6845 Data Register 


Z = don't care condition 



Programming the 6845 CRT Controller 

The controller has 19 internal accessible registers, which are used 
to define and control a raster-scan CRT display. One of these 
registers, the index register, is used as a pointer to the the other 
18 registers. It is a write-only register, which is loaded from the 
processor by executing an 'out' instruction to I/O address hex 
3D4. The five least-significant bits of the I/O bus are loaded into 
the index register. 

In order to load any of the other 18 registers, the index register is 
first loaded with the necessary pointer, then the data register is 



Color/ Graphics Monitor Adapter 15 



loaded with the information to be placed in the selected register. 
The data register is loaded from the processor by executing an 
'out' instruction to I/O address hex 3D5. 

The table on the next page defines the values that must be loaded 
into the 6845 CRT Controller registers to control the different 
modes of operation supported by the attachment. 



16 Color/ Graphics Monitor Adapter 



Address 
Register 


Register 
Number 


Register 
Type 


Units 


I/O 


40 by 25 
Alpha- 
numeric 


80 by 25 
Alpha- 
numeric 


Graphic 
Modes 





RO 


Horizontal 
Total 


Character 


Write 
Only 


38 


71 


38 


1 


R1 


Horizontal 
Displayed 


Character 


Write 
Only 


28 


50 


28 


2 


R2 


Horizontal 
Sync Position 


Character 


Write 
Only 


2D 


5A 


2D 


3 


R3 


Horizontal 
Sync Width 


Character 


Write 
Only 


OA 


OA 


OA 


4 


R4 


Vertical Total 


Character 
Row 


Write 
Only 


IF 


1F 


7F 


5 


R5 


Vertical Total 
Adjust 


Scan 
Line 


Write 
Only 


06 


06 


06 


6 


R6 


Vertical 
Displayed 


Character 
Row 


Write 
Only 


19 


19 


64 


7 


R7 


Vertical 
Sync Position 


Character 
Row 


Write 
Only 


1C 


1C 


70 


8 


R8 


Interlace 
Mode 




Write 
Only 


02 


02 


02 


9 


R9 


Maximum 
Scan Line 
Address 


Scan 
Line 


Write 
Only 


07 


07 


01 


A 


R10 


Cursor Start 


Scan 
Line 


Write 
Only 


06 


06 


06 


B 


R11 


Cursor End 


Scan 
Line 


Write 
Only 


07 


07 


07 


C 


R12 


Start 
Address (H) 


- 


Write 
Only 


00 


00 


00 


D 


R13 


Start 
Address (L) 




Write 
Only 


00 


00 


00 


E 


R14 


Cursor 
Address (H) 




Read/ 
Write 


XX 


XX 


XX 


F 


R15 


Cursor 
Address (L) 




Read/ 
Write 


XX 


XX 


XX 


10 


R16 


Light Pen (H) 


- 


Read 
Only 


XX 


XX 


XX 


11 


R17 


Light Pen (L) 


- 


Read 
Only 


XX 


XX 


XX 


Note: All register values are given in hexadecimal 



6845 Register Description 



Color/Graphics Monitor Adapter 17 



Color-Select Register 

The color-select register is a 6-bit output-only register. Its I/O 
address is hex 3D9, and it can be written to using a processor 
'out' command. The following are the bit definitions for this 
register. 

Bit Selects blue border color in 40 by 25 alphanumeric 
mode. 

Selects blue background color (CO-Cl) in 320 by 200 
graphics mode. 

Selects blue foreground color in 640 by 200 graphics 
mode. 

Bit 1 Selects green border color in 40 by 25 alphanumeric 
mode. 

Selects green background color (CO-Cl) in 320 by 200 
graphics mode. 

Selects green foreground color in 640 by 200 graphics 
mode. 

Bit 2 Selects red border color in 40 by 25 alphanumeric mode. 
Selects red background color (CO-Cl) in 320 by 200 
graphics mode. 

Selects red foreground color in 640 by 200 graphics 
mode. 

Bit 3 Selects intensified border color in 40 by 25 
alphanumeric mode. 

Selects intensified background color (CO-Cl) in 320 by 
200 graphics mode. 

Selects intensified foreground color in 640 by 200 
graphics mode. 

Bit 4 Selects alternate, intensified set of colors in the graphics 
mode. 
Selects background colors in the alphanumeric mode. 

Bit 5 Selects active color set in 320 by 200 graphics mode. 



18 Color/ Graphics Monitor Adapter 



When bit 5 is set to 1, colors are determined as follows: 



CI 


CO 


Set Selected 





1 
1 




1 



1 


Background (Defined by bits 0-3 of port hex 3D9) 

Cyan 

Magenta 

White 



When bit 5 is set to 0, colors are determined as follows: 



CI 


CO 


Set Selected 





1 
1 




1 



1 


Background (Defined by bits 0-3 of port hex 3D9) 

Green 

Red 

Brown 



Bit 6 Not used 
Bit 7 Not used 



Mode-Control Register 

The mode-control register is a 6-bit output-only register. Its I/O 
address is hex 3D8, and it can be written to using a processor 
*out' command. The following are bit definitions for this register. 

Bit A 1 selects 80 by 25 alphanumeric mode. 
A selects 40 by 25 alphanumeric mode. 

Bit 1 A 1 selects 320 by 200 graphics mode. 
A selects alphanumeric mode. 

Bit 2 A 1 selects black-and-white mode. 
A selects color mode. 

Bit 3 A 1 enables the video signal. The video signal is 
disabled when changing modes. 



Color/Graphics Monitor Adapter 19 



Bit 4 A 1 selects the high-resolution (640 by 200) 

black-and-white graphics mode. One of eight colors can 
be selected on direct-drive monitors in this mode by 
using register hex 3D9. 

Bit 5 A 1 will change the character background intensity to 
the bUnking attribute function for alphanumeric modes. 
When the high-order attribute is not selected, 16 
background colors or intensified colors are available. 
This bit is set to 1 to allow the blinking function. 



Mode-Control Register Summary 



Bits 






1 


2 


3 


4 


5 








1 







1 
















1 


1 





1 







1 


1 













1 





1 


1 







z 





1 










z 





1 


1 




1 


z 



40 X 25 Alphanumeric Black-and-White 

40 X 25 Alphanumeric Color 

80 X 25 Alphanumeric Black-and-White 

80 X 25 Alphanumeric Color 

320 X 200 Black-and-White Graphics 

320 X 200 Color Graphics 

640 X 200 Black-and-White Graphics 






Enable Blink Attribute 
640 X 200 Black-and-White 
Enable Video Signal 
Select Black-and-White Mode 
Select 320 x 200 Graphics 
80 X 25 Alphanumeric Select 



z = don't care condition 

Note: The low-resolution (160 by 100) mode requires special programming and is 
set up as the 40 by 25 alphanumeric mode. 



20 Color/Graphics Monitor Adapter 



Status Register 

The status register is a 4-bit read-only register. Its I/O address is 
hex 3DA, and it can be read using the processor 4n' instruction. 
The following are bit definitions for this register. 

Bit A 1 indicates that a regen-buff er memory access can be 
made without interfering with the display. 

Bit 1 A 1 indicates that a positive-going edge from the light 
pen has set the light pen's trigger. This trigger is reset 
when power is turned on and may also be cleared by a 
processor 'out' command to hex address 3DB. No 
specific data setting is required; the action is 
address-activated. 

Bit 2 The Ught pen switch is reflected in this bit. The switch 
is not latched or debounced. A indicates that the 
switch is on. 

Bit 3 A 1 indicates that the raster is in a vertical retrace mode. 
Screen-buffer updating can be performed at this time. 



Sequence of Events for Changing Modes 

1 Determine the mode of operation. 

2 Reset the video-enable bit in the mode-control register. 

3 Program the 6845 CRT Controller to select the mode. 

4 Program the mode-control and color-select registers 
including re-enabUng the video. 



Color/Graphics Monitor Adapter 21 



Memory Requirements 

The memory used by this adapter is self-contained. It consists of 
16K bytes of memory without parity. This memory is used as 
both a display buffer for alphanumeric data and as a bit map for 
graphics data. The regen buffer's address starts at hex B8000. 



Read/Write Memory 
Address Space (in hex) 



System 

Read/Write 

Memory 



Display Buffer 
(16K Bytes) 



01000 



AOOOO 



B8000 



BCOOO 



COOOO 



"^ 



1 28K Reserved 
Regen Area 



22 Color/Graphics Monitor Adapter 



Specifications 



The following pages contain card and connector specifications for 
the IBM Color/Graphics Monitor Adapter. 



Color/ Graphics Monitor Adapter 23 



Color Composite 
Signal Phono Jack 




Color Direct 
Drive 9-Pin 
D-Shell Connector 





At Standard TTL Levels 
Ground 


1 










Ground 


2 






^ Red 


3 




IBM Color Display 


Green 


4 


Color/Grj 


or other Direct-Drive 


Blue 


5 


Direct-Dr 


Monitor 


Intensity 


6 


Adapter 




Reserved 


7 






Horizontal Drive 


8 






^ Vertical Drive 


9 














Composite Phono Jack 
Hookup to Monitor 



Video 
Monitor 



Composite Video Signal of 
Approximately 1 .5 Volts 

Peak to Peak Amplitude 



Chassis Ground 



Color/Graphics 
Composite Jack 



Connector Specifications (Part 1 of 2) 



24 Color/Graphics Monitor Adapter 



PI (4-Pin Berg Strip) 
for RF Modulator 



P2 (6- Pin Berg Strip) 
for Light-Pen 
Connector 



Color/Graphics 
Monitor Adapter 




RF 
Modulator 



+ 1 2 Volts 



(key) Not Used 



Composite Video Output 



Logic Ground 



Color/Graphics 

Monitor 

Adapter 



RF Modulator Interface 





- Light Pen Input 


1 




Light 
Pen 


(key) Not Used 


2 


Color/Graphics 
Monitor 


- Light Pen Switch 


3 




Chassis Ground 


4 


Adapter 




^ +5 Volts 


5 






+ 12 Volts 


6 













Light Pen Interface 

Connector Specifications (Part 2 of 2) 



Color/Graphics Monitor Adapter 25 



26 Color/ Graphics Monitor Adapter 



Logic Diagrams 



The following pages contain the logic diagrams for the IBM 
Color/Graphics Monitor Adapter. 



Color/ Graphics Monitor Adapter 27 



00 

O 

I 

n 

S 
I 

t 




Color/Graphics Monitor Adapter (Sheet 1 of 6) 



n 



I 



g- 






1^ 




Color/Graphics Monitor Adapter (Sheet 2 of 6) 



o 

O 
o 

b: 

o 



o 
o 

> 

a. 




(6) -LPEN INPUT 



Color/Graphics Monitor Adapter (Sheet 3 of 6) 



n 

© 

5" 

*^ 
'^ 

O 
ft 



© 
B. 



a. 




Color/Graphics Monitor Adapter (Sheet 4 of 6) 






o 
B. 



a. 




Color/Graphics Monitor Adapter (Sheet 5 of 6) 



(5) COUP VID 



i 



O 
o 



© 
B. 







iininmiiniiin mini 



CIO C2^ Cr7 CIB CI2 Cm 



r I 







LOGIC 










GROUND 




NC 















-LPEN SW (2) 
-LPEN INPUT (3) 



X UM2 



^>f 



-lOR 


(3,6) 




(1.3) 


-MEMW 


(3,4) 






Color/Graphics Monitor Adapter (Sheet 6 of 6) 



34 Color/Graphics Monitor Adapter 



Index 



alphanumeric mode 6 

B 

basic operations 12 



change modes 21 
character generator 5 
color-select register 1 8 
composite color generator 6 
controller 5 



D 



description 1 
display buffer 5 



Index- 1 



graphics modes 9 

high-resolution black-and-white 1 1 
low-resolution color 9 
medium-resolution color 9 



H 

high-resolution black-and-white graphics mode 1 1 



logic diagrams 27 

low-resolution color/graphics mode 9 



M 



medium-resolution color/graphics mode 9 
memory requirements 22 
mode set register 5 
mode types 

alphanumeric 6 

graphics 9 
mode-control register 19 
mode-control register summary 20 
modes of operation 1 



Index-2 



programming considerations 15 

programming the mode control and status register 1 5 

programming the 6845 crt controller 15 



R 



registers 

color-select 18 

mode control and status 15 

mode set 5 

mode-control 19 

status 21 



sequence of events for changing modes 21 
specifications 23 
status register 21 



timing generator 6 



Index-3 



Index-4 



Personal Computer 



IBM Enhanced Graphics 
Adapter 



Contents 



Description 1 

Major Components 3 

Modes of Operation 5 

Basic Operations 8 

Registers 12 

Programming Considerations 62 

Programming the Registers 62 

RAM Loadable Character Generator 69 

Creating a 512 Character Set 70 

Creating an 80 by 43 Alphanumeric Mode 71 

Vertical Interrupt Feature 72 

Creating a Split Screen 73 

Compatibility Issues 74 

Interface 76 

Feature Connector 76 

Specifications 79 

System Board Switches 79 

Configuration Switches 80 

Direct Drive Connector 83 

Light Pen Interface 84 

Jumper Descriptions 85 

Logic Diagrams 87 

BIOS Listing 103 

Vectors with Special Meanings 103 

Index Index-1 



VI 



Description 



The IBM Enhanced Graphics Adapter (EGA) is a graphics 
controller that supports both color and monochrome direct drive 
displays in a variety of modes. In addition to the direct drive port, 
a light pen interface is provided. Advanced features on the 
adapter include bit-mapped graphics in four planes and a RAM 
(Random Access Memory) loadable character generator. Design 
features in the hardware substantially reduce the software 
overhead for many graphics functions. 

The Enhanced Graphics Adapter provides Basic Input Output 
System (BIOS) support for both alphanumeric (A/N) modes and 
all-points-addressable (APA) graphics modes, including all modes 
supported by the Monochrome Display Adapter and the 
Color/Graphics Monitor Adapter. Other modes provide APA 
640x350 pel graphics support for the IBM Monochrome Display, 
full 16 color support in both 320x200 pel and 640x200 pel 
resolutions for the IBM Color Display, and both A/N and APA 
support with resolution of 640x350 for the IBM Enhanced Color 
Display. In alphanumeric modes, characters are formed from one 
of two ROM (Read Only Memory) character generators on the 
adapter. One character generator defines 7x9 characters in a 
9x14 character box. For Enhanced Color Display support, the 
9x14 character set is modified to provide an 8x14 character set. 
The second character generator defines 7x7 characters in an 8x8 
character box. These generators contain dot patterns for 256 
different characters. The character sets are identical to those 
provided by the IBM Monochrome Display Adapter and the IBM 
Color/Graphics Monitor Adapter. 

The adapter contains 64K bytes of storage configured as four 
16K byte bit planes. Memory expansion options are available to 
expand the adapter memory to 128K bytes or 25 6K bytes. 

The adapter is packaged on a single 13-1/8 inch (333.50 mm) 
card. The direct drive port is a right-angle mounted connector at 
the rear of the adapter and extends through the rear panel of the 
system unit. Also on the card are five large scale integration 
(LSI) modules custom designed for this controller. 



August 2, 1984 IBM Enhanced Graphics Adapter 1 



Located on the adapter is a feature connector that provides access 
to internal functions through a 32-pin berg connector. A separate 
64-pin connector provides an interface for graphics memory 
expansion. 

The following is a block diagram of the Enhanced Graphics 
Adapter: 



CPU 
Addr. 

CPU 
Data' 



♦-^ 



ROM 



CRTC 
LSI 



MUX 



SEQ 
LSI 



GRAPH 
LSI 



GRAPH 
LSI 



¥▼▼ 



BIT ' 
MAP 



BIT 
MAP 



ATTRIB 
LSI 



-^ DIRECT 
± DRIVE 
I> OUTPUT 



Enhanced Graphics Adapter Block Diagram 



2 IBM Enhanced Graphics Adapter 



August 2, 1984 



Major Components 

CRT Controller 

The CRT (Cathode Ray Tube) Controller (CRTC) generates 
horizontal and vertical synchronous timings, addressing for the 
regenerative buffer, cursor and underline timings, and refresh 
addressing for the dynamic RAMs. 



Sequencer 

The Sequencer generates basic memory timings for the dynamic 
RAMs and the character clock for controlling regenerative 
memory fetches. It allows the processor to access memory during 
active display intervals by inserting dedicated processor memory 
cycles periodically between the display memory cycles. Map 
mask registers are available to protect entire memory maps from 
being changed. 



Graphics Controller 

The Graphics Controller directs the data from the memory to the 
attribute controller and the processor. In graphics modes, 
memory data is sent in serialized form to the attribute chip. In 
alpha modes the memory data is sent in parallel form, bypassing 
the graphics controller. The graphics controller formats the data 
for compatible modes and provides color comparators for use in 
color painting modes. Other hardware facilities allow the 
processor to write 32 bits in a single memory cycle, (8 bits per 
plane) for quick color presetting of the display areas, and 
additional logic allows the processor to write data to the display 
on non-byte boundaries. 



Attribute Controller 

The Attribute Controller provides a color palette of 16 colors, 
each of which may be specified separately. Six color outputs are 



August 2, 1984 IBM Enhanced Graphics Adapter 3 



available for driving a display. Blinking and underlining are 
controlled by this chip. This chip takes data from the display 
memory and formats it for display on the CRT screen. 



Display Buffer 

The display buffer on the adapter consists of 64K bytes of 
dynamic read/ write memory configured as four 16K byte video 
bit planes. Two options are available for expanding the graphics 
memory. The Graphics Memory Expansion Card plugs into the 
memory expansion connector on the adapter, and adds one bank 
of 16K to each of the four bit planes, increasing the graphics 
memory to 128K bytes. The expansion card also provides DIP 
sockets for further memory expansion. Populating the DIP 
sockets with the Graphics Memory Module Kit adds two 
additional 16K banks to each bit plane, bringing the graphics 
memory to its maximum of 25 6K bytes. 

The address of the display buffer can be changed to remain 
compatible with other video cards and application software. Four 
locations are provided. The buffer can be configured at segment 
address hex AOOOO for a length of 128K bytes, at hex AOOOO for 
a length of 64K bytes, at hex BOOOO for a length of 32K bytes, or 
at hex B8000 for a length of 32K bytes. 



BIOS 

A read-only memory (ROM) Basic Input Output System (BIOS) 
module on the adapter is linked to the system BIOS. This ROM 
BIOS contains character generators and control code and is 
mapped into the processor address at hex COOOO for a length of 
16K bytes. 



Support Logic 

The logic on the card surrounding the LSI modules supports the 
modules and creates latch buses for the CRT controller, the 



4 IBM Enhanced Graphics Adapter August 2, 1984 



processor, and character generator. Two clock sources (14 MHz 
and 16 MHz) provide the dot rate. The clock is multiplexed 
under processor I/O control. The four I/O registers on the card 
are not part of the LSI devices. 



Modes of Operation 
IBM Color Display 

The following table describes the modes supported by BIOS on 
the IBM Color Display: 









Alpha 


Buffer 


Box 


Max. 




Mode# 


Type 


Colors 


Format 


Start 


Size 


Pages 


Resolution 





A/N 


16 


40x25 


B8000 


8x8 


8 


320x200 


1 


A/N 


16 


40x25 


B8000 


8x8 


8 


320x200 


2 


A/N 


16 


80x25 


B8000 


8x8 


4/8/8 


640x200 


3 


A/N 


16 


80x25 


B8000 


8x8 


4/8/8 


640x200 


4 


APA 


4 


40x25 


B8000 


8x8 


1 


320x200 


5 


APA 


4 


40x25 


B8000 


8x8 


1 


320x200 


6 


APA 


2 


80x25 


B8000 


8x8 


1 


640x200 


D 


APA 


16 


40x25 


AOOOO 


8x8 


2/4/8 


320x200 


E 


APA 


16 


80x25 


AOOOO 


8x8 


1/2/4 


640x200 



Modes through 6 emulate the support provided by the IBM 
Color/Graphics monitor Adapter. 

Modes 0, 2, and 5 are identical to modes 1,3, and 4, respectively, 
at the adapter's direct drive interface. 

The "MAX. PAGES" fields for modes 2, 3, D, and E indicate the 
number of pages supported when 64K, 128K, or 25 6K bytes of 
graphics memory is installed, respectively. 



January 20, 1986 



IBM Enhanced Graphics Adapter 5 



IBM Monochrome Display 

The following table describes the modes supported by BIOS on 
the IBM Monochrome Display. 



Mode# 


Type 


Colors 


Alpha 
Format 


Buffer 
Start 


Box 
Size 


Max. 
Pages 


Resolution 


7 
F 


A/N 
APA 


4 
4 


80x25 
80x25 


BOOOO 
AOOOO 


9x14 
8x14 


4/8 
1/2 


720x350 
640x350 



The ''MAX. PAGES" fields for modes 7 and F indicate the 
number of pages supported when either 64K or greater than 64K 
of graphics memory is installed, respectively. 

Mode 7 emulates the support provided by the IBM Monochrome 
Display Adapter. 



IBM Enhanced Color Display 

The Enhanced Graphics Adapter supports attachment of the IBM 
Enhanced Color Display. The IBM Enhanced Color Display is 
capable of running at the standard television frequency of 15.75 
KHz as well as running.21.85 KHz. The tabl^ below summarizes 
the characteristics of the IBM Enhanced Color Display: 



Parameter 


TV Frequency 


High Resolution 


Horiz Scan Rate 


15.75 KHz. 


21.85 KHz. 


Vertical Scan Rate 


60 Hz. 


60 Hz. 


Video Bandwidth 


14.318 MHz. 


16.257 MHz. 


Displayable Colors 


16 Maximum 


16 or 64 


Character Size 


7 by 7 Pels 


7 by 9 Pels 


Character Box Size 


8 by 8 Pels 


8 by 14 Pels 


Maximum Resolution 


640x200 Pels 


640 by 350 Pels 


Alphanumeric Modes 


0,1,2,3 


0,1,2,3 


Graphics Modes 


4,5,6,D,E 


10 



In the television frequency mode, the IBM Enhanced Color 
Display displays information identical in color and resolution to 
the IBM Color Display. 



6 IBM Enhanced Graphics Adapter 



January 20, 1986 



In the high resolution mode, the adapter provides enhanced 
alphanumeric character support. This enhanced alphanumeric 
support consists of transforming the 8 by 8 character box into an 
8 by 14 character box, and providing 16 colors out of a palette of 
64 possible display colors. Display colors are changed by altering 
the programming of the color palette registers in the Attribute 
Controller. In alphanumeric modes, any 16 of 64 colors are 
displayable. The screen resolution is 320x350 for modes and 1, 
and 640x350 for modes 2 and 3. 

The resolution displayed on the IBM Enhanced Color Display is 
selected by the switch settings on the Enhanced Graphics 
Adapter. 

The Enhanced Color Display is compatible with all modes listed 
for the IBM Color Display. The following table describes 
additional modes supported by BIOS for the IBM Enhanced 
Color Display: 









Alpha 


Buffer 


Box 


Max. 




Mode# 


Type 


Colors 


Format 


Start 


Size 


Pages 


Resolution 


0* 


A/N 


16/64 


40x25 


B8000 


8x14 


8 


320x350 


1* 


A/N 


16/64 


40x25 


B8000 


8x14 


8 


320x350 


2* 


A/N 


16/64 


80x25 


B8000 


8x14 


4/8 


640x350 


3* 


A/N 


16/64 


80x25 


B8000 


8x14 


4/8 


640x350 


10 


APA 


4/16 
16/64 


80x25 


AOOOO 


8x14 


1/2 


640x350 



* Note that modes 0, 1,2, and 3 are also listed for IBM Color 
Display support. BIOS provides enhanced support for these 
modes when an Enhanced Color Display is attached. 

The values in the "COLORS" field indicate 16 colors of a 64 
color palette or 4 colors of a sixteen color palette. 

In modes 2, 3, and 10, the dual values for the "COLORS" field 
and the "MAX. PAGES" field indicate the support provided 
when either 64K or greater than 64K of graphics memory is 
installed, respectively. 



January 20, 1986 



IBM Enhanced Graphics Adapter 7 



Basic Operations 
Alphanumeric Modes 

The data format for alphanumeric modes on the Enhanced 
Graphics Adapter is the same as the data format on the IBM 
Color/Graphics Monitor Adapter and the IBM Monochrome 
Display Adapter. As an added function, bit three of the attribute 
byte may be redefined by the Character Map Select register to act 
as a switch between character sets. This gives the programmer 
access to 512 characters at one time. This function is valid only 
when memory has been expanded to 128K bytes or more. 

When an alphanumeric mode is selected, the BIOS transfers 
character patterns from the ROM to bit plane 2. The processor 
stores the character data in bit plane 0, and the attribute data in 
bit plane 1 . The programmer can view bit planes and 1 as a 
single buffer in alphanumeric modes. The CRTC generates 
sequential addresses, and fetches one character code byte and one 
attribute byte at a time. The character code and row scan count 
address bit plane 2, which contains the character generators. The 
appropriate dot patterns are then sent to the palette in the 
attribute chip, where color is assigned according to the attribute 
data. 



Graphics Modes 



320x200 Two and Four Color Graphics (Modes 4 and 5) 

Addressing, mapping and data format are the same as the 
320x200 pel mode of the Color/Graphics Monitor Adapter. The 
display buffer is configured at hex B8000. Bit image data is 
stored in bit planes and 1. 



640x200 Two Color Graphics (Mode 6) 

Addressing, mapping and data format are the same as the 
640x200 pel black and white mode of the Color/Graphics 



8 IBM Enhanced Graphics Adapter January 20, 1986 



Monitor Adapter. The display buffer is configured at hex B8000. 
Bit image data is stored in bit plane 0. 



640x350 Monochrome Graphics (Mode F ) 

This mode supports graphics on the IBM Monochrome Display 
with the following attributes: black, video, blinking video, and 
intensified video. Resolution of 640x350 requires 56K bytes to 
support four attributes. By chaining maps and 1, then maps 2 
and 3 together, two 32K bit planes can be formed. This chaining 
is done only when necessary (less than 128K of graphics 
memory). The first map is the video bit plane, and the second 
map is the intensity bit plane. Both planes reside at hex address 
AOOOO. 

Two bits, one from each bit plane, define one picture element 
(pel) on the screen. The bit definitions for the pels are given in 
the following table. The video bit plane is denoted by CO and the 
Intensity Bit Plane is denoted by C2. 



C2 


CO 


Pixel Color 


Valid Attributes 





1 
1 




1 



1 


Black 
Video 

Blinking Video 
Intensified Video 



3 
C 
F 



The byte organization in memory is sequential. The first eight 
pels on the screen are defined by the contents of memory in 
location AOOOiOH, the second eight pels by location A000:1H, 
and so on. The first pel within any one byte is defined by bit 7 in 
the byte. The last pel within the byte is defined by bit in the 
byte. 

Monochrome graphics works in odd/even mode, which means 
that even CPU addresses go into even bit planes and odd CPU 
addresses go into odd bit planes. Since both bit planes reside at 
address AOOOO, the user must select which plane or planes he 
desires to update. This is accomplished by the map mask register 
of the sequencer. (See the table above for valid attributes). 



August 2, 1984 



IBM Enhanced Graphics Adapter 9 



16/64 Color Graphics Modes (Mode 10) 

These modes support graphics in 16 colors on either a medium or 
high resolution monitor. The memory in these modes consists of 
using all four bit planes. Each bit plane represents a color as 
shown below. The bit planes are denoted as C0,C1,C2 and C3 
respectively. 

CO = Blue Pels 
CI = Green Pels 
C2 = Red Pels 
C3 = Intensified Pels 

Four bits (one from each plane) define one pel on the screen. 
The color combinations are illustrated in the following table: 



1 


R 


G 


B 


Color 














Black 













Blue 








1 





Green 








1 




Cyan 





1 








Red 





1 







Magenta 





1 


1 





Brown 





1 


1 




White 













Dark Gray 












Light Blue 







1 





Light Green 







1 




Light Cyan 




1 








Light Red 




1 







Light Magenta 




1 


1 





Yellow 




1 


1 




Intensified White 



The display buffer resides at address AOOOO. The map mask 
register of the sequencer is used to select any or all of the bit 
planes to be updated when a memory write to the display buffer is 
executed by the CPU. 



Color Mapping 

The Enhanced Graphics Adapter supports 640x350 Graphics for 
both the IBM Monochrome and the IBM Enhanced Color 



10 IBM Enhanced Graphics Adapter 



August 2, 1984 



Displays. Four color capability is supported on the EGA without 
the Graphics Memory Expansion Card (base 64 KB), and sixteen 
colors are supported when the Graphics Memory Expansion Card 
is installed on the adapter (128 KB or above). This section 
describes the differences in the colors displayed depending upon 
the graphics memory available. Note that colors OH, IH, 4H, and 
7H map directly regardless of the graphics memory available. 



Character 
Attribute 


Monochrome 


Model OH 
64KB 


Model OH 
>64KB 


OOH* 


Black 


Black 


Black 


01 H* 


Video 


Blue 


Blue 


02 H 


Black 


Black 


Green 


03 H 


Video 


Blue 


Cyan 


04H* 


Blinking 


Red 


Red 


05 H 


Intensified 


White 


Magenta 


06H 


Blinking 


Red 


Brown 


07H* 


Intensified 


White 


White 


08 H 


Black 


Black 


Dark Gray 


09 H 


Video 


Blue 


Light Blue 


OAH 


Black 


Black 


Light Green 


OBH 


Video 


Blue 


Light Cyan 


OCH 


Blinking 


Red 


Light Red 


ODH 


Intensified 


White 


Light Magenta 


OEH 


Blinking 


Red 


Yellow 


OFH 


Intensified 


White 


Intensified White 



* Graphics character attributes which map directly regardless of 
the graphics memory available. 



August 2, 1984 



IBM Enhanced Graphics Adapter 11 



Registers 

External Registers 

This section contains descriptions of the registers of the Enhanced 
Graphics Adapter that are not contained in an LSI device. 



Name 


Port 


Index 


Miscellaneous Output Register 
Feature Control Register 
Input Status Register 
Input Status Register 1 


3C2 
3?A 
3C2 
3?2 


- 


? = B In Monochrome Modes ? = D In Color Modes 



Miscellaneous Output Register 

This is a write-only register. The processor output port address is 
hex 3C2. A hardware reset causes all bits to reset to zero. 



Miscellaneous Output Register Format 



Bit 



7 6 5 4 3 2 10 






I/O Address Select 
Enable Ram 
Clock Select 
Clock Select 1 

Disable Internal Video Drivers 
Page Bit For Odd/Even 
Horizontal Retrace Polarity 
Vertical Retrace Polarity 



BitO 



3BX/3DX CRTC I/O Address— This bit maps 
the CRTC I/O addresses for IBM Monochrome 
or Color/Graphics Monitor Adapter emulation. 
A logical sets CRTC addresses to 3BX and 
Input Status Register 1 's address to 3BA for 
Monochrome emulation. A logical 1 sets CRTC 



12 IBM Enhanced Graphics Adapter 



August 2, 1984 



addresses to 3DX and Input Status Register Ts 
address to 3DA for Color/Graphics Monitor 
Adapter emulation. 

Bit 1 Enable RAM — A logical disables RAM from 

the processor; a logical 1 enables RAM to 
respond at addresses designated by the Control 
Data Select value programmed into the Graphics 
Controllers. 

Bit 2-Bit 3 Clock Select — These two bits select the clock 

source according to the following table: 

Bits 

3 2 

0- Selects 14 MHz clock from the processor 
I/O channel 

1- Selects 16 MHz clock on-board oscillator 

1 0- Selects external clock source from the 

feature connector. 
11- Not used 

Bit 4 Disable Internal Video Drivers — A logical 

activates internal video drivers; a logical 1 
disables internal video drivers. When the internal 
video drivers are disabled, the source of the direct 
drive color output becomes the feature connector 
direct drive outputs. 

Bit 5 Page Bit For Odd/Even — Selects between two 

64K pages of memory when in the Odd/Even 
modes (0,1,2,3,7). A logical selects the low 
page of memory; a logical 1 selects the high page 
of memory. 

Bit 6 Horizontal Retrace Polarity — A logical selects 

positive horizontal retrace; a logical 1 selects 
negative horizontal retrace. 

Bit 7 Vertical Retrace Polarity — A logical selects 

positive vertical retrace; a logical 1 selects 



August 2, 1984 IBM Enhanced Graphics Adapter 13 



negative vertical retrace. The IBM Monochrome 
display requires a negative vertical retrace 
polarity. 



Feature Control Register 

This is a write-only register. The processor output register is hex 
3BA or 3DA. 



Feature Control Register Format 



Bit 



7 ( 


3 t 


5 ^ 


% : 


5 : 


2 


1 


—► 












► 



Feature Control Bit 
Feature Control Bit 1 
Reserved 
Not Used 



Bits and 1 Feature Control Bits — These bits are used to 
convey information to the feature connector. 
The output of these bits goes to the FEAT (pin 
19) and FEAT 1 (pin 17) of the feature 
connector. 



Input Status Register Zero 

This is a read-only register. The processor input port address is 
hex 3C2. 



14 IBM Enhanced Graphics Adapter 



August 2, 1984 



Input Status Register Zero Format 


Bit 


T i 


3 i 


5 A 


t 3 2 1 


Not Used 
Switch Sense 
Reserved 
Reserved 
CRT Interrupt 





















Bit 4 



Switch Sense — When set to 1, this bit allows the 
processor to read the four configuration switches 
on the board. The setting of the CLKSEL field 
determines which switch is being read. The 
switch configuration can be determined by 
reading byte 40:88H in RAM. 

Bit 3: Switch 4 ; Logical = switch closed 
Bit 2: Switch 3 ; Logical = switch closed 
Bit 1 : Switch 2 ; Logical = switch closed 
Bit 0: Switch 1 ; Logical = switch closed 



Bits 5 and 6 Feature Code — These bits are input from the 
Feat (0) and Feat (1) pins on the feature 
connector. 



Bit? 



CRT Interrupt — A logical 1 indicates video is 
being displayed on the CRT screen; a logical 
indicates that vertical retrace is occurring. 



Input Status Register One 

This is a read-only register. The processor port address is hex 
3BA or hex 3DA. 



August 2, 1984 



IBM Enhanced Graphics Adapter 15 



Input Status Register One Format 



Bit 



7 6 5 4 3 2 10 



► 



Display Enable 
Light Pen Strobe 
Light Pen Switch 
Vertical Retrace 
Diagnostic 1 
Diagnostic 
Not Used 



BitO 



Bitl 



Bit 2 



Bit 3 



Bits 4 and 5 



Display Enable — Logical indicates the CRT 
raster is in a horizontal or vertical retrace 
interval. This bit is the real time status of the 
display enable signal. Some programs use this 
status bit to restrict screen updates to inactive 
display intervals. The Enhanced Graphics 
Adapter does not require the CPU to update the 
screen buffer during inactive display intervals to 
avoid glitches in the display image. 

Light Pen Strobe — A logical indicates that the 
light pen trigger has not been set; a logical 1 
indicates that the Ught pen trigger has been set. 

Light Pen Switch — A logical indicates that the 
light pen switch is closed; a logical 1 indicates 
that the Ught pen switch is open. 

Vertical Retrace — A logical indicates that video 
information is being displayed on the CRT 
screen; a logical 1 indicates the CRT is in a 
vertical retrace interval. This bit can be 
programmed to interrupt the processor on 
interrupt level 2 at the start of the vertical 
retrace. This is done through bits 4 and 5 of the 
Vertical Retrace End Register of the CRTC. 

Diagnostic Usage — These bits are selectively 
connected to two of the six color outputs of the 



16 IBM Enhanced Graphics Adapter 



August 2, 1984 



Attribute Controller. The Color Plane Enable 
register controls the multiplexer for the video 
wiring. The following table illustrates the 
combinations available and the color output 
wiring. 



Color Plane 
Register 


Input Status 
Register One 


Bits Bit 4 


Bits Bit 4 




1 

1 

1 1 


Red Blue 
Secondary Blue Green 
Secondary Red Secondary Green 
Not Used Not Used 



August 2, 1984 



IBM Enhanced Graphics Adapter 17 



Sequencer Registers 



Name 


Port 


Index 


Address 


3C4 


- 


Reset 


3C5 


00 


Clocking Mode 


3C5 


01 


Map Mask 


3C5 


02 


Character Map Select 


3C5 


03 


Memory Mode 


3C5 


04 



Sequencer Address Register 

The Address Register is a pointer register located at address hex 
3C4. This register is loaded with a binary value that points to the 
sequencer data register where data is to be written. This value is 
referred to as "Index" in the table above. 



Sequencer Address Register Format 



Bit 



7 6 5 4 3 2 10 



Sequencer Address 
Not Used 



Bit 0-Bit 3 



Sequencer Address Bits — ^A binary value pointing 
to the register where data is to be written. 



Reset Register 

This is a write-only register pointed to when the value in the 
address register is hex 00. The output port address for this 
register is hex 3C5. 



18 IBM Enhanced Graphics Adapter 



August 2, 1984 



Reset Register Format 



Bit 



7 6 5 4 3 2 10 






Asynchronous Reset 
Synchronous Reset 
Not Used 



BitO 



Bitl 



Asynchronous Reset — A logical commands the 
sequencer to asynchronous clear and halt. All 
outputs are placed in the high impedance state 
when this bit is a 0. A logical 1 commands the 
sequencer to run unless bit 1 is set to zero. 
Resetting the sequencer with this bit can cause 
data loss in the dynamic RAMs. 

Synchronous Reset — A logical commands the 
sequencer to synchronous clear and halt. Bits 1 
and must both be ones to allow the sequencer 
to operate. Reset the sequencer with this bit 
before changing the Clocking Mode Register, if 
memory contents are to be preserved. 



Clocking Mode Register 

This is a write-only register pointed to when the value in the 
address register is hex 01. The output port address for this 
register is hex 3C5. 



Clocking Mode Register Format 



Bit 



7 6 5 4 



3 2 10 

1 ^ 





8/9 Dot Clocks 
Bandwidth 
Sliift Load 
Dot Clock 
Not Used 



August 2, 1984 



IBM Enhanced Graphics Adapter 19 



Bit 8/9 Dot Clocks— A logical directs the 

sequencer to generate character clocks 9 dots 
wide; a logical 1 directs the sequencer to generate 
character clocks 8 dots wide. Monochrome 
alphanumeric mode (07H) is the only mode that 
uses character clocks 9 dots wide. All other 
modes must use 8 dots per character clock. 

Bit 1 Bandwidth — A logical makes CRT memory 

cycles occur on 4 out of 5 available memory 
cycles; a logical 1 makes CRT memory cycles 
occur on 2 out of 5 available memory cycles. 
Medium resolution modes require less data to be 
fetched from the display buffer during the 
horizontal scan time. This allows the CPU 
greater access time to the display buffer. All high 
resolution modes must provide the CRTC with 4 
out of 5 memory cycles in order to refresh the 
display image. 

Bit 2 Shift Load — When set to 0, the video serializers 

are reloaded every character clock; when set to 1 , 
the video serializers are loaded every other 
character clock. This mode is useful when 16 bits 
are fetched per cycle and chained together in the 
shift registers. 

Bit 3 Dot Clock — A logical selects normal dot clocks 

derived from the sequencer master clock input. 
When this bit is set to 1 , the master clock will be 
divided by 2 to generate the dot clock. All the 
other timings will be stretched since they are 
derived from the dot clock. Dot clock divided by 
two is used for 320x200 modes (0, 1, 4, 5) to 
provide a pixel rate of 7 MHz, (9 MHz for mode 
D). 



Map Mask Register 

This is a write-only register pointed to when the value in the 
address register is hex 02. The output port address for this 
register is hex 3C5. 



20 IBM Enhanced Graphics Adapter August 2, 1984 



Map Mask Register Format 



Bit 



r 6 5 4 3 2 1 





- 










► 



1 Enables Map 
1 Enables Map 1 
1 Enables Map 2 
1 Enables Map 3 
Not Used 



Bit 0-Bit 3 Map Mask — A logical 1 in bits 3 through 

enables the processor to write to the 
corresponding maps 3 through 0. If this register 
is programmed with a value of OFH, the CPU can 
perform a 32-bit write operation with only one 
memory cycle. This substantially reduces the 
overhead on the CPU during display update 
cycles in graphics modes. Data scrolling 
operations are also enhanced by setting this 
register to a value of OFH and writing the display 
buffer address with the data stored in the CPU 
data latches. This is a read-modify-write 
operation. When odd/even modes are selected, 
maps and 1 and maps 2 and 3 should have the 
same map mask value. 



Character Map Select Register 

This is a write-only register pointed to when the value in the 
address register is hex 03. The output port address for this 
register is 3 C5. 



August 2, 1984 



IBM Enhanced Graphics Adapter 21 



Character Map Select Register Format 



Bit 7 6 5 4 3 2 10 



-► Character Map Select B 
-► Character Map Select A 
-► Not Used 



Bit 0-Bit 1 Character Map Select B — ^Selects the map used 

to generate alpha characters when attribute bit 3 
is a 0, according to the following table: 



Bits 
1 


Map 
Selected 


Table Location 


Value 



1 

1 

1 1 




1 
2 
3 


1 St 8K of Plane 2 BankO 
2nd 8K of Plane 2 Bank 1 
3rd 8K of Plane 2 Bank 2 
4th 8K of Plane 2 Bank 3 



Bit 2-Bit 3 Character Map Select A — Selects the map used 

to generate alpha characters when attribute bit 3 
is a 1, according to the following table: 



Bits 
3 2 


Map 
Selected 


Table Location 


Value 



1 

1 

1 1 



1 
2 
3 


1 St 8K of Plane 2 BankO 
2nd 8K of Plane 2 Bank 1 
3rd 8K of Plane 2 Bank 2 
4th 8K of Plane 2 Bank 3 



In alphanumeric modes, bit 3 of the attribute byte normally has 
the function of turning the foreground intensity on or off. This 
bit however may be redefined as a switch between character sets. 
This function is enabled when there is a difference between the 
value in Character Map Select A and the value in Character Map 
Select B. Whenever these two values are the same, the character 
select function is disabled. The memory mode register bit 1 must 
be a 1 (indicates the memory extension card is installed in the 
unit) to enable this function; otherwise, bank is always selected. 



22 IBM Enhanced Graphics Adapter 



August 2, 1984 



128K of graphics memory is required to support two character 
sets. 256K supports four character sets. Asynchronous reset 
clears this register to 0. This should be done only when the 
sequencer is reset. 



Memory Mode Register 

This is a write-only register pointed to when the value in the 
address register is hex 04. The processor output port address for 
this register is 3C5. 



Memory Mode Register Format 



Bit 



7 6 5 4 3 2 10 



U 



Alpha 

Extended Memory 

Odd/Even 

Not Used 



BitO 



Bitl 



Bit 2 



Alpha — A logical indicates that a non-alpha 
mode is active. A logical 1 indicates that alpha 
mode is active and enables the character 
generator map select function. 

Extended Memory — A logical indicates that the 
memory expansion card is not installed. A logical 
1 indicates that the memory expansion card is 
installed and enables access to the extended 
memory through address bits 14 and 15. 

Odd/Even — A logical directs even processor 
addresses to access maps and 2, while odd 
processor addresses access maps 1 and 3. A 
logical 1 causes processor addresses to 
sequentially access data within a bit map. The 
maps are accessed according to the value in the 
map mask register. 



Aij^st 2, 1984 



IBM Enhanced Graphics Adapter 23 



CRT Controller Registers 



Name 


Port 


Index 


Address Register 


3?4 


- 


Horizontal Total 


3?5 


00 


Horizontal Display End 


3?5 


01 


Start Horizontal Blank 


3?5 


02 


End Horizontal Blank 


3?5 


03 


Start Horizontal Retrace 


3?5 


04 


End Horizontal Retrace 


3?5 


05 


Vertical Total 


3?5 


06 


Overflow 


3?5 


07 


Preset Row Scan 


3?5 


08 


Max Scan Line 


3?5 


09 


Cursor Start 


3?5 


OA 


Cursor End 


3?5 


OB 


Start Address High 


3?5 


OC 


Start Address Low 


3?5 


OD 


Cursor Location High 


3?5 


OE 


Cursor Location Low 


3?5 


OF 


Vertical Retrace Start 


3?5 


10 


Light Pen High 


3?5 


10 


Vertical Retrace End 


3?5 


11 


Light Pen Low 


3?5 


11 


Vertical Display End 


3?5 


12 


Offset 


3?5 


13 


Underline Location 


3?5 


14 


Start Vertical Blank 


3?5 


15 


End Vertical Blank 


3?5 


16 


Mode Control 


3?5 


17 


Line Compare 


3?5 


18 


? = B in Monochrome Mod 


es and D 


in Color Modes 



CRT Controller Address Register 

The Address register is a pointer register located at hex 3B4 or 
hex 3D4. If an IBM Monochrome Display is attached to the 
adapter, address 3B4 is used. If a color display is attached to the 
adapter, address 3D4 is used. This register is loaded with a binary 
value that points to the CRT Controller data register where data 
is to be written. This value is referred to as "Index" in the table 
above. 



24 IBM Enhanced Graphics Adapter 



August 2, 1984 



CRT Controller Address Register Format 



Bit 



7 6 5 4 3 2 10 



CRTC Address 
Not Used 



Bit 0-Bit 4 CRT Controller Address Bits— A binary value 

pointing to the CRT Controller register where 
data is to be written. 



Horizontal Total Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 00. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



Horizontal Total Register Format 


Bit 7 6 5 4 3 2 10 


Horizontal Total 





This register defines the total number of characters in the 
horizontal scan interval including the retrace time. The value 
directly controls the period of the horizontal retrace output signal. 
An internal horizontal character counter counts character clock 
inputs to the CRT Controller, and all horizontal and vertical 
timings are based upon the horizontal register. Comparators are 
used to compare register values with horizontal character values 
to provide horizontal timings. 

Bit 0-Bit 7 Horizontal Total — The total number of 

characters less 2. 



August!, 1984 



IBM Enhanced Graphics Adapter 25 



Horizontal Display Enable End Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 01. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



Horizontal Display Enable End Register Format 


Bit 


7 6 5 4 3 2 10 





This register defines the length of the horizontal display enable 
signal. It determines the number of displayed character positions 
per horizontal Une. 

Bit 0-Bit 7 Horizontal display enable end — A value one less 

than the total number of displayed characters. 



Start Horizontal Blanking Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 02. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



Start Horizontal Blanking Register Format 


Bit 


7 6 5 4 3 2 10 

hfc Start Vertical RIankinn 





This register determines when the horizontal blanking output 
signal becomes active. The row scan address and underline scan 
line decode outputs are multiplexed on the memory address 
outputs and cursor outputs respectively during the blanking 
interval. These outputs are latched external to the CRT 
Controller with the f aUing edge of the BLANK output signal. 
The row scan address and underline signals remain on the output 
signals for one character count beyond the end of the blanking 
signal. 



26 IBM Enhanced Graphics Adapter August 2, 1984 



Bit 0-Bit 7 Start Horizontal Blanking — The horizontal 

blanking signal becomes active when the 
horizontal character counter reaches this value. 



End Horizontal Blanking Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 03. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



End Horizontal Blanking Register Format 



Bit 



7 e 


) £ 


) 4 


3 


2 


1 











1 ► 



End Blanking 

Display Enable Skew Control 



^ Not Used 



This register determines when the horizontal blanking output 
signal becomes inactive. The row scan address and underline scan 
line decode outputs are multiplexed on the memory address 
outputs and the cursor outputs respectively during the blanking 
interval. These outputs are latched external to the CRT 
Controller with the falling edge of the BLANK output signal. 
The row scan address and underline signals remain on the output 
signals for one character count beyond the end of the blanking 
signal. 



Bit 0-Bit 4 End Horizontal Blanking — A value equal to the 
five least significant bits of the horizontal 
character counter value at which time the 
horizontal blanking signal becomes inactive 
(logical 0). To obtain a blanking signal of width 
W, the following algorithm is used: Value of 
Start Blanking Register + Width of Blanking 
signal in character clock units = 5-bit result to be 
programmed into the End Horizontal Blanking 
Register. 



August 2, 1984 IBM Enhanced Graphics Adapter 27 



Bit 5-Bit 6 Display Enable Skew Control — These two bits 

determine the amount of display enable skew. 
Display enable skew control is required to 
provide sufficient time for the CRT Controller to 
access the display buffer to obtain a character 
and attribute code, access the character generator 
font, and then go through the Horizontal Pel 
Panning Register in the Attribute Controller. 
Each access requires the display enable signal to 
be skewed one character clock unit so that the 
video output is in synchronization with the 
horizontal and vertical retrace signals. The bit 
values and amount of skew are shown in the 
following table: 

Bits 
6 5 

Zero character clock skew 

1 One character clock skew 

1 Two character clock skew 

1 1 Three character clock skew 



Start Horizontal Retrace Pulse Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 04. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



start Horizontal Retrace Pulse Register Format 


Bit 


7 6 5 4 3 2 10 





This register is used to center the screen horizontally, and to 
specify the character position at which the Horizontal Retrace 
Pulse becomes active. 



28 IBM Enhanced Graphics Adapter August 2, 1984 



Bit 0-Bit 7 Start Horizontal Retrace Pulse — The value 

programmed is a binary count of the character 
position number at which the signal becomes 
active. 



End Horizontal Retrace Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 05. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



End Horizontal Retrace Register Format 



Bit 7 6 5 4 3 2 10 



> 
► 
► 



End Horizontal Retrace 
Horizontal Retrace Delay 
Start Odd Memory Address 



This register specifies the character position at which the 
Horizontal Retrace Pulse becomes inactive (logical 0). 

Bit 0-Bit 4 End Horizontal Retrace — A value equal to the 

five least significant bits of the horizontal 
character counter value at which time the 
horizontal retrace signal becomes inactive (logical 
0). To obtain a retrace signal of width W, the 
following algorithm is used: Value of Start 
Retrace Register + width of horizontal retrace 
signal in character clock units = 5 -bit result to be 
programmed into the End Horizontal Retrace 
Register. 

Bit 5-Bit 6 Horizontal Retrace Delay — These bits control 
the skew of the horizontal retrace signal. Binary 
00 equals no Horizontal Retrace Delay. For 
some modes, it is necessary to provide a 
horizontal retrace signal that takes up the entire 
blanking interval. Some internal tunings are 
generated by the falling edge of the horizontal 
retrace signal. To guarantee the signals are 



August 2, 1984 IBM Enhanced Graphics Adapter 29 



latched properly, the retrace signal is started 
before the end of the display enable signal, and 
then skewed several character clock times to 
provide the proper screen centering. 

Bit 7 Start Odd/Even Memory Address — This bit 

controls whether the first CRT memory address 
output after a horizontal retrace begins with an 
even or an odd address. A logical selects even 
addresses; a logical 1 selects odd addresses. This 
bit is used for horizontal pel panning applications. 
Generally, this bit should be set to a logical 0. 



Vertical Total Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 06. The processor output port 
address for this register is hex 3B5 or 3D5. 



Vertical Total Register Format 


Bit 7 6 5 4 3 2 10 


Vertical Total 





Bit 0-Bit 7 Vertical Total — This is the low-order eight bits of 

a nine-bit register. The binary value represents 
the number of horizontal raster scans on the CRT 
screen, including vertical retrace. The value in 
this register determines the period of the vertical 
retrace signal. Bit 8 of this register is contained 
in the CRT Controller Overflow Register hex 07 
bitO. 



CRT Controller Overflow Register 

This is a write-only register pointed to when the value in the CRT 
Controller Address Register is hex 07. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



30 IBM Enhanced Graphics Adapter August 2, 1984 



CRTC Overflow Register Format 



Bit 



7 6 5 



\ : 


I 2 


> 1 




► 








► 



Vertical Total Bit 8 

Vertical Display Enable End Bit 8 

Vertical Retrace Start Bit 8 

Start Vertical Blank Bit 8 

Line Compare Bit 8 

Cursor Location Bit 8 

Not Used 



BitO 
Bitl 

Bit 2 
Bit 3 
Bit 4 
Bits 



Vertical Total — Bit 8 of the Vertical Total 
register (index hex 06). 

Vertical Display Enable End — Bit 8 of the 
Vertical Display Enable End register (index hex 
12). 

Vertical Retrace Start — Bit 8 of the Vertical 
Retrace Start register (index hex 10). 

Start Vertical Blank— Bit 8 of the Start Vertical 
Blank register (index hex 15). 

Line Compare — Bit 8 of the Line Compare 
register (index hex 18). 

Cursor Location — Bit 8 of the Cursor Location 
register (index hex OA). 



Preset Row Scan Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 08. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



August 2, 1984 



IBM Enhanced Graphics Adapter 31 



Preset Row Scan Register Format 



Bit 



7 6 5 4 3 2 10 



Starting Row Scan Count after 
a Vertical Retrace 

Not Used 



This register is used for pel scrolling. 



Bit 0-Bit 4 Preset Row Scan (Pel Scrolling)— This register 

specifies the starting row scan count after a 
vertical retrace. The row scan counter 
increments each horizontal retrace time until a 
maximum row scan occurs. At maximum row 
scan compare time the row scan is cleared (not 
preset). 



Maximum Scan Line Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 09. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



Maximum Scan Line Register Format 


Bit / 


' i 


3 i 


5 4 3 2 10 

- 1 ^ ^/I^Yimllm Rrnn 1 ino 


^ Mnt 1 IqoH 




1 



Bit 0-Bit 4 Maximum Scan Line — This register specifies the 

number of scan Unes per character row. The 
number to be programmed is the maximum row 
scan number minus one. 



Cm-sor Start Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex OA. The processor output port 



32 IBM Enhanced Graphics Adapter 



August 2, 1984 



address for this register is hex 3B5 or hex 3D5. 



Cursor Start Register Format 



Bit 



7 6 5 4 3 2 1 



Row Scan Cursor Begins 
Not Used 



Bit 0-Bit 4 Cursor Start — This register specifies the row scan 

of a character line where the cursor is to begin. 
The number programmed should be one less than 
the starting cursor row scan. 



Cursor End Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex OB. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



Cursor End Register Format 



Bit 



7 6 5 4 3 2 10 






Row Scan Cursor Ends 
Cursor Skew Control 
Not Used 



Bit 0-Bit 4 Cursor End — These bits specify the row scan 

where the cursor is to end. 

Bit 5-Bit 6 Cursor Skew — These bits control the skew of the 

cursor signal. 



August 2, 1984 



IBM Enlianced Graphics Adapter 33 



Bits 
6 5 

Zero character clock skew 

1 One character clock skew 

1 Two character clock skew 

1 1 Three character clock skew 



Start Address High Register 

This is a read/ write register pointed to when the value in the CRT 
Controller address register is hex OC. The processor 
input/output port address for this register is hex 3B5 or hex 3D5. 



start Address High Register Format 



Bit 7 6 5 4 3 2 10 

J — ► High Order Start Address 



Bit 0-Bit 7 Start Address High — These are the high-order 

eight bits of the start address. The 16-bit value, 
from the high-order and low-order start address 
registers, is the first address after the vertical 
retrace on each screen refresh. 



Start Address Low Register 

This is a read/ write register pointed to when the value in the CRT 
Controller address register is hex OD. The processor 
input/output port address for this register is hex 3B5 or hex 3D5. 



Start Address Low Register Format 



Bit 7 6 5 4 3 2 10 

III 



Low Order Start Address 



34 IBM Enhanced Graphics Adapter August 2, 1984 



Bit 0-Bit 7 Start Address Low — These are the low-order 8 

bits of the start address. 



Cursor Location High Register 

This is a read/ write register pointed to when the value in the CRT 
Controller address register is hex OE. The processor input/output 
port address for this register is hex 3B5 or hex 3D5. 



Cursor Location High Register Format 


Bit 


7 6 5 4 3 2 10 


High Order Cursor Location 





Bit 0-Bit 7 Cursor Location High — These are the high-order 

8 bits of the cursor location. 



Cursor Location Low Register 

This is a read/ write register pointed to when the value in the CRT 
Controller address register is hex OF. The processor input/output 
port address for this register is hex 3B5 or Hex 3D5. 



Cursor Location Low Register Format 


Bit 


7 6 5 4 3 2 10 


Low Order Cursor Location 





Bit 0-Bit 7 Cursor Location Low — These are the low-order 

8 bits of the cursor location. 



August 2, 1984 IBM Enhanced Graphics Adapter 35 



Vertical Retrace Start Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 10. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



Vertical Retrace Start Register Format 



Bit 7 6 5 4 3 2 10 

J — ^. Low Order Vertical Retrace Pulse 



Bit 0-Bit 7 Vertical Retrace Start — This is the low-order 8 

bits of the vertical retrace pulse start position 
programmed in horizontal scan lines. Bit 8 is in 
the overflow register location hex 07. 



Light Pen High Register 

This is a read-only register pointed to when the value in the CRT 
Controller address register is hex 10. The processor input port 
address for this register is hex 3B5 or hex 3D5. 



Light Pen (High Register Format 



Bit 7 6 5 4 3 2 10 



High Order Memory Address 
Counter 



Bit 0-Bit 7 Light Pen High — This is the high order 8 bits of 

the memory address counter at the time the light 
pen was triggered. 



Vertical Retrace End Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 11. The processor output port 



36 IBM Enhanced Graphics Adapter August 2, 1984 



address for this register is hex 3B5 or hex 3D5. 



Vertical Retrace End Register Format 



Bit 7 6 5 4 3 2 10 



-► Vertical Retrace End 



-► 0=Clear Vertical Interrupt 
-► 0=Enable Vertical Interrupt 



-► Not Used 



Bit 0-Bit 3 



Bit 4 
Bits 



Vertical Retrace End — These bits determine the 
horizontal scan count value when the vertical 
retrace output signal becomes inactive. The 
register is programmed in units of horizontal scan 
lines. To obtain a vertical retrace signal of width 
W, the following algorithm is used: Value of Start 
Vertical Retrace Register + width of vertical 
retrace signal in horizontal scan units = 4-bit 
result to be programmed into the End Horizontal 
Retrace Register. 

Clear Vertical Interrupt — A logical will clear a 
vertical interrupt. 

Enable Vertical Interrupt — A logical will 
enable vertical interrupt. 



Light Pen Low Register 

This is a read-only register pointed to when the value in the CRT 
Controller address register is hex 11. The processor input port 
address for this register is hex 3B5 or 3D5. 



August 2, 1984 



IBM Enhanced Graphics Adapter 37 



Light Pen Low Register Format 


Bit 7 6 5 4 3 2 10 

1 1 1 1 1 




Low Order Memory Address 
Counter 







Bit 0-Bit 7 Light Pen Low — This is is the low-order 8 bits of 
the memory address counter at the time the light 
pen was triggered. 



Vertical Display Enable End Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 12. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



Vertical Display Enable End Register Format 


Bit 


7 6 5 4 3 2 10 

w 1 ow Order Vertical DisnlaY 


Enable End 



Bit 0-Bit 7 Vertical Display Enable End— These are the 

low-order 8 bits of the vertical display enable end 
position. This address specifies which scan line 
ends the active video area of the screen. Bit 8 is 
in the overflow register location hex 07. 



Offset Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 13. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



38 IBM Enhanced Graphics Adapter August 2, 1984 



Offset Register Format 


Bit 7 6 5 4 3 2 10 

II 1 II. 


Logical line width of the screen 





Bit 0-Bit 7 Offset — This register specifies the logical line 

width of the screen. The starting memory 
address for the next character row is larger than 
the current character row by this amount. The 
Offset Register is programmed with a word 
address. Depending upon the method of clocking 
the CRT Controller, this word address is either a 
word or double word address. 



Underline Location Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 14. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



Underline Location Register Format 



Bit 7 6 5 4 3 2 10 



Horizontal row scan where 
underline will occur 

Not Used 



Bit 0-Bit 4 Underline Location — This register specifies the 

horizontal row scan on which underline will 
occur. The value programmed is one less than 
the scan line number desired. 



Start Vertical Blanking Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 15. The processor output port 



August 2, 1984 



IBM Enhanced Graphics Adapter 39 



address for this register is hex 3B5 or hex 3D5. 



Start Vertical Blanking Register Format 



Bit 7 6 5 4 3 2 10 



-► Start Vertical Blanking 



Bit 0-Bit 7 Start Vertical Blank — These are the low 8 bits of 

the horizontal scan line count, at which the 
vertical blanking signal becomes active. Bit 8 bit 
is in the overflow register hex 07. 



End Vertical Blanking Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 16. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



End Vertical Blanking Register Format 



Bit 



7 6 5 4 3 2 1 



End Vertical Blanking 
Not Used 



Bit 0-Bit 4 End Vertical Blank — This register specifies the 
horizontal scan count value when the vertical 
blank output signal becomes inactive. The 
register is programmed in units of horizontal scan 
lines. To obtain a vertical blank signal of width 
W, the following algorithm is used: Value of Start 
Vertical Blank Register + width of vertical blank 
signal in horizontal scan units = 5 -bit result to be 
programmed into the End Vertical Blank 
Register. 



40 IBM Enhanced Graphics Adapter 



August 2, 1984 



Mode Control Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 17. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



Mode Control Register Format 


Bit 


7 


D , 


5 ^ 


x : 


3 


2 1 







CMSO 

Select Row Scan Counter 
Horizontal Retrace Select 
Count by Two 
Output Control 
Address Wrap 
Word/Byte Mode 
Hardware Reset 








































^ 









BitO 



Compatibility Mode Support — When this bit is 
a logical 0, the row scan address bit is 
substituted for memory address bit 13 during 
active display time. A logical 1 enables memory 
address bit 13 to appear on the memory address 
output bit 13 signal of the CRT Controller. The 
CRT Controller used on the IBM 
Color/Graphics Monitor Adapter is the 6845. 
The 6845 has 128 horizontal scan line address 
capability. To obtain 640 by 200 graphics 
resolution, the CRTC was programmed for 100 
horizontal scan lines with 2 row scan addresses 
per character row. Row scan address bit 
became the most significant address bit to the 
display buffer. Successive scan Unes of the 
display image were displaced in memory by 8K 
bjrtes. This bit allows compatibility with the 
6845 and Color Graphics APA modes of 
operation. 



August 2, 1984 



IBM Enhanced Graphics Adapter 41 



Bit 1 Select Row Scan Counter — A logical selects 

row scan counter bit 1 on MA 14 output pin. A 
logical 1 selects MA 14 counter bit on MA 14 
output pin. 

Bit 2 Horizontal Retrace Select — This bit selects 

Horizontal Retrace or Horizontal Retrace divided 
by 2 as the clock that controls the vertical timing 
counter. This bit can be used to effectively 
double the vertical resolution capability of the 
CRT Controller. The vertical counter has a 
maximum resolution of 512 scan lines due to the 
9-bit wide Vertical Total Register. If the vertical 
counter is clocked with the horizontal retrace 
divided by 2 clock, then the vertical resolution is 
doubled to 1024 horizontal scan lines. A logical 
selects HRTC and a logical 1 selects HRTC 
divided by 2. 

Bit 3 Count By Two — When this bit is set to 0, the 

memory address counter is clocked with the 
character clock input. A logical 1 clocks the 
memory address counter with the character clock 
input divided by 2. This bit is used to create 
either a byte or word refresh address for the 
display buffer. 

Bit 4 Output Control — A logical enables the module 

output drivers. A logical 1 forces all outputs into 
high impedance state. 

Bit 5 Address Wrap — This bit selects Memory Address 

counter bit MA 13 or bit MA 15, and it appears 
on the MA output pin in the word address 
mode. If you are not in the word address mode, 
MA counter output appears on the MA 
output pin. A logical 1 selects MA 15. In 
odd/even mode, bit MA 13 should be selected 
when the 64K memory is installed on the board. 
Bit MA 15 should be selected when greater then 
64K memory is installed. This function is used to 
implement Color Graphics Monitor Adapter 
compatibility. 



42 IBM Enhanced Graphics Adapter August 2, 1984 



Bit 6 



Word Mode or Byte Mode — When this bit is a 
logical 0, the Word Mode shifts all memory 
address counter bits down one bit, and the most 
significant bit of the counter appears on the least 
significant bit of the memory address outputs. 
See table below for address output details. A 
logical 1 selects the Byte Address mode. 





Internal Memory Address Counter 
Wiring to the Output Multiplexer 


CRTC Out Pin 


Byte Address 
Mode 


Word Address 
Mode 


MAO/RFAO 
MA1/RFA1 
MA2/RFA2 

MA3/RFA3 

* 
* 
* 

MA14/RS3 
MA15/RS4 


MAO 
MAI 
MA 2 

MA 3 

* 
* 
• 

MA 14 
MA 15 


MA15orMA13 

MAO 

MA1 

MA 2 

* 
• 

MA 13 
MA 14 



Bit? 



Hardware Reset — A logical forces horizontal 
and vertical retrace to clear. A logical 1 forces 
horizontal and vertical retrace to be enabled. 



Line Compare Register 

This is a write-only register pointed to when the value in the CRT 
Controller address register is hex 18. The processor output port 
address for this register is hex 3B5 or hex 3D5. 



Line Compare Register Format 


Bit 7 6 5 4 3 2 10 

1 1 . 


Line Compare Target 





Bit 0-Bit 7 Line Compare — This register is the low-order 8 
bits of the compare target. When the vertical 



August 2, 1984 



IBM Enhanced Graphics Adapter 43 



counter reaches this value, the internal start of 
the line counter is cleared. This allows an area of 
the screen to be immune to scrolling. Bit 8 of 
this register is in the overflow register hex 07. 



44 IBM Enhanced Graphics Adapter August 2, 1984 



Graphics Controller Registers 



Name 


Port 


Index 


Graphics 1 Position 


3CC 


_ 


Graphics 2 Position 


3CA 


- 


Graphics 1 & 2 Address 


3CE 


- 


Set/Reset 


3CF 


00 


Enable Set/Reset 


3CF 


01 


Color Compare 


3CF 


02 


Data Rotate 


3CF 


03 


Read Map Select 


3CF 


04 


Mode Register 


3CF 


05 


Miscellaneous 


3CF 


06 


Color Don't Care 


3CF 


07 


Bit Mask 


3CF 


08 



Graphics 1 Position Register 

This is a write-only register. The processor output port address 
for this register is hex 3CC. 



Graphics I Position Register Format 



Bit 



7 6 5 4 3 2 1 



u 



Position 
► Position 1 
■► Not Used 



Bit 0-Bit 1 Position — These 2 bits are binary encoded 

hierarchy bits for the graphics chips. The 
position register controls which 2 bits of the 
processor data bus each chip responds to. 
Graphics 1 must be programmed with a position 
register value of for this card. 



August 2, 1984 



IBM Enhanced Graphics Adapter 45 



Graphics 2 Position Register 

This is a write-only register. The processor output port address 
for this register is hex 3CA. 



Graphics II Position Register Format 



Bit 



7 6 5 4 3 2 10 



u 



Position 
^- Position 1 



-► Not Used 



Bit 0-Bit 1 Position — These 2 bits are binary encoded 

hierarchy bits for the graphics chips. The 
position register controls which 2 bits of the 
processor data bus to which each chip responds. 
Graphics 2 must be programmed with a position 
register value of 1 for this card. 



Graphics 1 and 2 Address Register 

This is a write-only register and the processor output port address 
for this register is hex 3CE. 



Graphics 1 and 2 Address Register Formats 



Bit 



7 6 5 4 3 2 10 



Graphics Address 
Not Used 



Bit 0-Bit 3 Graphics 1 and 2 Address Bits — This output loads 
the address register in both graphics chips 
simultaneously. This register points to the data 
register of the graphics chips. 



46 IBM Enhanced Graphics Adapter 



August 2, 1984 



Set/Reset Register 

This is a write-only register pointed to by the value in the 
Graphics 1 and 2 address register. This value must be hex 00 
before writing can take place. The processor output port address 
for this register is hex 3CF. 



Set/Reset Register Format 



Bit 



7 ( 


5 t 


3 ^ 


[ : 


3 : 


2 















1 ► 

► 










1 ^ 



-Set/Reset Bit 
-Set/Reset Bit 1 



-►Set/Reset Bit 2 



-►Set/Reset Bit 3 



>- Not Used 



Bit 0-Bit 3 Set/Reset — These bits represent the value 

written to the respective memory planes when the 
processor does a memory write with write mode 
selected and set/reset mode is enabled. 
Set/Reset can be enabled on a plane by plane 
basis with separate OUT commands to the 
Set/Reset register. 



Enable Set/Reset Register 

This is a write-only register and is pointed to by the value in the 
Graphics 1 and 2 address register. This value must be hex 01 
before writing can take place. The processor output port for this 
register is hex 3CF. 



January 20, 1986 



IBM Enhanced Graphics Adapter 47 



Enable Set/Reset Register Format 



Bit 



u 



Enable Set/Reset Bit 
► Enable Set/Reset Bit 1 



-►Enable Set/Reset Bit 2 



-►Enable Set/Reset Bit 3 
-►Not Used 



Bit 0-Bit 3 Enable Set/Reset — These bits enable the 

set/reset function. The respective memory plane 
is written with the value of the Set/Reset register 
provided the write mode is 0. When write mode is 
and Set/Reset is not enabled on a plane, that 
plane is written with the value of the processor 
data. 



Color Compare Register 

This is a write-only register pointed to by the value in the 
Graphics 1 and 2 address register. This value must be hex 02 
before writing can take place. The processor output port address 
for this register is hex 3CF. 



Color Compare Register Format 



Bit 



u 



Color Compare 
-►Color Compare 1 
-► Color Compare 2 
-► Color Compare 3 
-► Not Used 



Bit 0-Bit 3 Color Compare — These bits represent a 4 bit 

color value to be compared. If the processor sets 



48 IBM Enhanced Graphics Adapter 



January 20, 1986 



read mode 1 on the graphics chips, and does a 
memory read, the data returned from the memory 
cycle will be a 1 in each bit position where the 4 
bit planes equal the color compare register. 



Data Rotate Register 

This is a write-only register pointed to by the value in the 
Graphics 1 and 2 address register. This value must be hex 03 
before writing can take place. The processor output port address 
for this register is hex 3CF. 



Data Rotate Register Format 



Bit 



7 6 5 



[ 3 


2 


1 

1 ► 

► 



Rotate Count 
Rotate Count 1 
Rotate Count 2 
Function Select 
Not Used 



Bit 0-Bit 2 Rotate Count — These bits represent a binary 

encoded value of the number of positions to 
rotate the processor data bus during processor 
memory writes. This operation is done when the 
write mode is 0. To write unrotated data the 
processor must select a count of 0. 

Bit 3-Bit 4 Function Select — Data written to memory can 

operate logically with data already in the 
processor latches. The bit functions are defined 
in the following table. 



August 2, 1984 



IBM Enhanced Graphics Adapter 49 



Bits 
4 3 

Data unmodified. 

1 Data AND'ed with latched data. 

1 Data OR'ed with latched data. 

1 1 Data XOR'ed with latched data. 

Data may be any of the choices selected by the Write Mode 
Register except processor latches. If rotated data is selected, the 
rotate applies before the logical function. 



Read Map Select Register 

This is a write-only register pointed to by the value in the 
Graphics 1 and 2 address register. This value must be hex 04 
before writing can take place. The processor output port address 
for this register is hex 3CF. 



Read Map Select Register Format 



Bit 



7 6 5 4 3 2 10 



u 



Map Select 
Map Select 1 
Map Select 2 
Not Used 



Bit 0-Bit 2 Map Select — These bits represent a binary 

encoded value of the memory plane number from 
which the processor reads data. This register has 
no effect on the color compare read mode 
described elsewhere in this section. 



Mode Register 

This is a write-only register pointed to by the value in the 
Graphics 1 and 2 address register. This value must be hex 05 



50 IBM Enhanced Graphics Adapter 



August 2, 1984 



before writing can take place. The processor output port address 
for this register is 3CF. 



Mode Register Format 



Bit 



7 6 5 4 3 2 10 



^ 
^ 
#- 



Write Mode 

Test Condition 

Read IVIode 

Odd/Even 
^" Shift Register Mode 
^ Not Used 



Bit 0-Bit 1 



Write Mode 



Bits 
1 

Each memory plane is written with the 
processor data rotated by the number of 
counts in the rotate register, unless 
Set/Reset is enabled for the plane. Planes 
for which Set/Reset is enabled are written 
with 8 bits of the value contained in the 
Set/Reset register for that plane. 

1 Each memory plane is written with the 

contents of the processor latches. These 
latches are loaded by a processor read 
operation. 

1 Memory plane n (0 through 3) is filled 

with 8 bits of the value of data bit n. 
1 1 Not Valid 



Bit 2 



The logic function specified by the function select 
register also applies. 

Test Condition — A logical 1 directs graphics 
controller outputs to be placed in high impedance 
state for testing. 



August 2, 1984 



IBM Enhanced Graphics Adapter 51 



Bit 3 



Bit 4 



Bits 



Read Mode— When this bit is a logical 0, the 
processor reads data from the memory plane 
selected by the read map select register. When 
this bit is a logical 1, the processor reads the 
results of the comparison of the 4 memory planes 
and the color compare register. 

Odd/Even — A logical 1 selects the odd/even 
addressing mode, which is useful for emulation of 
the Color Graphics Monitor Adapter compatible 
modes. Normally the value here follows the value 
of the Memory Mode Register bit 3 of the 
Sequencer. 

Shift Register — A logical 1 directs the shift 
registers on each graphics chip to format the 
serial data stream with even numbered bits on the 
even numbered maps and odd numbered bits on 
the odd maps. 



Miscellaneous Register 

This is a write-only register pointed to by the value in the 
Graphics 1 and 2 address register. This value must be hex 06 
before writing can take place. The processor output port for this 
register is hex 3CF. 



Miscellaneous Register Format 



Bit 7 6 5 4 



5 2 


> 1 

► 



Graphics Mode 
Chain Odd Maps to Even 
Memory MapO 
Memory Map 1 
Not Used 



52 IBM Enhanced Graphics Adapter 



August 2, 1984 



Bit Graphics Mode — This bit controls alpha-mode 

addressing. A logical 1 selects graphics mode. 
When set to graphics mode, the character 
generator address latches are disabled. 

Bit 1 Chain Odd Maps To Even Maps — ^When set to 1 , 

this bit directs the processor address bit to be 
replaced by a higher order bit and odd/even 
maps to be selected with odd/even values of the 
processor AO bit, respectively. 

Bit 2-Bit 3 Memory Map — These bits control the mapping of 

the regenerative buffer into the processor address 
space. 

Bits 

3 2 



Hex AOOO for 128K bytes. 

1 Hex AOOO for 64K bytes. 

1 Hex BOOO for 32K bytes 
1 1 Hex B800 for 32K bytes. 

If the display adapter is mapped at address hex AOOO for 128K 
bytes, no other adapter can be installed in the system. 



Color Don't Care Register 

This is a write-only register and is pointed to by the value in the 
Graphics 1 and 2 address register. This value must be hex 07 
before writing can take place. The processor output port for this 
register is hex 3CF. 



August 2, 1984 IBM Enhanced Graphics Adapter 53 



Color Don't Care Register Format 



Bit 



7 6 5 4 



J 2 


I 1 

u 

I ► 




► 



Color Plane 0=Don't Care 
Color Plane 1 =Don't Care 
Color Plane 2=Don't Care 
Color Plane 3=Don't Care 
Not Used 



BitO 



Color Don't Care — Color plane O=don't care 
when reading color compare when this bit is set to 
1. 



Bitl 



Color Don't Care — Color plane 1= don't care 
when reading color compare when this bit is set to 
1. 



Bit 2 



Color Don't Care — Color plane 2=don't care 
when reading color compare when this bit is set to 
1. 



Bit 3 



Color Don't Care — Color plane 3=don't care 
when reading color compare when this bit is set to 
1. 



Bit Mask Register 

This is a write-only register and is pointed to by the value in the 
Graphics 1 and 2 address register. This value must be hex 08 
before writing can take place. The processor output port for this 
register is hex 3CF. 



Bit Mask Register Format 



Bit 



7 6 5 4 3 2 10 



0-lmmune to change 
1 -Unimpeded Writes 



54 IBM Enhanced Graphics Adapter 



August!, 1984 



Bit 0-Bit 7 Bit Mask — Any bit programmed to n causes tlie 

corresponding bit n in each bit plane to be 
immune to change provided that the location 
being written was the last location read by the 
processor. Bits programmed to a 1 allow 
unimpeded writes to the corresponding bits in the 
))it planes. 

The bit mask applies to any data written by the processor (rotate, 
AND'ed, OR'ed, XOR'ed, DX and S/R). To preserve bits using 
the bit mask, data must be latched internally by reading the 
location. When data is written to preserve the bits, the most 
current data in latches is written in those positions. The bit mask 
applies to all bit planes simultaneously. 



January 20, 1986 IBM Enhanced Graphics Adapter 55 



Attribute Controller Registers 



Name 


Port 


Index 


Address Register 


SCO 


- 


Palette Registers 


SCO 


00-OF 


Mode Control Register 


SCO 


10 


Overscan Color Register 


SCO 


11 


Color Plane Enable Register 


SCO 


12 


Horizontal Pel Panning Register 


SCO 


IS 



Attribute Address Register 

This is a write-only register. The processor output port is hex 
3C0. 



Attribute Address Register Format 



Bit 



■^►Attribute Address 



-^ Palette Address Source 



-►Not Used 



Bit 0"Bit 4 Attribute Address Bits — The Address Register is 

a pointer register located at hex 3 CO. This 
register is loaded with a binary value that points 
to the attribute data register where data is to be 
written. The Attribute Controller does not have 
an address bit input to control selection of the 
address and data registers. An internal address 
flip-flop controls selection of either the address 
or data registers. To initialize the flip-flop, an 
lOR instruction is issued to the Attribute 
Controller at address 3BA or 3DA. This clears 
the flip-flop, and selects the Address Register. 
After the Address Register has been loaded, the 
next OUT instruction loads the data register. 



56 IBM Enhanced Graphics Adapter 



January 20, 1986 



The flip-flop toggles each time an OUT is issued 
to the Attribute Controller. 



Bits 



Palette Address Source — When loading the color 
palette registers, bit 5 must be cleared to 0. To 
enable the memory data to access the color 
palette, bit 5 must be set to 1. 



Palette Register Hex 00 through Hex OF 

This is a write-only register. The processor output port is hex 
3C0. 



Palette Registers Hex 00 through Hex OF Format 



Bit 



1 



u 



Blue Video 
>- Green Video 



-► Red Video 



-^ Secondary Blue/Mono Video 
->^ Secondary Green/Intensity 



-► Secondary Red Video 
-► Not Used 



Bit 0-Bit 5 Palette — These 6-bit registers allow a dynamic 

mapping between the text attribute or graphic 
color input value and the display color in the 
CRT screen. A logical 1 selects the appropriate 
color. A logical de-selects. The color palette 
register should be modified only during the 
vertical retrace interval to avoid glitches in the 
displayed image. Note that some color monitors 
do not have an intensity input and only a 
maximum of eight colors are available. Monitors 
with four color inputs display sixteen colors, and 
monitors with six color inputs display 64 colors. 



January 20, 1986 



IBM Enhanced Graphics Adapter 57 



Mode Control Register 

This is a write-only register pointed to by the value in the 
Attribute address register. This value must be hex 10 before 
writing can take place. The processor output port address for this 
register is hex SCO. 



Mode Control Register Format 



Bit 



7 6 5 4 3 2 1 



u 



Graphics/Alphanumeric Mode 
>- Display Type 



Enable Line Graphics Character 
Codes 



-► Select Background Intensity Or 
Enable Blink 



-► Not Used 



BitO 



Bitl 



Bit 2 



Graphics/ Alphanumeric Mode — A logical 
selects alphanumeric mode. A logical 1 selects 
graphics mode. 

Monochrome Display/ Color Display — A logical 
selects IBM monochrome display attributes. A 
logical 1 selects color Display attributes. 

Enable Line Graphics Character Codes — When 
this bit is set to 0, the ninth dot will be the same 
as the background. A logical 1 enables the 
special line graphics character codes for the IBM 
Monochrome Display adapter. When enabled, 
this bit forces the ninth dot of a Une graphic 
character to be identical to the eighth dot of the 
character. The Une graphics character codes for 
the Monochrome Display Adapter are Hex CO 
through Hex DF. 

For character fonts that do not utilize the Une 
graphics character codes in the range of Hex CO 



58 IBM Enhanced Graphics Adapter 



January 20, 1986 



Bit 3 



through Hex DF, bit 2 of this register should be a 
logical 0. Otherwise unwanted video information 
will be displayed on the CRT screen. 

Enable Blink/Select Background Intensity — A 
logical selects the background intensity of the 
attribute input. This mode was available on the 
Monochrome and Color Graphics adapters. A 
logical 1 enables the bUnk attribute in 
alphanumeric modes. This bit must also be set to 
1 for blinking graphics modes. 



Overscan Color Register 

This is a write-only register pointed to by the value in the 
Attribute address register. This value must be hex 1 1 before 
writing can take place. The processor output port address for this 
register is hex SCO. 



Overscan Color Register Format 


Bit 7 6 5 4: 
1 1 1 


3 2 10 
























Selects Blue Border Color 

Selects Green Border Color 

Selects Red Border Color 

Selects Secondary Blue 
Border Color 




































































Selects Intensified or 
Secondary Green 


















Selects Secondary Red 
Border Color 
















Not Used 






^' 



Bit 0-Bit 5 Overscan Color — This 6-bit register determines 

the overscan (border) color displayed on the 
CRT screen. For monochrome display this 
register should be set to a value of 0. A logical 1 
selects the appropriate color. 



August 2, 1984 



IBM Enhanced Graphics Adapter 59 



Color Plane Enable Register 

This is a write-only register pointed to by the value in the 
Attribute address register. This value must be hex 12 before 
writing can take place. The processor output port address for this 
register is SCO. 



Color Plane Enable Register Format 



Bit 7 6 5 4 3 2 10 






Enable Color Plane 
Video Status MUX 
Not Used 



Bit 0-Bit 3 Enable Color Plane — Writing a logical 1 in any 

of bits through 3 enables the respective display 
memory color plane. 

Bit 4-Bit 5 Video Status MUX — Selects two of the six color 

outputs to be available on the status port. The 
following table illustrates the combinations 
available and the color output wiring. 



COLOR PLANE 
ENABLE REGISTER 


INPUT STATUS 
REGISTER ONE 


Bits Bit 4 


Bits Bit 4 




1 

1 

1 1 


Red Blue 
Secondary Blue Green 
Secondary Red Secondary Green 
Not Used Not Used 



Horizontal Pel Panning Register 

This is a write-only register pointed to by the value in the 
Attribute address register. This value must be hex 12 before 
writing can take place. The processor output port address for this 
register is hex 3 CO. 



60 IBM Enhanced Graphics Adapter 



Aug^st 2, 1984 



Horizontal Pel Panning Register Format 



Bit 7 6 5 4 3 2 10 



Horizontal Pel Panning 
Not Used 



Bit 0-Bit 3 Horizontal Pel Panning — This 4 bit register 

selects the number of picture elements (pels) to 
shift the video data horizontally to the left. Pel 
panning is available in both A/N and APA 
modes. In Monochrome A/N mode, the image 
can be shifted a maximum of 9 pels. In all other 
A/N and APA modes, the image can be shifted a 
maximum of 8 pels. The sequence for shifting 
the image is given below: 

9 pels/character : 8, 0, 1, 2, 3, 4, 5, 6, 7 
(Monochrome A/N mode only) 

8 pels/character : 0, 1, 2, 3, 4, 5, 6, 7 (All other 
Modes) 



August 2, 1984 



IBM Enhanced Graphics Adapter 61 



Programming Considerations 



Programming the Registers 

Each of the LSI devices has an address register and a number of 
data registers. The address register serves as a pointer to the 
other registers on the LSI device. It is a write-only register that is 
loaded by the processor by executing an 'OUT' instruction to its 
I/O address with the index of the selected data register. 

The data registers on each LSI device are accessed through a 
common I/O address. They are distinguished by the pointer 
(index) in the address register. To write to a data register, the 
address register is loaded with the index of the appropriate data 
register, then the selected data register is loaded by executing an 
'OUT' instruction to the common I/O address. 

The external registers that are not part of an LSI device and the 
Graphics I and II registers are not accessed through an address 
register; they are written to directly. 

The following tables define the values that are loaded into the 
registers by BIOS to support the different modes of operation 
supported by this adapter. 



62 IBM Enhanced Graphics Adapter August 2, 1984 



Register 


Mode of Operition 


Nime 


Port 


Index 





1 


2 


3 


4 


5 


6 


7 


D 


E 


F 


10 


FJ 


10$ 


0* 


1* 


2* 


3* 


Miscellaneous 


3C2 


- 


23 


23 


23 


23 


23 


23 


23 


A6 


23 


23 


A2 


A7 


A2 


A7 


A7 


A7 


A7 


A7 


Feature Cntrl 


3?A 


- 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


Input Stat 


3C2 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


Input Stat 1 


3?2 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 




- 


- 


- 


- 


- 


- 


- 


? = B in monochrome modes ? = D in color modes 


Values for these modes when the IBM Enhanced Color Display is attached 


J Values for these modes when greater than 64 K Graphics Memory is installed 



External Registers 



Register 


Mode of Operation 


Name 


Port 


Index 





1 


2 


3 


4 


5 


6 


7 


D 


E 


F 


10 


FJ 


10$ 


0* 


1* 


2* 


3* 


Seq Address 


3C4 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 




- 


- 


- 


- 


- 


- 


- 


Reset 


3C5 


00 


03 


03 


03 


03 


03 


03 


03 


03 


03 


03 


03 


03 


03 


03 


03 


03 


03 


03 


Clocl< Mode 


3C5 


01 


OB 


OB 


01 


01 


OB 


OB 


01 


00 


OB 


01 


05 


05 


01 


01 


OB 


OB 


01 


01 


Map Mask 


3C5 


02 


03 


03 


03 


03 


03 


03 


01 


03 


OF 


OF 


OF 


OF 


OF 


OF 


03 


03 


03 


03 


Char Gen Sel 


3C5 


03 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


Memory Mode 


3C5 


04 


03 


03 


03 


03 


02 


02 


06 


03 


06 


06 


00 


00 


06 


06 


03 


03 


03 


03 


* Values for these modes when the IBM Enhanced Color Display is attached 


Walues for these modes when greater than 64 K Graphics Memory is installed 



Sequencer Registers 



Au^st 2, 1984 



IBM Enhanced Graphics Adapter 63 



Register 


Mode of Operation 


Nime 


Port 


Index 





1 


2 


3 


4 


5 


6 


7 


D 


E 


F 


10 


FJ 


io: 


0* 


1* 


2* 


3* 


Address Reg 


3?4 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


Horiz Total 


3?5 


00 


37 


37 


70 


70 


37 


37 


70 


60 


37 


70 


60 


5B 


60 


5B 


2D 


2D 


5B 


5B 


Hrz Disp End 


3?5 


01 


27 


27 


4F 


4F 


27 


27 


4F 


4F 


27 


4F 


4F 


4F 


4F 


4F 


27 


27 


4F 


4F 


Strt Hrz BIk 


3?5 


02 


2D 


2D 


5C 


5C 


2D 


2D 


59 


56 


2D 


56 


56 


53 


56 


53 


2B 


2B 


53 


53 


End Hrz BIk 


3?5 


03 


37 


37 


2F 


2F 


37 


37 


2D 


3A 


37 


2D 


1A 


17 


3A 


37 


2D 


2D 


37 


37 


Strt Hrz Retr 


3?5 


04 


31 


31 


5F 


5F 


30 


30 


5E 


51 


30 


5E 


50 


50 


50 


52 


28 


28 


51 


51 


End Hrz Retr 


3?5 


05 


15 


15 


07 


07 


14 


14 


06 


60 


14 


06 


EO 


BA 


60 


00 


6D 


6D 


5B 


5B 


Vert Total 


3?5 


06 


04 


04 


04 


04 


04 


04 


04 


70 


04 


04 


70 


6C 


70 


6C 


6C 


6C 


6C 


6C 


Overflow 


3?5 


07 


11 


11 


11 


11 


11 


11 


11 


IF 


11 


11 


IF 


IF 


IF 


IF 


IF 


1F 


IF 


IF 


Preset Row SC 


3?5 


08 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


Max Scan Line 


3?5 


09 


07 


07 


07 


07 


01 


01 


01 


OD 


00 


00 


00 


00 


00 


00 


OD 


OD 


OD 


OD 


Cursor Start 


3?5 


OA 


06 


06 


06 


06 


00 


00 


00 


06 


00 


00 


00 


00 


00 


00 


OB 


OB 


OB 


OB 


Cursor End 


3?5 


OB 


07 


07 


07 


07 


00 


00 


00 


OC 


00 


00 


00 


00 


00 


00 


OC 


OC 


OC 


OC 


Strt Addr Hi 


3?5 


OC 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


Strt Addr Lo 


3?5 


OD 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


" 


- 


- 


- 


- 


? = B in monochrome modes ? = D in color modes 


* Values for these modes when the IBM Enhanced Color Display is attached 


: Values for these modes when greater than 64 K Graphics Memory is installed 



CRT Controller Registers (1 of 2) 



64 IBM Enhanced Graphics Adapter 



August 2, 1984 



Registsr 


Mode of Operation 


Niine 


Port 


Index 





1 


2 


3 


4 


5 


6 


7 


D 


E 


F 


10 


f: 


lo: 


0* 


1* 


2* 


3* 


Cursor LC Hi 


3?5 


OE 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


Cursor LC Low 


3?5 


OF 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


Vrt Retr Strt 


3?5 


10 


El 


El 


El 


E1 


El 


El 


EO 


5E 


El 


EO 


5E 


5E 


5E 


5E 


5E 


5E 


5E 


5E 


Light Pen Hi 


3?5 


10 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


Vert Retr End 


3?5 


11 


24 


24 


24 


24 


24 


24 


23 


2E 


24 


23 


2E 


2B 


2E 


2B 


2B 


2B 


2B 


2B 


Light Pen Low 


3?5 


11 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


Vrt Disp End 


3?5 


12 


C7 


C7 


C7 


C7 


C7 


C7 


C7 


5D 


C7 


C7 


5D 


5D 


5D 


5D 


5D 


5D 


5D 


5D 


Offset 


3?5 


13 


14 


14 


28 


28 


14 


14 


28 


28 


14 


28 


14 


14 


28 


28 


14 


14 


28 


28 


Underline Loc 


3?5 


14 


08 


08 


08 


08 


00 


00 


00 


OD 


00 


00 


OD 


OF 


OD 


OF 


OF 


OF 


OF 


OF 


Strt Vert BIk 


3?5 


15 


EO 


EO 


EO 


EO 


EO 


EO 


DF 


5E 


EO 


DF 


5E 


5F 


5E 


5F 


5E 


5E 


5E 


5E 


End Vert BIk 


3?5 


16 


FO 


FO 


FO 


FO 


FO 


FO 


EF 


6E 


FO 


EF 


6E 


OA 


6E 


OA 


OA 


OA 


OA 


OA 


Mode Control 


3?5 


17 


A3 


A3 


A3 


A3 


A2 


A2 


C2 


A3 


E3 


E3 


8B 


8B 


E3 


E3 


A3 


A3 


A3 


A3 


Line Compare 


3?5 


18 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


? = B in monochrome modes ? = D in color modes 


* Values for these modes when the IBM Enhanced Color Display is attached 


: Values for these modes when greater than 64 K Graphics Memory is installed 



CRT Controller Registers (2 of 2) 



August 2, 1984 



IBM Enhanced Graphics Adapter 65 



Register 


Mode of Operation 


Name 


Port 


Index 





1 


2 


3 


4 


5 


6 


7 


D 


E 


F 


10 


F$ 


m 


0* 


1* 


2* 


3* 


Grphx 1 Pos 


3CC 


- 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


GO 


GO 


Grphx II Pos 


3CA 


- 


01 


01 


01 


01 


01 


01 


01 


01 


01 


01 


01 


01 


01 


01 


01 


01 


01 


01 


Grphx 1 II AD 


3CE 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


Set Reset 


3CF 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


Enable S/R 


3CF 


01 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


Color Compare 


3CF 


02 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


GO 


Data Rotate 


3CF 


03 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


GO 


GO 


Read Map Sel 


3CF 


04 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


GO 


GO 


Mode Register 


3CF 


05 


10 


10 


10 


10 


30 


30 


00 


10 


00 


00 


10 


10 


00 


00 


10 


10 


10 


10 


Miscellaneous 


3CF 


06 


OE 


OE 


OE 


OE 


OF 


OF 


OD 


OA 


05 


05 


07 


07 


05 


05 


OE 


OE 


OE 


OE 


Color No Care 


3CF 


07 


00 


00 


00 


00 


00 


00 


00 


00 


OF 


OF 


OF 


OF 


OF 


OF 


00 


00 


00 


GO 


Bit Mask 


3CF 


08 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


FF 


* Values for these modes when the IBM Enhanced Color Display is attached 


sValues for these modes when greater than 64 K Graphics Memory is installed 



Graphics SI Registers 



66 IBM Enhanced Graphics Adapter 



August!, 1984 



Register 


Mode ol Operition 


Name 


Port 


Index 





1 


2 


3 


4 


5 


6 


7 


D 


E 


F 


10 


F5 


lo: 


0* 


1* 


2* 


3* 


Address 


3?A 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


- 


Palette 


3C0 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


Palette 


3C0 


01 


01 


01 


01 


01 


13 


1S 




08 


01 


01 


08 


01 


08 


01 


01 


01 


01 


01 


Palette 


SCO 


02 


02 


02 


02 


02 


15 


15 




08 


02 


02 


00 


00 


00 


02 


02 


02 


02 


02 


Palette 


SCO 


OS 


OS 


OS 


OS 


OS 


17 


17 




08 


OS 


OS 


00 


00 


00 


OS 


OS 


OS 


OS 


OS 


Palette 


SCO 


04 


04 


04 


04 


04 


02 


02 




08 


04 


04 


18 


04 


18 


04 


04 


04 


04 


04 


Palette 


SCO 


05 


05 


05 


05 


05 


04 


04 




08 


05 


05 


18 


07 


18 


05 


05 


05 


05 


05 


Palette 


SCO 


06 


06 


06 


06 


06 


06 


06 




08 


06 


06 


00 


00 


00 


06 


14 


14 


14 


14 


Palette 


SCO 


07 


07 


07 


07 


07 


07 


07 




08 


07 


07 


00 


00 


00 


07 


07 


07 


07 


07 


Palette 


SCO 


08 


10 


10 


10 


10 


10 


10 




10 


10 


10 


00 


00 


00 


S8 


S8 


S8 


S8 


S8 


Palette 


SCO 


09 


11 


11 


11 


11 


11 


11 




18 


11 


11 


08 


01 


08 


S9 


S9 


S9 


S9 


S9 


Palette 


SCO 


OA 


12 


12 


12 


12 


12 


12 




18 


12 


12 


00 


00 


00 


SA 


SA 


SA 


SA 


SA 


Palette 


SCO 


OB 


IS 


IS 


IS 


1S 


IS 


IS 




18 


1S 


IS 


00 


00 


00 


SB 


SB 


SB 


SB 


SB 


? = B in monochrome modes ? = D in color modes 


* Values for these modes when the IBM Enhanced Color Display is attached 


JValues for these modes when greater than 64 K Graphics Memory is installed 



Attribute Registers (1 of 2) 



August!, 1984 



IBM Enhanced Graphics Adapter 67 



Register 


Mode of Operation 


Name 


Port 


Index 





1 


2 


3 


4 


5 


6 


7 


D 


E 


F 


to 


FJ 


10$ 


0* 


1* 


2* 


3* 


Palette 


3C0 


OC 


14 


14 


14 


14 


14 


14 


17 


18 


14 


14 


00 


04 


00 


sc 


sc 


SC 


SC 


SC 


Palette 


SCO 


OD 


15 


15 


15 


15 


15 


15 


17 


18 


15 


15 


18 


07 


18 


SD 


SD 


SD 


SD 


SD 


Palette 


3C0 


OE 


16 


16 


16 


16 


16 


16 


17 


18 


16 


16 


00 


00 


00 


SE 


SE 


SE 


SE 


SE 


Palette 


3C0 


OF 


17 


17 


17 


17 


17 


17 


18 


17 


17 


00 


00 


00 


3F 


SF 


SF 


SF 


SF 


SF 


Mode Control 


SCO 


10 


08 


08 


08 


08 


01 


01 


01 


OE 


01 


01 


OB 


OB 


OB 


01 


08 


08 


08 


08 


Overscan 


SCO 


11 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


Color Plane 


SCO 


12 


OF 


OF 


OF 


OF 


OS 


OS 


01 


OF 


OF 


OF 


05 


05 


05 


OF 


OF 


OF 


OF 


OF 


Hrz Panning 


SCO 


IS 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


00 


* Values for these modes when the IBM Enhanced Color Display is attached 


^Values for these modes when greater than 64 K Graphics Memory is installed 



Attribute Registers (2 of 2) 



68 IBM Enhanced Graphics Adapter 



August 2, 1984 



RAM Loadable Character Generator 

The character generator on the adapter is RAM loadable and can 
support characters up to 32 scan lines high. Two character 
generators are stored within the BIOS and one is automatically 
loaded into the RAM by the BIOS when an alphanumeric mode is 
selected. The Character Map Select Register can be programmed 
to define the function of bit 3 of the attribute byte to be a 
character generator switch. This allows the user to select between 
any two character sets residing in bit plane 2. This effectively 
gives the user access to 512 characters instead of 256. character 
tables may be loaded off line.The adapter must have 128K bytes 
of storage to support this function. Up to four tables can be 
loaded can be loaded with 25 6K of graphics memory installed. 

The structure of the character tables is described in the following 
figure. The character generator is in bit plane 2 and must be 
protected using the map mask function. 



+0K 


















Bit Plane 2 






























































+8K 
















































+16K 


































































































+32 K 


































































































+48 K 


































































































_1_0>I IX 





Character 
Generator 



Character 
Generator 1 



Character 
Generator 2 



Character 
Generator 3 



The following figure illustrates the structure of each character 
pattern. If the CRT controller is programmed to generate n row 



August 2, 1984 



IBM Enhanced Graphics Adapter 69 



scans, then n bytes must be filled in for each character in the 
character generator. The example assumes eight row scans per 
character. 




CC = Value of the character code. For example, 41H in the case 
of an ASCII "A". 



Creating a 512 Character Set 

This section describes how to create a 512 character set on the 
IBM Color Display. Note that only 256 characters can be printed 
on the printer. This is a special appUcation which the Enhanced 
Graphics Adapter will support. The 9 by 14 characters will be 
displayed when attribute bit 3 is a logical 0, and the IBM 
Color/Graphics Monitor Adapter 8 by 8 characters will be 
displayed when the attribute bit 3 is a logical 1 . This example is 
for demonstrative purposes only. The assembly language routine 
for creating 512 characters is given below. Debug 2.0 was used 
for this example. The starting assembly address is 100 and the 
character string is stored in location 200. This function requires 
128K or more of graphics memory. 



70 IBM Enhanced Graphics Adapter 



August 2, 1984 



alOO 

movax,1102 
mov bl,02 
intlO 



;load 8x8 character font in character 
; generator number 2 



mov ax, 11 03 
mov bl,08 
intlO 

mov ax, 1000 
movbx,0712 
intlO 

mov ax, 1301 
mov bx,OOOF 
mov cx,003A 
mov dx, 1600 
mov bp,0200 
push cs 
popes 
int 10 



; select 512 character operation 
;if attribute bit 3 = 1 use 8x8 font 
;if attribute bit 3=0 use 9x14 font 

;set color plane enable to 7H to disable 
; attribute bit 3 in the color palette 
; lookup table 



; write char, string with attribute bit 3 = 1 
;cx = character string length 
;write character on line 22 of display 
; pointer to character string location 



mov ax ,1301 
mov bx,0007 
mov cx,003A 
movdx,1700 
mov bp,0200 
push cs 
popes 
int 10 
int 3 

a200 db 



; write char, string with attribute bit 3=0 
;cx = character string length 
; write character on line 23 of display 
;pointer to character string location 



"This character string is used to show 512 
characters" 



Creating an 80 by 43 Alphanumeric Mode 

The following examples show how to create 80 column by 43 
row, both alphanumeric and graphics, images on the IBM 
Monochrome Display. The BIOS Interface supports an 80 
column by n row display by using the character generator load 
routine call. The print screen routine must be revectored to 



August 2, 1984 



IBM Enhanced Graphics Adapter 71 



handle the additional character rows on the screen. The assembly 
language required for both an alphanumeric and a graphics screen 
is shown below. 



mov al,7 


;Monochrome alphanumeric mode 


intlO 


;video interrupt call 


mov ax,1112 


;character generator BIOS routine 


mov bl,0 


;load 8 by 8 double dot character font 


intlO 


;video interrupt call 


mov ax, 1200 


; alternate screen routine 


move bl,20 


; select alternate print screen routine 


intlO 


;video interrupt call 


int3 




mov ax,f 


;Monochrome graphic mode 


intlO 


;video interrupt call 


mov ax, 11 23 


;character generator BIOS routine 


mov bl,0 


;load 8 by 8 double dot character font 


mov dl,2B 


;43 character rows 


intlO 


;video interrupt call 


mov ax, 1200 


; alternate screen routine 


mov bl,20 


; alternate print screen routine 


int 10 


;video interrupt call 


int3 





Vertical Interrupt Feature 

The Enhanced Graphics Adapter can be programmed to create an 
interrupt each time the vertical display refresh time has ended. 
An interrupt handler routine must be written by the application to 
take advantage of this feature. The CRT Vertical interrupt is on 
IRQ2. The CPU can poll the Enhanced Graphics Adapter Input 
Status Register (bit 7) to determine whether the CRTC caused 
the interrupt to occur. 

The Vertical Retrace End Register (IIH) in the CRT controller 
contains two bits which are used to control the interrupt circuitry. 
The remaining bits must be output as per the value in the mode 
table. 



72 IBM Enhanced Graphics Adapter 



August 2, 1984 



Bit 5 Enable Vertical Interrupt — A logical will 

enable vertical interrupt. 

Bit 4 Clear Vertical Interrupt — A logical will clear a 

vertical interrupt. 

The sequence of events which occur in an interrupt handler are 
outlined below. 

1. Clear IRQ latch and enable driver 

2. Enable IRQ latch 

3. Wait for vertical interrupt 

4. Poll Interrupt Status Register to determine if CRTC has 
caused the interrupt 

5. If CRTC interrupt, then clear IRQ latch; if not, then branch 
to next interrupt handler. 

6. Enable IRQ latch 

7. Update Enhanced Graphics Adapter during vertical blanking 
interval 

8. Wait for next vertical interrupt 



Creating a Split Screen 

The Enhanced Graphics Adapter hardware supports an 
alphanumeric mode dual screen display. The top portion of the 
screen is designated as screen A, and the bottom portion of the 
screen is designated as screen B as per the following figure. 



Screen A 



Screen B 



Dual Screen Definition 



The following figure shows the screen mapping for a system 
containing a 32K byte alphanumeric storage buffer. Note that the 
Enhanced Graphics Adapter has a 32K byte storage buffer in 
alphanumeric mode. Information displayed on screen A is 



August 2, 1984 IBM Enhanced Graphics Adapter 73 



defined by the start address high and low registers (OCH and 
ODH) of the CRTC. Information displayed on screen B always 
begins at address OOOOH. 



OOOOH 



OFFFH 
1000H 

7FFFH 



Screen B 
Buffer Storage Area 



Screen A 
Buffer Storage Area 



Screen Mapping Within the Display Buffer Address Space 

The Line Compare Register (18H) of the CRT Controller is 
utilized to perform the split screen function. The CRTC has an 
internal horizontal scan counter, and logic which compares the 
horizontal scan counter value to the Line Compare Register value 
and clears the memory address generator when a compare occurs. 
The linear address generator then sequentially addresses the 
display buffer starting at location zero, and each subsequent row 
address is is determined by the 16 bit addition of the start of line 
latch and the offset register. 

Screen B can be smoothly scrolled onto the CRT screen by 
updating the Line compare in synchronization with the vertical 
retrace signal. The information on screen B is immune from 
scrolling operations which utilize the Start Address High and Low 
registers to scroll through the Screen A address map. 



Compatibility Issues 

The CRT Controller on the IBM Enhanced Graphics Adapter is a 
custom design, and is different than the 6845 controller used on 
the IBM Monochrome Monitor Adapter and the IBM 
Color/Graphics Monitor Adapter. It should be noted that several 
CRTC register addresses differ between the adapters. The 
following figure illustrates the registers which do not map directly 
across the two controllers. 



74 IBM Enhanced Graphics Adapter August 2, 1984 



Register 


6485 Function 


EGA CRTC Function 


02H 


Start Horiz. Retrace 


Start Horiz. Blanking 


03 H 


End Horiz. Retrace 


End Horiz. Blanking 


04 H 


Vertical Total 


Start Horiz. Retrace 


05 H 


Vertical Total Adjust 


End Horiz. Retrace 


06H 


Vertical Displayed 


Vertical Total 


07 H 


Vertical Sync Position 


Overflow 


08 H 


Interlace Mode and Skew 


Preset Row Scan 



Existing applications which utihze the BIOS interface will 
generally be compatible with the Enhanced Graphics Adapter. 

Horizontal screen centering was required on the IBM 
Color/Graphics Monitor Adapter in order to center the screen 
when generating composite video. This was done through the 
Horizontal Sync Position Register. Since the Enhanced Graphics 
Adapter does not support a composite video monitor, programs 
which do screen centering may cause loss of the screen image if 
centering is attempted. 

The Enhanced Graphics Adapter offers a wider variety of 
displayable monochrome character attributes than the IBM 
Monochrome Display Adapter. Some attribute values may 
display differently between the two Adapters. The values listed in 
the table below, in any combinations with the blink and intensity 
attributes, will display identically. 



Baclcground 
RGB 


Foreground 
RGB 


Function 






1 1 1 




1 

1 1 1 




Non-Display 

Underline 

White Character/Black Background 

Reverse Video 



Software which expUcitly addresses 3D8 (Mode Select Register) 
or 3D9 (Color Select Register) on the Color Graphics Monitor 
Adapter may produce different results on the Enhanced Graphics 
Adapter. For example, blinking which is disabled by writing to 
3D8 on the Color Graphics Adapter will not be disabled on the 
Enhanced Graphics Adapter. 



August 2, 1984 



IBM Enhanced Graphics Adapter 75 



Interface 



Feature Connector 

The following is a description of the Enhanced Graphics Adapter 
feature connector. Note that signals coming from the Enhanced 
Graphics Adapter are labeled "inputs" and the signals coming to 
the Enhanced Graphics Adapter through the feature connector 
are labeled "outputs". 

Signal Description 

J2 This pin is connected to auxiliary jack 2 on the rear 

panel of the adapter. 

R'OUT Secondary red output 

ATRS/L Attribute shift load. This signal controls the 

seriaUzation of the video information. The shift 
register parallel loads at the dot clock leading edge 
when this signal is low. 

G OUT Primary green output 

R' Secondary red input 

R Primary red input 

FCl This signal is input from bit 1 (Feature Control Bit 

1) of the Feature Control Register. 

FCO This signal is input from bit (Feature Control Bit 

0) of the Feature control Register. 

FEAT This signal is output to bit 5 (Feature Code 0) of 
Input Status Register 0. 

BVV Secondary blue input/Monochrome video 

VIN Vertical retrace input 



76 IBM Enhanced Graphics Adapter 



August!, 1984 



Internal This signal is output to bit 4 (Disable Internal Video 
Drivers) of the Miscellaneous Output Register. 



VOUT 


Vertical retrace output 


Jl 


This pin is connected to 
panel of the adapter. 


G'OUT 


Secondary green output 


B'OUT 


Secondary blue output 


BOUT 


Blue output 


G 


Green input 


B 


Blue input 


ROUT 


Red output 


BLANK 


This is a composite hori: 



signal from the CRTC. 

FEAT 1 This signal is output to bit 6 (Feature Code 1) of 
Input Status Register 0. 

GVI Secondary green/Intensity input 

HIN Horizontal retrace input from the CRTC 

14MHZ 14 MHz signal from the system board 

EXT OSC External dot clock output 

HOUT Horizontal retrace output 



August 2, 1984 



IBM Enhanced Graphics Adapter 77 



The following figure shows the layout and pin numbering of the 
feature connector. 



Signal Name 



Gnd 

+12V 

J2 

R'OUT 

ATRS/L 

GOUT 

R' 

R 

FEAT1 

FEATO 

FCO 

BVV 

VI N 

Internal 

VOUT 

GND 



31 



32 



's: 



Signal Name 

-12V 



J1 

G'OUT 

B'OUT 

BOUT 

G 

B 

ROUT 

BLANK 

FC1 

G7I 

HIN 

14MHz 

EXT OSC 

HOUT 

+5V 



Feature Connector Diagram 



78 IBM Enhanced Graphics Adapter 



August 2, 1984 



Specifications 



System Board Switches 

The following figure shows the proper system board DIP switch 
settings for the IBM Enhanced Graphics Adapter when used with 
the Personal Computer and the Personal Computer XT. The 
switch block locations are illustrated in the Technical Reference 
Manual "System Board Component Diagram". The Personal 
Computer has two DIP switch blocks; the switch settings shown 
pertain to DIP Switch Block 1. The Personal Computer XT has 
one DIP switch block. 




N 


1 


2 


3 


4 


5 
■ 


6 
■ 


7 


8 





Switch Block (1) 

Note: The DIP switches must be set as shown whenever the 
IBM Enhanced Graphics Adapter is installed, regardless of 
display type. This is true even when a second display adapter 
is installed in the system. 



August!, 1984 



IBM Enhanced Graphics Adapter 79 



Configuration Switches 

The following diagram shows the location and orientation of the 
configuration switches on the Enhanced Graphics Adapter. 



Option 
Retaining ^ 
Bracket 




Optional 

Graphics Memory 
Expansion Card 



Off On 



80 IBM Enhanced Graphics Adapter 



August 2, 1984 



Configuration Switch Settings 

The configuration switches on the Enhanced Graphics Adapter 
determine the type of display support the adapter provides, as 
follows: 



Switch Settings for Entianced Graphics Adapter 
as Primary Display Adapter 


SW1 


SW2 


SW3 


SW4 


Configuration 


Enhanced 
Adapter 


iMonochrome 
Adapter 


Coior/Graphics 
Adapter 


On 


Off 


Off 


On 


Color Display 
40x25 


Secondary 


- 


Off 


Off 


Off 


On 


Color Display 
80x25 


Secondary 


- 


On 


On 


On 


Off 


Enhanced Display 
Emulation Mode 


Secondary 


- 


Off 


On 


On 


Off 


Enhanced Display 
Hi Res Mode 


Secondary 


- 


On 


Off 


On 


Off 


Monochrome 


- 


Secondary 
40x25 


Off 


Off 


On 


Off 


Monochrome 


- 


Secondary 
80x25 



August 2, 1984 



IBM Enhanced Graphics Adapter 81 



Switch Settings for Enlianced Grapliics Adapter 
as Secondary Display Adapter 


SW1 


SW2 


SW3 


SW4 


Configuration 


Enlianced 
Adapter 


Monochrome 
Adapter 


Color/Graphics 
Adapter 


On 


On 


On 


On 


Color Display 
40x25 


Primary 


- 


Off 


On 


On 


On 


Color Display 
80x25 


Primary 


- 


On 


Off 


On 


On 


Enfianced Display 
Emulation Mode 


Primary 


- 


Off 


Off 


On 


On 


Enhanced Display 
Hi Res Mode 


Primary 


- 


On 


On 


Off 


On 


Monochrome 


- 


Primary 
40x25 


Off 


On 


Off 


On 


Monochrome 


- 


Primary 
80x25 



82 IBM Enhanced Graphics Adapter 



Aagfist 2, 1984 



Direct Drive Connector 




9- Pin Direct 
Drive Signal 



Signal Name - Description 



Pin 



Direct 

Drive 

Display 



Ground 



Secondary Red 



Primary Red 



Primary Green 



Primary Blue 



Secondary Green/Intensity 



Secondary Blue/Mono Video 



Horizontal Retrace 



Vertical Retrace 



Enhanced 
Graphics Adapter 



August 2, 1984 



IBM Enhanced Graphics Adapter 83 



Light Pen Interface 



P-2 Connector 




P-2 Connector 



Pin 



Light Pen 
Attachment 



+Light Pen Input 



Not used 



+Light Pen Switch 



Ground 



+5 Volts 



1 2 Volts 



Enhanced 
Graphics Adapter 



84 IBM Enhanced Graphics Adapter 



August 2, 1984 



Jumper Descriptions 

Located on the adapter are two jumpers designated PI and P3. 
Jumper PI changes the function of pin 2 on the direct drive 
interface. When placed on pins 2 and 3, jumper PI selects ground 
as the function of direct drive interface, pin 2. This selection is 
for displays that support five color outputs, such as the IBM 
Color Display. When PI is placed on pins 1 and 2, red prime 
output is placed on pin 2 of the direct drive interface connector. 
This supports the IBM Enhanced Color Display, which utilizes six 
color outputs on the direct drive interface. 

Jumper P3 changes the I/O address port of the Enhanced 
Graphics Adapter within the system. In its normal position, (pins 
1 and 2), all Enhanced Graphics Adapter addresses are in the 
range 3XX. Moving jumper P3 to pins 2 and 3 changes the 
addresses to 2XX. Operation of the adapter in the 2XX mode is 
not supported in BIOS. 

The following figure shows the location of the jumpers and 
numbering of the connectors. 




Ai^ustl, 1984 



IBM Enhanced Graphics Adapter 85 



86 IBM Enhanced Graphics Adapter August 2, 1984 







o 

a* 

I 
I 



00 
-4 



lOuF 



XI- 



r-^ OE 




m 

2 


o 


> 


QTQ 




^rt« 


o 


c 


m 




o 


d 


3D 


N^« 


J> 


&s 




(JO 


n 


•^ 


CO 


&5 


> 

no 


B 


-1 




m 

3D 





LSOH 

-!l|^>o!i. 



BOO SHT2.3,6,'AS.9 



B07 SHT 23/^18.9 



- Ii* MHZ SHT l(W 



Enhanced Graphics Adapter Sheet 1 of 11 



00 



SHT I mnHZ 



o 




et 




a^ 


SHT 10 EXTOSC 


O 




7< 


SHT 9 CLKSELO 


^ 




■a 


SHT 9 CLKSELI 


s 


SHTH HoioiT 


s 


SHTH AO 


SHT 6 MID? 


SHTH VMEMR 


>- 


SHTH VMEMW 


8- 




*a 




(-K 




«> 


t nnt 



p^" 



SEQUENCER LSI 



? 



K> 



33ACASI 

J?T- 



— I .^SOH ^ SOH 

l/UIH U^IH 



^SI25 



SHT 6,7,11 

t 

SHT 6,7,11 



- ACASI 

- ACAS2 

- ACAS3 



DOT cm 


SHT 6,7.8,10 


-CCLK SHT 3,5 
CRT LATCH SHT S,6,7,8 


CPU LATCH SHT 6,7 
S/L SHT 6,7 


WE 


SHT 6,7.11 


WE 


SHT 6,7 


CRT/CPiJ 


SHT 3,H,S 


MUX 


SHT 3,5 


MUX 


SHT 3,S 



ATRS/L 


SHT 8 


10 


BCASO 


SHT 7 




BCAST 


SHT 11 




BC«2 
BCAS3 


SHT 1! 
SHT 11 








a 

30 

> 



> 

> 



00 



Enhanced Graphics Adapter Sheet 2 of 11 



K> 



00 



s 






t 



ft 



00 
V6 



SHT 2 MUX 



SHT2 
SHT 2 
SHT6 
SHTS 
SHT I 
SHTM 
SHTH 
SHT^ 



SHT 9 LPSTB 




AA3 

AA^ 

AAS 
AA6 
AA7 



CRTINT SHT I ,9 
REFAGR SHTS 
SYNC SHT 2 

HSYNC SHT 9 
VSYNC SHT 8,9,10 
BLANK SHT 8,10) 
DE SHTS 

OJRSOR/UL SHT 8 
BAO SHTH,S,7,II 



BAS 

BA6 T 

BA7 SHT 4, "5,7,1 



RS2 

RS^ t 

RSH SHTS 



o 
m 

o 
o 

> 






> 
3 



Enhanced Graphics Adapter Sheet 3 of 11 



o 






O 
f^ 

Oi 



SO 

I 



t 






SHT2 MUX AM 






00 




SHTII MEMOPT 

SHT 2 CRT/CFD 

SHT9 RAH ENABLE 

SHT 7 COSELI 

SHT 7 C05EL0 



> 

2 
m 

D 

o 

> 



O 
C/3 



Enhanced Graphics Adapter Sheet 4 of 11 



t 



f^ 



K> 


SHT3 
SHT6 
SHT6 
SHT6 




RSH - 




MODI- 
M0D2- 












SHT2 


CRT 


LATCH - 





SHT6 




SHT6 


5 


SHT6 
SHT6 


2 


SHT6 


B 





1 


SHT6 


GRAPHICS 






o 


SHT2 


CRT/CPU 


SHT2 


MUX 


»^ 






S9 






T3 








SHT2 


MUX 


00 







SHT3 REF ADR 
SHT2 -CCLK 




o 

> 

z 
o 

CO 

> 
> 

m 

3D 



GRAPHICS SHT8 



SREFADR SHT3 



Enhanced Graphics Adapter Sheet 5 of 11 



\o 








K» 






NN 






d0 


SHT 1 


BDO 


2 






BDI 
BD2 


w 






BD3 
BD^ 


5* 






BOS 
BD6 


5 






•5 






fD 


SHT2 


CPU LATCH - 


Oi 




CRTUTCH - 


1 




SHT 2 


WE 








VMEMR(2) - 
AO 



t 



fD 



SHT 3 
SHT 2 



AAS 
AAb 
AA7 
RASP 

RasT 




z 
> 

O 

m 

a 
a 

> 



o 

CO 

> 
> 



Enhanced Graphics Adapter Sheet 6 of 11 



SHT 

f 


2 

! 

2 

} 


CPU LATCH - 
CRT LATCH - 
DOTCLK - 
S/L 
WE 




SHT 


SHT 




VMEMR 

AO 

A2 


( 


SHT 






ft 

a 

I 







C2 


SHT 8 




m 


C3 


SHT 8 


2 


CDSELO 


SHT^ 
SHTH 

SHT 5,8 


> 


M2D0 


M2DI 








o 


M2D2 








m 


M2D3 








o 


M2Dt 
M2DS 








o 


M2D6 








3D 


M2D7 


SHT S,8 


> 

-o 

X 

> 










> 



Enhanced Graphics Adapter Sheet 7 of 1 1 



so 




^ 




s 




s 


SHT6 






W 


SHT6 
SHT6 


^ 


SHT7 
SHT6 


g 


SHT7 
SHT6 


^ 




o 




Ok 


SHT>; 






M2D0 
M2DI 
M2D2 
M2D3 
M2DH • 
M2DS • 
M2Db ■ 
M2D7 ■ 



SHT2 CRT LATCH - 

SHT2 ATRS/L - 

SHT2 DOTCLK 

SHT3 BLANK 

SHT3 VSYNC 

SHT3 DE 

SHT 3 CURSOR/UL - 



ATTRIBUTE LSI 



ATR^ 
ATR5 
ATR6 
ATR7 



ATRI/CI 
ATR2/C2 
ATR3/C3 



Gi 

> 



> 



m 

3D 



K) 



00 



Enhanced Graphics Adapter Sheet 8 of 11 



^ 


SHT 10 


ROUT 
R'OUT 
B-OUT 
G'OUT 
BOUT 


i 


SHT 10 


G OUT 

VOUT 
HOUT 


b^ 


SHT 9 
SHT 5 


HPOL 
HSYNC 


^^ 






so 

00 


SHT 9 
SHT 3 


VPOL 
VSYNC 






^E>^ 



i^E>- 




pi[5T7| 



rt 






<t 






a. 






O 












(d 








SHT ID 


FEAT 


E 


SHT 10 


FEAT 1 


SHT 3 


CRTINT 


ft 


SHT H 


STATUS 


«) 


SHT 4 


LPSET 


>> 






t 






^ 






2 








SHT H 


LPCLR 




SHT H 


ATRIOR 


VO 






Ul 







o 
m 

o 
a 

> 



CO 






SHT 10 
SHT 10 



- MONO MONITOR SHT 
■ RAM ENABLE SHT 

- CLK SEL SHT 2 

- CLK SEL I SHT 2 

• INTERN AL SHT 10 

- PGSEL SHT 4 
H POL SHT 9 

• V POL SHT 9 









> lo+S RPI 

6 PIN SIP 




LSI-J? 






SWI 


8 3 H] ? 6 


10 


2C0 

2C1 2Y 

2C3 "'^ 








1 2 


7 1 




9 2 


U3'j 

2Y 
2A 3Y 
3A 4Y 

^A 

Gl SY 
5A 6Y 

G2 




t 3 


6 * . 


12 






{ •* 


■5 


1^ 


3 BDH 


i 














■* 




b 




10 












12 


13 BDI 










m 






X6 BERC 




LSOH 




M 


74LS7H 


r-^ 






6 

2 


o|2V 

-LPEN Sw'^'^ 


^ 2 


%,8 ° 


s 














r^8 








L<^ 




















-LPEN IN 







































LPEN STB SHT 3 



Enhanced Graphics Adapter Sheet 9 of 11 



OS 



a. 



I 






SHT 9 
SHT q 
SHT 8 



G - 

B - 

R' - 

G'/I - 

B'/V - 

mMHZ - 



ATRS/L - 

■t-SV ■ 

INTERNAL - 

+I2V ■ 



GND - 
GND 



fi 









z 






> 






2 






O 






m 


FEAT 


SHT 9 a 


FEAT 1 


SHT 9 _ 
SHT 2 ^ 


EXT OSC 


ROUT 


SHT 9 30 


GOUT 






> 


BOUT 






^ 


R'OUT 






X 


G'OUT 








B'OUT 
HOUT 






o 

CO 


VOUT 


SHT 9 > 






a 






> 






■o 






H 








m 



^^ 



FEATURE CONNECTOR 



NOTE: 

I GROUNDS- ONE AT EACH END OF CONNECTOR. 



Enhanced Graphics Adapter Sheet 10 of 11 



2X32 CONNECTOR 



SHT 6 MODO ■ 



CD 

m 
o 

> 



CO 

> 
o 
> 

-q 



d0 

I 

I 



SHT 7 M3D7 



SHT 3 
SHT 2 



- MEMOPT SHT H 



t 






MEMORY EXPANSION 
2X32 



Enhanced Graphics Adapter Sheet 11 of 11 









I 

I 

I? 



SHT H MODO- 

MODl- 

M0D2- 

M0D3- 

MODt- 

MODS- 

I M0D6- 

SHTH M0D7- 

SHT 5 MIDO- 

MIDI- 

MID2- 

MID3- 

MIDH- 

MID5- 

1 MID6- 

SHT •> MID7- 

SHT 6 M2D0- 

M2DI- 

M2D2- 

M2D^- 

M2DH- 

M2D5- 

I M2Db- 

SHT 6 M2D7- 

SHT 7 H3D0- 

M3DI- 

M3D2— 

M3D3- 

M3DH- 

M3D6- 
SHT 7 M3D7- 



1.1 CI71+ ciTu C19I+ 



CI7 
lOuF 



-T • • • T lOwFT lOuFT lOuFT 



CI8i 
lOuFl 



lOuFT 



CI-CI6 
.0H7uF 



_JS 



PI 

2X32 



'^ 



F 



U9 
7HLS0H 



-AA2 
-AA3 
-AAH 
-AA5 



-BAI 

-BA2 

-BA? 

-BAH 

-BA5 

-BA6 

-BA7 

-A CAS 

-A CAS 2 SHT 

-A CAS 3 SHT 

- B CAS I SHT 
-BCAS2 SHT 
-BCAS3 SHT 

- RAS SHT 



r H,*? 
r 6.7 



6.7 

H.S 

«♦,•; 
6,7 
6,7 
6.7 



-RAS I 
-RAS 2 
-RAS 3 



SHT 
SHT 
SHT 



-WEO SHT " 

-WEI SHT • 

-WE? SHT ( 

-WEl SHT 



> 
2 
O 

m 

a 



CO 

> 
> 



Graphics Memory Expansion Card Sheet 1 of 5 




m 

o 
a 

> 



o 

> 
> 



MODO SHT3 

MODI 

M0D2 

M0D3 

M0D4 

MODS 

M0D6 

M0D7 SHT3 



?5 



SO 



Graphics Memory Expansion Card Sheet 2 of 5 



1 






SHT 


3 ACASI 


SHT 


? ACAS2 


SHT 


3 ACAS3 




SHT 


3 RAS 1 


1 


SHT 
SHT 


3 WE 1 
3 AO 

Al 

A2 


g 




A3 
AS 


rt 




A6 


f^ 


SHT 


3 A7 


c^ 







© 






5 




> 

o 






> 
> 



Graphics Memory Expansion Card Sheet 3 of 5 




m 



o 

3D 
> 



O 

> 
> 



o 



Graphics Memory Expansion Card Sheet 4 of 5 



» 




> 

2 
O 



30 

> 



o 

CO 

> 

> 



Graphics Memory Expansion Card Sheet 5 of 5 



BIOS Listing 

Vectors with Special Meanings 

Interrupt Hex 42 - Reserved 

When an IBM Enhanced Graphics Adapter is installed, the BIOS 
routines use interrupt 42 to revector the video pointer. 



Interrupt Hex 43 - IBM Enhanced Graphics Video 
Parameters 

When an IBM Enhanced Graphics Adapter is installed, the BIOS 
routines use this vector to point to a data region containing the 
parameters required for the initializing of the IBM Enhanced 
Graphics Adapter. Note that the format of the table must adhere 
to the BIOS conventions established in the listing. The power-on 
routines initialize this vector to point to the parameters contained 
in the IBM Enhanced Graphics Adapter ROM. 



Interrupt Hex 44 - Graphics Character Table 

When an IBM Enhanced Graphics Adapter is installed the BIOS 
routines use this vector to point to a table of dot patterns that will 
be used when graphics characters are to be displayed. This table 
will be used for the first 128 code points in video modes 4, 5, and 
6. This table will be used for 256 characters in all additional 
graphics modes. See the appropriate BIOS interface for 
additional information on setting and using the graphics character 
table pointer. 



August 2, 1984 IBM Enhanced Graphics Adapter 103 



PAGE, 120 

TITLE ENHANCED GRAPHICS ADAPTER BIOS 

EXTRN CGMN:NEAR, CGDDOT:NEAR, I NT_1 F_1 : NEAR, CGMN_FDG: NEAR 

EXTRN ENO_ADDRESS:NEAR 



THE BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH 
SOFTWARE INTERRUPTS ONLY, ANY ADDRESSES PRESENT IN 
THE LISTINGS ARE INCLUDED ONLY FOR COMPLETENESS, 
NOT FOR REFERENCE. APPLICATIONS WHICH REFERENCE 
ABSOLUTE ADDRESSES WITHIN THE CODE SEGMENT 
VIOLATE THE STRUCTURE AND DESIGN OF BIOS. 



124 
125 
126 



INCLUDE VFRONT. INC 

SUBTTL VFRONT. INC 

PAGE 

■-- INT 10 - — ■ 

VIDE0_I0 

THESE ROUTINES PROVIDE THE CRT INTERFACE 
THE FOLLOWING FUNCTIONS ARE PROVIDED: 
(AH)=0 SET MODE (AL) CONTAINS MODE VALUE 



AL AD 


TYPE 


RES 


NOTES 


DF-DIM 


DISPLAY 


MAX PCS 


B8 


ALPHA 


6U0X200 






40X25 


COLOR - BW 


8 


1 B8 


ALPHA 


6«tOX200 






40X25 


COLOR 


8 


2 88 


ALPHA 


6U0X200 






80X25 


COLOR - BW 


8 


3 88 


ALPHA 


6U0X200 






80X25 


COLOR 


8 


U 88 


GRPHX 


320X200 






40X25 


COLOR 


1 


5 B8 


GRPHX 


320X200 






40X25 


COLOR - BW 


1 


6 B8 


GRPHX 


640X200 






80X25 


COLOR - BW 




7 BO 


ALPHA 


720X350 






80X25 


MONOCHROME 


8 


8 


RESERVED 












9 


RESERVED 












A 


RESERVED 












B 


RESERVED - INTERNAL 


USE 








C 


RESERVED - INTERNAL 


USE 









D AC GRPHX 320X200 

E AO GRPHX 640X200 

F AO GRPHX 640X350 

10 AO GRPHX 640X350 



40X25 COLOR 

80X25 COLOR 

80X25 MONOCHROME 

80X25 HI RES 



*** NOTE BW MODES OPERATE SAME AS COLOR MODES, BUT 
COLOR BURST IS NOT ENABLED 
(AH)=1 SET CURSOR TYPE 

(CH) = BITS 4-0 = START LINE FOR CURSOR 

** HARDWARE WILL ALWAYS CAUSE BLINK 
*» SETTING BIT 5 OR 6 WILL CAUSE ERRATIC 
BLINKING OR NO CURSOR AT ALL 
(CL) = BITS 4-0 = END LINE FOR CURSOR 
(AH)=2 SET CURSOR POSITION 

(DH,DL) = ROW, COLUMN (0,0) IS UPPER LEFT 
(BH) = PAGE NUMBER 
(AH)=3 READ CURSOR POSITION 
(BH) = PAGE NUMBER 

ON EXIT (DH,DL) = ROW, COLUMN OF CURRENT CURSOR 
(CH,CL) = CURSOR MODE CURRENTLY SET 
(AH)=4 READ LIGHT PEN POSITION 
ON EXIT: 

(AH) = -- LIGHT PEN SWITCH NOT DOWN/NOT TRIGGERED 
(AH) = 1 — VALID LIGHT PEN VALUE IN REGISTERS 

(DH,DL) = ROW, COLUMN OF CHARACTER LP POSN 
(CH) = RASTER LINE (0-199) 

(CX) = RASTER LINE (O-NNN) NEW GRAPHICS MODES 
(BX) = PIXEL COLUMN (0-319,639) 
(AH)=5 SELECT ACTIVE DISPLAY PAGE 

(AL) = NEW PAGE VALUE, SEE AH=0 FOR PAGE INFO 
(AH)=6 SCROLL ACTIVE PAGE UP 

(AL) = NUMBER OF LINES, INPUT LINES BLANKED AT BOTTOM 
OF WINDOW 
AL = MEANS BLANK ENTIRE WINDOW 
(CH,CL) = ROW, COLUMN OF UPPER LEFT CORNER OF SCROLL 
(DH,DL) = ROW,COLUMN OF LOWER RIGHT CORNER OF SCROLL 
(BH) = ATTRIBUTE TO BE USED ON BLANK LINE 
(AH)=7 SCROLL ACTIVE PAGE DOWN 

(AL) = NUMBER OF LINES, INPUT LINES BLANKED AT TOP 
OF WINDOW 
AL = MEANS BLANK ENTIRE WINDOW 
(CH,CL) = ROW, COLUMN OF UPPER LEFT CORNER OF SCROLL 
(DH,DL) = ROW, COLUMN OF LOWER RIGHT CORNER OF SCROLL 
(BH) = ATTRIBUTE TO BE USED ON BLANK LINE 

CHARACTER HANDLING ROUTINES 

(AH) = 8 READ ATTRIBUTE/CHARACTER AT CURRENT CURSOR POSITION 

(BH) = DISPLAY PAGE 

ON EXIT: 

(AL) = CHAR READ 

(AH) = ATTRIBUTE OF CHARACTER READ (ALPHA MODES ONLY) 
(AH) = 9 WRITE ATTRIBUTE/CHARACTER AT CURRENT CURSOR POSITION 

(BH) = DISPLAY PAGE 

(CX) = COUNT OF CHARACTERS TO WRITE 

(AL) = CHAR TO WRITE 

(BL) = ATTRIBUTE OF CHARACTER (ALPHA) /COLOR OF CHAR 
(GRAPHICS) 
SEE NOTE ON WRITE DOT FOR BIT 7 OF BL = 1 . 
(AH) = A WRITE CHARACTER ONLY AT CURRENT CURSOR POSITION 

(BH) = DISPLAY PAGE 

(CX) = COUNT OF CHARACTERS TO WRITE 

(AL) = CHAR TO WRITE 
FOR READ/WRITE CHARACTER INTERFACE WHILE IN GRAPHICS MODE, THE 

CHARACTERS ARE FORMED FROM A CHARACTER GENERATOR IMAGE 

MAINTAINED IN THE SYSTEM ROM. ONLY THE 1ST 128 CHARS 

ARE CONTAINED THERE. TO READ/WRITE THE SECOND 128 

CHARS, THE USER MUST INITIALIZE THE POINTER AT 

INTERRUPT 1FH (LOCATION 0007CH) TO POINT TO THE IK BYTE 

TABLE CONTAINING THE CODE POINTS FOR THE SECOND 

128 CHARS (128-255). 



FOR WRITE CHARACTER INTERFACE IN GRAPHICS MODE, THE REPLICATION 
FACTOR CONTAINED IN (CX) ON ENTRY WILL PRODUCE VALID 
RESULTS ONLY FOR CHARACTERS CONTAINED ON THE SAME ROW. 
CONTINUATION TO SUCCEEDING LINES WILL NOT PRODUCE 
CORRECTLY. 



104 IBM Enhanced Graphics Adapter 



August 2, 1984 



127 
128 
129 
130 
131 
132 
133 
134 



164 
165 
166 



GRAPHICS INTERFACE 

(AH) = B SET COLOR PALETTE 

FOR USE IN COMPATIBILITY MODES 

(BH) = PALETTE COLOR ID BEING SET (0-127) 

(BL) = COLOR VALUE TO BE USED WITH THAT COLOR ID 

NOTE: FOR THE CURRENT COLOR CARD, THIS ENTRY POINT 
HAS MEANING ONLY FOR 320X200 GRAPHICS. 
COLOR ID = SELECTS THE BACKGROUND COLOR (0-15): 
COLOR ID = 1 SELECTS THE PALETTE TO BE USED: 

= GREEN(1 )/RED(2)/BROWN(3) 

1 = CYAN(1)/MAGENTA(2)/WHITE(3) 

IN 40X25 OR 80X25 ALPHA MODES, THE VALUE SET 
FOR PALETTE COLOR INDICATES THE 
BORDER COLOR TO BE USED (VALUES 0-31. 
WHERE 16-31 SELECT THE HIGH INTENSITY 
BACKGROUND SET). 
(AH) = C WRITE DOT 
(BH) = PAGE 
(DX) = ROW NUMBER 
(CX) = COLUMN NUMBER 
(AL) = COLOR VALUE 

IF BIT 7 OF AL = 1, THEN THE COLOR VALUE IS 
EXCLUSIVE OR'D WITH THE CURRENT CONTENTS OF 
THE DOT 
(AH) = D READ DOT 
(BH) = PAGE 
(DX) = ROW NUMBER 
(CX) = COLUMN NUMBER 
(AL) RETURNS THE DOT READ 

ASCII TELETYPE ROUTINE FOR OUTPUT 

(AH) = E WRITE TELETYPE TO ACTIVE PAGE 
(AL) = CHAR TO WRITE 

(BL) = FOREGROUND COLOR IN GRAPHICS MODE 
NOTE -- SCREEN WIDTH IS CONTROLLED BY PREVIOUS MODE SET ; 

(AH) = F CURRENT VIDEO STATE 

RETURNS THE CURRENT VIDEO STATE 

(AL) = MODE CURRENTLY SET (SEE AH=0 FOR EXPLANATION) 

(AH) = NUMBER OF CHARACTER COLUMNS ON SCREEN 

(BH) = CURRENT ACTIVE DISPLAY PAGE 

(AH) = 10 SET PALETTE REGISTERS 

(AL) = SET INDIVIDUAL PALETTE REGISTER 
BL = PALETTE REGISTER TO BE SET 
BH = VALUE TO SET 



194 
195 
196 
197 
198 
199 
200 
201 
202 
203 
204 
205 
206 
207 
208 
209 
210 
211 
212 
213 
214 
215 
216 
217 
218 
219 
220 
221 
222 
223 
224 
225 
226 
227 
228 
229 
230 
231 
232 
233 
234 
235 
236 
237 
238 
239 
240 
241 
242 
243 
244 
245 
246 
247 
248 
249 
250 
251 
252 



AL = 2 SET ALL PALETTE REGISTERS AND OVERSCAN 
ES:DX POINTS TO A 17 BYTE TABLE 

BYTES 0-15 ARE THE PALETTE VALUES, RESPECTIVELY 
BYTE 16 IS THE OVERSCAN VALUE 

AL = 3 TOGGLE INTENSIFY/BLINKING BIT 

BL - ENABLE INTENSIFY 
BL - 1 ENABLE BLINKING 

(AH) = 11 CHARACTER GENERATOR ROUTINE 

NDTE : THIS CALL WILL INITIATE A MODE SET, COMPLETELY 

RESETTING THE VIDEO ENVIRONMENT BUT MAINTAINING ; 
THE REGEN BUFFER. 

AL = 00 USER ALPHA LOAD 

ES:BP - POINTER TO USER TABLE 
CX - COUNT TO STORE 
DX - CHARACTER OFFSET INTO TABLE 
BL - BLOCK TO LOAD 

BH - NUMBER OF BYTES PER CHARACTER 
AL = 01 ROM MONOCHROME SET 

BL - BLOCK TO LOAD 
AL = 02 ROM 8X8 DOUBLE DOT 

BL - BLOCK TO LOAD 
AL = 03 SET BLOCK SPECIFIER 

BL - CHAR GEN BLOCK SPECIFIER 

D3-D2 ATTR BIT 3 ONE, CHAR GEN 0-3 
D1-D0 ATTR BIT 3 ZERO, CHAR GEN 0-3 
NOTE : WHEN USING AL = 03 A FUNCTION CALL 
AX = 1000H 
BX = 0712H 

IS RECOMMENDED TO SET THE COLOR PLANES 
RESULTING IN 512 CHARACTERS AND EIGHT 
CONSISTENT COLORS. 

NOTE : THE FOLLOWING INTERFACE (AL=1X) IS SIMILAR IN FUNCTION 
TO (AL=OX) EXCEPT THAT : 

- PAGE ZERO MUST BE ACTIVE 

- POINTS (BYTES/CHAR) WILL BE RECALCULATED 

- ROWS WILL BE CALCULATED FROM THE FOLLOWING: 

INT[(200 OR 350) / POINTS] - 1 

- CRT_LEN WILL BE CALCULATED FROM : 

( ROWS + 1 ) * CRT_COLS • 2 

- THE CRTC WILL BE REPROGRAMMED AS FOLLOWS : 

R09H = POINTS - 1 MAX SCAN LINE 

R09H DONE ONLY IN MODE 7 

ROAH = POINTS - 2 CURSOR START 
ROBH = CURSOR END 

R12H = VERT DISP END 

[(ROWS + 1) * POINTS] - 1 
R14H = POINTS UNDERLINE LOG 

THE ABOVE REGISTER CALCULATIONS MUST BE CLOSE TO THE 
ORIGINAL TABLE VALUES OR UNDETERMINED RESULTS WILL 
OCCUR. 

NOTE : THE FOLLOWING INTERFACE IS DESIGNED TO BE 

CALLED ONLY IMMEDIATELY AFTER A MODE SET HAS 
BEEN ISSUED. FAILURE TO ADHERE TO THIS PRACTICE ; 
MAY CAUSE UNDETERMINED RESULTS. 

AL = 10 USER ALPHA LOAD 

ES:BP - POINTER TO USER TABLE 

CX - COUNT TO STORE 

DX - CHARACTER OFFSET INTO TABLE 

BL - BLOCK TO LOAD 

BH - NUMBER OF BYTES PER CHARACTER 
AL = 11 ROM MONOCHROME SET 

BL - BLOCK TO LOAD 
AL = 12 ROM 8X8 DOUBLE DOT 

BL - BLOCK TO LOAD 



August 2, 1984 



IBM Enhanced Graphics Adapter 105 



253 
25t» 
255 
256 
257 
258 
259 
260 
261 
262 
263 
264 
265 
266 
267 
268 
269 
270 
271 
272 
273 
27U 
275 
276 
277 
278 
279 
280 
281 
282 
283 
284 
285 
286 
287 
288 
289 
290 
291 
292 
293 
294 
295 
296 
297 
298 
299 
300 
301 
302 
303 
304 
305 
306 
307 
308 
309 
310 



NOTE : THE FOLLOWING INTERFACE IS DESIGNED TO BE 

CALLED ONLY IMMEDIATELY AFTER A MODE SET HAS 
BEEN ISSUED. FAILURE TO ADHERE TO THIS PRACTICE 
MAY CAUSE UNDETERMINED RESULTS. 

AL = 20 USER GRAPHICS CHARS INT 01 FH (8X8) 

ES:BP - POINTER TO USER TABLE 
AL = 21 USER GRAPHICS CHARS 

ES:BP - POINTER TO USER TABLE 

CX - POINTS (BYTES PER CHARACTER) 

BL - ROW SPECIFIER 

BL = USER 

DL - ROWS 
BL = 1 14 (OEH) 
BL = 2 25 (19H) 
BL = 3 43 (2BH) 

AL = 22 ROM 8 X 14 SET 

BL - ROW SPECIFIER 
AL = 23 ROM 8X8 DOUBLE DOT 

BL - ROW SPECIFIER 



CX - POINTS 

DL - ROWS 
BH - RETURN CURRENT INT 1 FH PTR 

ES:BP - PTR TO TABLE 
BH - 1 RETURN CURRENT INT 44H PTR 

ES:BP - PTR TO TABLE 
BH - 2 RETURN ROM 8 X 14 PTR 

ES:BP - PTR TO TABLE 
BH - 3 RETURN ROM DOUBLE DOT PTR 

ES:BP - PTR TO TABLE 
BH - 4 RETURN ROM DOUBLE DOT PTR (TOP) 

ES:BP - PTR TO TABLE 
BH - 5 RETURN ROM ALPHA ALTERNATE 9X14 

ES:BP - PTR TO TABLE 

■■ 12 ALTERNATE SELECT 

BL = 10 RETURN EGA INFORMATION 

BH = - COLOR MODE IN EFFECT <3><D><X> 
1 - MONOC MODE IN EFFECT <3><B><X> 
BL = MEMORY VALUE 

- 064K 1 - 128K 

1 - 192K 1 1 - 256K 
CH = FEATURE BITS 

CL = SWITCH SETTING 

BL = 20 SELECT ALTERNATE PRINT SCREEN ROUTINE 

13 WRITE STRING 

ES:BP - POINTER TO STRING TO BE WRITTEN 

CX - CHARACTER ONLY COUNT 

DX - POSITION TO BEGIN STRING, IN CURSOR 

TERMS 
BH - PAGE NUMBER 



318 
319 
320 



BL - ATTRIBUTE 

STRING - (CHAR, CHAR, CHAR, 

CURSOR NOT MOVED 

BL - ATTRIBUTE 

STRING - (CHAR, CHAR, CHAR, 

CURSOR IS MOVED 



324 
325 
326 
327 
328 
329 
330 



CHAR RET, LINE FEED, BACKSPACE, AND BELL ARE 
TREATED AS COMMANDS RATHER THAN PRINTABLE 
CHARACTERS. 



0000 
0014 
0014 
0040 
0040 
007C 
007C 



0410 
0410 
0410 



0449 
0449 
044A 
044C 
044E 
0450 



335 
336 
337 
338 
339 
340 
341 
342 
343 
344 
345 
346 
347 
348 
349 
350 



354 
355 
356 
357 
358 
359 
360 
361 
362 
363 
364 
365 
366 
367 
368 
369 
370 
371 
372 
373 
374 
375 
376 
377 
378 



SRLOAD MACRO 


SEGREG 


VALUE 


IFNB <VALUE> 




IFIDN 


<VALUE>,<0> 


SUB 


DX,DX 




ELSE 






MOV 


DX, VALUE 


END IF 






END IF 






MOV 


SEGREG, 


DX 


ENDM 






J LOW MEMORY SEGMENT 


ABSO SEGMENT AT 





ORG 


005H»4 




INT5 PTR 


LABEL 


DWORD 


ORG 


010H*U 




VIDEO 


LABEL 


DWORD 


ORG 


01 FH*4 




EXT_PTR 


LABEL 


DWORD 


ORG 


042H*4 




PLANAR_VIDEO 


LABEL 


DWORD 


ORG 


043H*4 




GRX_SET 


LABEL 


DWORD 


ORG 


0410H 




EQUIP LOW 


LABEL 


BYTE 


EQU 1 P_FLAG 


DW 


? 


; REUSE RAM FROM PLANAR 


ORG 


449H 




CRT MODE 


DB 




CRT COLS 


DW 


? 


CRT LEN 


DW 




CRT START 


DW 




CURSOR_POSN 


DW 


8 DUP 


CURSOR MODE 


DW 


? 


ACT IVE_ PAGE 


DB 


? 



; PRINT SCREEN VECTOR 

; VIDEO I/O VECTOR 

; GRAPHIC CHARS 128-255 

: REVECTORED 10H*4 

; GRAPHIC CHARS 0-255 



106 IBM Enhanced Graphics Adapter 



August!, 1984 



0463 
0U65 
0166 

0U72 
0U72 
0U84 
0U84 
0485 



ADDR_68U5 

CRT_M0DE_SET 

CRT_PALETTE 

ORG 
RESET_FLAG 

ORG 
ROWS DB 
PO I NTS DW 

INFO DB 



0500 
0500 
0501 



1*02 
U03 
UOU 
405 
1406 
U07 
U08 
409 
410 



415 
416 
417 
418 
419 
420 
421 
422 
423 
424 
425 
426 
427 
428 
429 
430 
431 
432 
433 
434 
435 
436 
437 



442 
443 
444 
445 
446 
447 
448 
449 
450 
451 
452 
453 
454 
455 
456 
457 
458 
459 
460 
461 
462 
463 
464 
465 
466 
467 
468 
469 
470 
471 
472 
473 
474 
475 
476 
477 
478 
479 
480 



07 - HIGH BIT OF MODE SET, CLEAR/NOT CLEAR REGEN 

D6 - MEMORY D6 05 = - 064K 1 - 128K 

05 - MEMORY 1 - 192K 1 1 - 256K 

04 - RESERVED 

03 - EGA ACTIVE MONITOR (0), EGA NOT ACTIVE (1) 

02 - WAIT FOR DISPLAY ENABLE (1) 

D1 - EGA HAS A MONOCHROME ATTACHED (1) 

DO - SET C_TYPE EMULATE ACTIVE (0) 



INF0_3 DB 



SAVE_PTR IS A POINTER TO A TABLE AS DESCRIBED AS FOLLOWS ; 



DW0RD_1 
DW0RD_2 
DW0RD_3 
DW0RD_4 
DW0RD_5 
DW0RD_6 
DW0RD_7 

DW0RD_1 



VIDEO PARAMETER TABLE POINTER 

DYNAMIC SAVE AREA POINTER 

ALPHA MODE AUXILIARY CHAR GEN POINTER 

GRAPHICS MODE AUXILIARY CHAR GEN POINTER 

RESERVED 

RESERVED 

RESERVED 

PARAMETER TABLE POINTER 

INITIALIZED TO BIOS EGA PARAMETER TABLE. 

THIS VALUE MUST EXIST. 

PARAMETER SAVE AREA POINTER 

INITIALIZED TO 0000:0000, THIS VALUE IS OPTIONAL. 

WHEN NON-ZERO, THIS POINTER WILL BE USED AS POINTER 

TO A RAM AREA WHERE CERTAIN DYNAMIC VALUES ARE TO 

BE SAVED. WHEN IN EGA OPERATION THIS RAM AREA WILL 

HOLD THE 16 EGA PALETTE REGISTER VALUES PLUS 

THE OVERSCAN VALUE IN BYTES 0-160 RESPECTIVELY. 

AT LEAST 256 BYTES MUST BE ALLOCATED FOR THIS AREA. 

ALPHA MODE AUXILIARY POINTER 

INITIALIZED TO 0000:0000, THIS VALUE IS OPTIONAL. 
WHEN NON-ZERO, THIS POINTER IS USED AS A POINTER 
TO A TABLES DESCRIBED AS FOLLOWS : 

BYTE BYTES/CHARACTER 

BYTE BLOCK TO LOAD, SHOULD BE ZERO FOR NORMAL 

OPERATION 
WORD COUNT TO STORE, SHOULD BE 2560 FOR NORMAL 

OPERATION 
WORD CHARACTER OFFSET, SHOULD BE ZERO FOR NORMAL 

OPERATION 
DWORD POINTER TO A FONT TABLE 
BYTE DISPLAYABLE ROWS 

IF 'FF' THE MAXIMUM CALCULATED VALUE WILL BE 

USED, ELSE THIS VALUE WILL BE USED 
BYTE CONSECUTIVE BYTES OF MODE VALUES FOR WHICH 

THIS FONT DESCRIPTION IS TO BE USED. 

THE END OF THIS STREAM IS INDICATED BY A 

BYTE CODE OF ' FF' 

NOTE : USE OF THIS POINTER MAY CAUSE UNEXPECTED 
CURSOR TYPE OPERATION. FOR AN EXPLANATION 
OF CURSOR TYPE SEE AH = 01 IN THE INTERFACE 
SECTION. 

GRAPHICS MODE AUXILIARY POINTER 

INITIALIZED TO 0000:0000, THIS VALUE IS OPTIONAL. 
WHEN NON-ZERO, THIS POINTER IS USED AS A POINTER 
TO A TABLES DESCRIBED AS FOLLOWS : 



BYTE 
WORD 
DWORD 
BYTE 



ORG 
STATUS_BYTE 
ABSO ENDS 



DISPLAYABLE ROWS 

BYTES PER CHARACTER 

POINTER TO A FONT TABLE 

CONSECUTIVE BYTES OF MODE VALUES FOR WHICH 

THIS FONT DESCRIPTION IS TO BE USED. 

THE END OF THIS STREAM IS INDICATED BY A 

BYTE CODE OF ' FF' 



8255 PORT B ADDR 



: 00C4 

= 00C5 

= 0004 

= 00B4 

= 00D5 

: OOCC 

= OOCA 

: OOCE 

: OOCF 

: 00C2 

: 00C2 

: OOBA 

: 00 DA 

: OODA 

: OOCO 



485 
486 
487 



494 
495 
496 
497 
498 
499 
500 
501 
502 
503 
504 



EQUATES FOR CARC 

SEQ ADDR 


PORT / 
EQU 


\DDRESS 
0C4H 


SEQ DATA 


EQU 


0C5H 


CRTC ADDR 


EQU 


0D4H 


CRTG ADDR B 


EQU 


0B4H 


CRTC DATA 


EQU 


0D5H 


GRAPH 1 POS 


EQU 


OCCH 


GRAPH 2 POS 


EQU 


OCAH 


GRAPH ADDR 


EQU 


OCEH 


GRAPH DATA 


EQU 


OCFH 


MISC OUTPUT 


EQU 


0C2H 


1 N_STAT_0 


EQU 


0C2H 


INPUT STATUS B 


EQU 


OBAH 


INPUT STATUS 


EQU 


ODAH 


ATTR READ 


EQU 


ODAH 


ATTR_WR 1 TE 
EQUATES FOR ADDF 


EQU 
ESS RE 


OCOH 
SISTER \ 



August 2, 1984 



IBM Enhanced Graphics Adapter 107 



= 0000 






505 


= 0001 






506 


= 0002 






507 


= 0003 






508 


= 000«4 






509 
510 


= 0000 






511 


= 0001 






512 


= 0002 






513 


= 0003 






514 


= 000«4 






515 


= 0005 






516 


= 0006 






517 


= 0007 






518 


= 0008 






519 


= 0009 






520 


= OOOA 






521 


= OOOB 






522 


= OOOC 






523 


= OOOD 






524 


= OOOE 






525 


= 000 F 






526 


= 0010 






527 


= 0010 






528 


= 0011 






529 


= 0011 






530 


= 0012 






531 


= 0013 






532 


= 001U 






533 


= 0015 






534 


= 0016 






535 


= 0017 






536 


= 0018 






537 
538 


= 0000 






539 


= 0001 






540 


= 0002 






541 


= 0003 






542 


= OOOU 






543 


= 0005 






544 


= 0006 






545 


= 0007 






546 


= 0008 






547 
548 


= 0010 






549 


= oon 






550 


= 0012 






551 


= 0013 






552 
553 
554 
555 
556 
557 


0000 






558 
559 
560 
561 
562 
563 
564 
565 
566 


0000 






567 


0000 55 






568 


0001 AA 






569 


0002 20 






570 
571 
572 
573 
574 
575 
576 
577 
578 
579 
580 
581 
582 
583 
584 
585 
586 
587 
588 
589 
590 
591 
592 
593 
594 
595 
596 
597 
598 
599 
600 
601 
602 
603 
604 


0003 






605 


0003 EB 


28 




606 


0005 32 


3H 30 


30 


607 


0009 36 


32 37 


37 33 35 


608 


36 


20 28 


U3 29 43 


609 


UF 


50 59 


52 U9 47 


610 


48 


54 20 


49 42 4D 


611 


20 


31 39 


38 34 


612 


0026 39 


2F 31 


33 2F 38 


613 


3U 






614 
615 
616 
617 


002D 






618 


002D B6 


03 




619 


002 F B2 


DA 




620 


0031 EC 






621 


0032 B2 


BA 




622 


003U EC 






623 


0035 B2 


CO 




624 


0037 BO 


00 




625 


0039 EE 






626 
627 
628 


003A 2B 


D2 




629 


0030 8E 


DA 




630 



S RESET 


EQU 


OOH 


S_CL0CK 


EQU 


01H 


S MAP 


EQU 


02H 


S_CGEN 


EQU 


03H 


S_MEM 


EQU 


04H 


C HRZ TOT 


EQU 


OOH 


C_HRZ DSP 


EQU 


01H 


C STRT HRZ BLK 


EQU 


02H 


C END HRZ BLK 


EQU 


03H 


C STRT HRZ SYN 


EQU 


04H 


C END HRZ SYN 


EQU 


05H 


C VRT TOT 


EQU 


06H 


C OVERFLOW 


EQU 


07H 


C PRE ROW 


EQU 


08H 


C MAX SCAN LN 


EQU 


09H 


C CRSR START 


EQU 


OAH 


C CRSR END 


EQU 


OBH 


C STRT HGH 


EQU 


OCH 


C STRT LOW 


EQU 


ODH 


C CRSR LOG HGH 


EQU 


OEH 


C CRSR LOG LOW 


EQU 


OFH 


C VRT SYN STRT 


EQU 


10H 


C LGHT PEN HGH 


EQU 


10H 


C VRT SYN END 


EQU 


IIH 


C LGHT PEN LOW 


EQU 


11H 


C VRT DSP END 


EQU 


12H 


G OFFSET 


EQU 


13H 


C UNDERLN LOC 


EQU 


14H 


C STRT VRT BLK 


EQU 


15H 


C END VRT BLK 


EQU 


16H 


G MODE CNTL 


EQU 


17H 


C_LN_COMP 


EQU 


18H 


G SET RESET 


EQU 


OOH 


G ENBL SET 


EQU 


01H 


G CLR COMP 


EQU 


02H 


G DATA ROT 


EQU 


03H 


G READ MAP 


EQU 


04H 


G MODE 


EQU 


05H 


G_MISC 


EQU 


06H 


G COLOR 


EQU 


07H 


G_B 1 T_MASK 


EQU 


08H 


P MODE 


EQU 


10H 


P_OVERSC 


EQU 


11H 


P CPLANE 


EQU 


12H 


P_HPEL 


EQU 


13H 



WRITE ONLY 
READ ONLY 
WRITE ONLY 
READ ONLY 



• CODE SEGMENT 

SEGMENT PUBLIC 

INCLUDE VPOST.INC 

SUBTTL VPOST.INC 

PAGE 



CS:CODE,DS:ABSO 

OH 

055H 

OAAH 

020H 



SIGNATURE 

BYTES 
LENGTH INDICATOR 



• NOTE : DO NOT USE THE SIGNATURE BYTES AS A PRESENCE TEST 
PLANAR VIDEO SWITCH SETTINGS 

- UNUSED 

1 - 40 X 25 COLOR 

1 - 80 X 25 COLOR 

1 1 - 80 X 25 MONOCHROME 
: : MUST BE SET WHEN THIS ADAPTER IS INSTALLED. 

VIDEO ADAPTER SWITCH SETTINGS 

- MONOG PRIMARY, EGA COLOR, 40X25 

1 - MONOC PRIMARY, EGA COLOR, 80X25 

1 - MONOC PRIMARY, EGA HI RES EMULATE (SAME AS 0001) 

1 1 - MONOC PRIMARY, EGA HI RES ENHANCED 

1 - COLOR 40 PRIMARY, EGA MONOCHROME 

1 1 - COLOR 80 PRIMARY, EGA MONOCHROME 

1 1 - MONOC SECONDARY, EGA COLOR, 40X25 

1 1 1 - MONOC SECONDARY, EGA COLOR, 80X25 

1 - MONOC SECONDARY, EGA HI RES EMULATE (SAME AS 0111) 
1 1 - MONOC SECONDARY, EGA HI RES ENHANCED 

1 1 - COLOR 40 SECONDARY, EGA MONOCHROME 
1 1 1 - COLOR 80 SECONDARY, EGA MONOCHROME 

1 1 - RESERVED 

1 1 1 - RESERVED 

1 1 1 - RESERVED 

1 1 1 1 - RESERVED 

SETUP ROUTINE FOR THIS MODULE 

SETUP PROG FAR 

JMP SHORT LI 

DB '2400' 

DB '6277356 (C)COPYRIGHT IBM 1984' 



■ SET UP VIDEO VECTORS 



MOV 


DH,3 


MOV 


DL, INPUT STATUS 


IN 


AL, DX 


MOV 


DL, INPUT STATUS 


IN 


AL, DX 


MOV 


DL,ATTR WRITE 


MOV 


AL,0 


OUT 


DX,AL 


SRLOAD 


DS,0 


SUB 


DX,DX 


MOV 


DS,DX 



108 IBM Enhanced Graphics Adapter 



August 2, 1984 



003E 

003 F 
00*45 
00U9 

004 F 
0055 
005B 

005 F 
0065 
0069 
006F 
0073 



007U 
0079 
007C 
0080 
0083 
0087 
008B 
008E 
0091 
0091 
0092 



0092 
0092 
0093 
009U 
0095 
0096 
0098 
009A 
009B 



FA 

C7 06 0040 R 0CD7 R 

8C OE 0042 R 

C7 06 0108 R F065 

C7 06 01 OA R FOCO 

C7 06 04A8 R 01 OC R 

8C OE 04AA R 

C7 06 007C R 0000 E 

8C OE 007E R 

C7 06 01 OC R 0000 E 

8C OE 010E R 

FB 



C6 06 0487 R 04 
E8 009B R 
88 IE 0488 R 
E8 OOCE R 
08 06 0488 R 
8A IE 0488 R 
E8 00F3 R 
E9 0244 R 



CB 



009B 


B6 


03 


009D 


B2 


C2 


009F 


BO 


01 


00A1 


EE 




00A2 


BO 


OD 


00A4 


E8 


0092 R 


00A7 


DO 


E8 


00A9 


DO 


E8 


OOAB 


DO 


E8 


OOAD 


8A 


D8 


OOAF 


BO 


09 


00B1 


E8 


0092 R 


00B4 


DO 


E8 


00B6 


DO 


E8 


00B8 


OA 


D8 


00 BA 


BO 


05 


OOBC 


E8 


0092 R 


OOBF 


DO 


E8 


00C1 


OA 


D8 


00C3 


BO 


01 


00C5 


E8 


0092 R 


00C8 


OA 


D8 


OOCA 


80 


E3 OF 


OOCD 


C3 




OOCE 






OOCE 






OOCE 


B6 


03 


OODO 


B2 


BA 


00D2 


BO 


01 


00D4 


EE 




00D5 


B2 


DA 


00D7 


EE 




00D8 


B2 


C2 


00 DA 


EC 




OODB 


24 


60 


OODD 


DO 


E8 


OODF 


8A 


D8 


00E1 


B2 


BA 


00E3 


BO 


02 


00E5 


EE 




00 E6 


B2 


DA 


00E8 


EE 




00 E9 


B2 


02 


00 EB 


EC 




OOEC 


24 


60 


OOEE 


DO 


EO 


00 FO 


OA 


C3 


00 F2 


C3 




OOFS 







00F3 


2A FF 


00 F5 


80 E3 OF 


00 F8 


D1 E3 


00 FA 


52 


OOFB 


B6 03 


00 FD 


8A E6 


OOFF 


5A 


0100 


80 E4 01 


0103 


FE C4 


0105 


F6 D4 


0107 


2E: FF A7 0128 


010C 




010C 


0717 R 


010E 


COOO 


0110 


0000 


0112 


0000 


0114 


0000 


0116 


0000 


0118 


0000 



632 
633 
634 
635 
636 
637 
638 
639 
640 
641 
642 
643 
644 
645 
646 
647 
648 
649 
650 
651 
652 
653 
654 
655 
656 
657 
658 
659 
660 
661 
662 
663 
664 
665 
666 
667 
668 
669 
670 
671 
672 
673 
674 
675 
676 
677 
678 
679 
680 
681 
682 
683 
684 
685 
686 
687 
688 
689 
690 
691 
692 
693 
694 
695 
696 
697 
698 
699 
700 
701 
702 
703 
704 
705 
706 
707 
708 
709 
710 
711 
712 
713 
714 



717 
718 
719 
720 



727 
728 
729 
730 
731 
732 
733 
734 
735 
736 
737 
738 
739 
740 



744 
745 
746 
747 
748 
749 
750 
751 
752 
753 
754 
755 
756 



MOV WORD PTR VI DEO, OFFSET C0MB0_VIDE0 

MOV WORD PTR VIDEO+2, CS 

MOV WORD PTR PLANAR_VI DEO,0F065H 

MOV WORD PTR PLANAR_VI DEO+2,0FOO0H 

MOV WORD PTR SAVE_PTR, OFFSET SAVE_TBL 

MOV WORD PTR SAVE_PTR+2, CS 

MOV WORD PTR EXT_PTR, OFFSET I NT_1 F_1 

MOV WORD PTR EXT_PTR+2, CS 

MOV WORD PTR GRX_SET, OFFSET CGDDOT 

MOV WORD PTR GRX_SET+2, CS 





POST FOR 
MOV 


COMBO VIDEO CAF 
INFO,00000100B 




CALL 


RD SWS 




MOV 


INFO 3,BL 




CALL 


F_BTS 




OR 


INFO 3,AL 




MOV 


BL. INF0_3 




CALL 


MK ENV 




JMP 


POST 


SKIP: 


RET 




VIDEO_ 


SETUP 


ENDP 


P0R_1 


PROG 


NEAR 




OUT 


DX.AL 




PUSH 


AX 




POP 


AX 




IN 


AL, DX 




AND 


AL.OIOH 




SHR 


AL, 1 




RET 




P0R_1 


ENDP 






READ THE 


SWITCH SETTINGS 


RD_SWS 


PROC 


NEAR 




ASSUME 


DS:ABSO 




MOV 


DH,3 




MOV 


DL,MISC OUTPUT 




MOV 


AL, 1 




OUT 
COULD BE 


DX,AL 
0,4,8,C 



MOV 
CALL 
SHR 
SHR 
SHR 
MOV 

MOV 
CALL 
SHR 
SHR 



MOV 
CALL 
SHR 



AL,ODH 
P0R_1 
AL, 1 
AL, 1 
AL, 1 
BL,AL 

AL,9 
P0R_1 
AL, 1 
AL, 1 
BL,AL 

AL,5 



RD_SWS ENDP 



F_BTS 


OBTA 1 N 
PROC 


THE FEATURE BITS FROM DAUGHTEF 
NEAR 




MOV 


DH,3 




MOV 


DL.OBAH 




MOV 


AL,1 




OUT 


DX,AL 




MOV 


DL,ODAH 




OUT 


DX,AL 




MOV 


DL, IN STAT 




IN 


AL,DX 




AND 


AL,060H 




SHR 


AL, 1 




MOV 


BL,AL 




MOV 


DL, OBAH 




MOV 


AL,2 




OUT 


DX,AL 




MOV 


DL,ODAH 




OUT 


DX,AL 




MOV 


DL, 1 N STAT 




IN 


AL,DX 




AND 


AL,060H 




SHL 


AL, 1 




OR 


AL,BL 




RET 




F_BTS 


ENDP 






ESTABLI 


SH THE VIDEO ENVIRONMENT, KEY 


MK_ENV 


PROC 


NEAR 




ASSUME 


DS:ABSO 




SUB 


BH.BH 




AND 


BL,OFH 




SAL 


BX, 1 




PUSH 


DX 




MOV 


DH,3 




MOV 


AH,DH 




POP 


DX 




AND 


AH,1 




INC 






NOT 


AH 




JMP 


WORD PTR CS:[BX + OFFSET T5 


SAVE_TBL 


LABEL DWORD 




DW 


OFFSET VIDEO FARMS 




DW 


OCOOOH 



READ FEATURE BITS 



READ FEATURE BITS 



■ OF THE SWITCHES 



PARMS 

PARMS 

PAL SAVE AREA 

PAL SAVE AREA 

ALPHA TABLES 

ALPHA TABLES 

GRAPHICS TABLES 



Ai^st 2, 1984 



IBM Enhanced Graphics Adapter 109 



011A 


0000 




757 


C 






DW 













758 













one 


0000 




759 


C 






DW 





011E 


0000 




760 


C 






DW 





0120 


0000 




761 


C 






DW 





0122 


0000 




762 


C 






DW 





0124 


0000 




763 


C 






DW 





0126 


0000 




764 


C 






DW 













765 


C 










0128 








766 


C 


T5 




LABEL 


WORD 


0128 


0173 R 




767 


c 






DW 


OFFSET PST 


012A 


017E R 




768 


c 






DW 


OFFSET PST 1 


012C 


017E R 




769 


C 






DW 


OFFSET PST 2 


012E 


0189 R 




770 


C 






DW 


OFFSET PST 3 


0130 


0194 R 




771 


c 






OW 


OFFSET PST 4 


0132 


01 A8 R 




772 


c 






DW 


OFFSET PST 5 


0134 


01 BC R 




773 


c 






DW 


OFFSET PST_6 


0136 


01C7 R 




774 


c 






DW 


OFFSET PST_7 










775 


c 










0138 


01C7 R 




776 


c 






DW 


OFFSET PST 8 


01 3A 


01 02 R 




777 


c 






DW 


OFFSET PST 9 


013C 


01 DD R 




778 


c 






DW 


OFFSET PST A 


013E 


01F1 R 




779 


c 






DW 


OFFSET PST B 


01U0 


0204 R 




780 


c 






DW 


OFFSET PST OUT 


01U2 


0204 R 




781 


c 






DW 


OFFSET PST OUT 


0144 


0204 R 




782 


c 






DW 


OFFSET PST OUT 


01U6 


0204 R 




783 


c 






DW 


OFFSET PST_OUT 










784 


c 










0148 








785 


c 


ENV_ 


_X 


PROC 


NEAR 


0148 


80 


26 0410 R CF 


786 


c 






AND 


EQUIP LOW.OCFH 


0140 


80 


OE 0410 R 10 


787 


c 






OR 


EQUIP LOW, 01 OH 


0152 


B8 


0001 




788 


c 






MOV 


AX, 1H 


0155 


CD 


10 




789 


c 






INT 


10H 


0157 


C3 






790 


c 






RET 




0158 








791 
792 


c 
c 


ENV. 


.X 


ENDP 




0158 








793 


c 


ENV 


_0 


PROC 


NEAR 


0158 


80 


26 0410 R CF 


794 


c 






AND 


EQUIP LOW,OCFH 


015D 


80 


OE 0410 R 20 


795 


c 






OR 


EQUIP L0W,020H 


0162 


B8 


0003 




796 


c 






MOV 


AX,03H 


0165 


CD 


10 




797 


c 






INT 


10H 


0167 


C3 






798 


c 






RET 




0168 








799 
800 


c 
c 


ENV. 


.0 


ENDP 




0168 








801 


c 


ENV. 


_3 


PROC 


NEAR 


0168 


80 


OE 0410 R 30 


802 


c 






OR 


EQUIP L0W,030H 


016D 


B8 


0007 




803 


c 






MOV 


AX,07H 


0170 


CD 


10 




804 


c 






INT 


10H 


0172 


C3 






805 


c 






RET 




0173 








806 
807 
808 


c 
c 
c 


ENV 


.3 


ENDP 




0173 








809 


c 


PST. 


.0: 






0173 


20 


26 0487 R 


810 


c 






AND 


INFO. AH 


0177 


E8 


0148 


R 


811 


c 






CALL 


ENV X 


017A 


E8 


0168 


R 


812 


c 






CALL 


ENV_3 


0170 


C3 






813 


c 






RET 




017E 








814 


c 


PST 








017E 








815 


c 


PST. 


l2: 






017E 


20 


26 0487 R 


816 


c 






AND 


INFO, AH 


0182 


E8 


0158 


R 


817 


c 






CALL 


ENV 


0185 


E8 


0168 


R 


818 


c 






CALL 


ENV_3 


0188 


C3 






819 


c 






RET 




0189 








820 


c 


PST. 


.3: 






0189 


20 


26 0487 R 


821 


c 






AND 


INFO,AH 


0180 


E8 


0158 


R 


822 


c 






CALL 


ENV_0 


0190 


E8 


0168 


R 


823 


c 






CALL 


ENV_3 


0193 


C3 






824 


c 






RET 




0194 








825 


c 


PST. 


.4: 






0194 


B6 


03 




826 


c 






MOV 


OH, 3 


0196 


B2 


02 




827 


c 






MOV 


DL,MISC OUTPUT 


0198 


BO 


00 




828 


c 






MOV 


AL,0 


01 9A 


EE 






829 


c 






OUT 


DX,AL 


019B 


F6 


04 




830 


c 






NOT 


AH 


019D 


08 


26 0487 R 


831 


c 






OR 


INFO, AH 


01A1 


E8 


0168 


R 


832 


c 






CALL 


ENV 3 


01A4 


E8 


0148 


R 


833 


c 






CALL 


ENV_X 


01A7 


C3 






834 


c 






RET 




01A8 








835 


c 


PST. 


.5: 






01A8 


86 


03 




836 


c 






MOV 


OH, 3 


OlAA 


B2 


C2 




837 


c 






MOV 


DL,MISC OUTPUT 


01AC 


80 


00 




838 


c 






MOV 


AL,0 


01AE 


EE 






839 


c 






OUT 


DX,AL 


01AF 


F6 


D4 




840 


c 






NOT 


AH 


01B1 


08 


26 0487 R 


841 


c 






OR 


INFO, AH 


01B5 


E8 


0168 


R 


842 


c 






CALL 


ENV_3 


0188 


E8 


0158 


R 


843 


c 






CALL 


ENV_0 


01BB 


C3 






844 


c 






RET 




01 BC 








845 


c 


PST. 


.6: 






01BC 


20 


26 0487 R 


846 


c 






AND 


INFO, AH 


01C0 


E8 


0168 


R 


847 


c 






CALL 


ENV 3 


01C3 


E8 


0148 


R 


848 


c 






CALL 


ENV_X 


01C6 


03 






849 


c 






RET 




01C7 








850 


c 


PST 


.7: 






01C7 








851 


c 


pstI 


.8: 






01C7 


20 


26 0487 R 


852 


c 






AND 


INFO, AH 


01CB 


E8 


0168 


R 


853 


c 






CALL 


ENV 3 


01CE 


E8 


0158 


R 


854 


c 






CALL 


ENV_0 


01D1 


C3 






855 


c 






RET 




0102 








856 


c 


PST. 


-9: 






01 02 


20 


26 0487 R 


857 


c 






AND 


INFO, AH 


01D6 


E8 


0168 


R 


858 


c 






CALL 


ENV_3 


0109 


E8 


0158 


R 


859 


c 






CALL 


ENV_0 


01DC 


C3 






860 


c 






RET 




01 DD 








861 


c 


PST. 


A: 






01DD 


86 


03 




862 


c 






MOV 


OH, 3 


01DF 


82 


C2 




863 


c 






MOV 


DL,MISC OUTPUT 


01E1 


BO 


00 




864 


c 






MOV 


AL.O 


01E3 


EE 






865 


c 






OUT 


DX,AL 


01 E4 


F6 


04 




866 


c 






NOT 


AH 


01 E6 


08 


26 0487 R 


867 


c 






OR 


INFO, AH 


01 EA 


E8 


0148 


R 


868 


c 






CALL 


ENV X 


01ED 


E8 


0168 


R 


869 


c 






CALL 


ENV_3 


01 FO 


C3 






870 


c 






RET 




01F1 








871 


c 


PST. 


-B: 






01F1 


B6 


03 




872 


c 






MOV 


DH,3 


01 F3 


82 


C2 




873 


c 






MOV 


DL,MISC_OUTPUT 


01 F5 


80 


00 




874 


c 






MOV 


AL,0 


01F7 


EE 






875 


c 






OUT 


DX,AL 


01 F8 


F6 


D4 




876 


c 






NOT 


AH 


01 FA 


08 


26 0487 R 


877 


c 






OR 


INFO, AH 


01FE 


E8 


0158 


R 


878 


c 






CALL 


ENV 


0201 


E8 


0168 


R 


879 


c 






CALL 


ENV 3 


0204 








880 


c 


PST. 


.OUT: 




0204 


C3 






881 


c 






RET 




0205 








882 


c 


MK_ENV 


ENDP 





GRAPHICS TABLES 



SET 40X25 COLOR ALPHA 



SET 80X25 COLOR ALPHA 



SET MONOCHROME ALPHA 



110 IBM Enhanced Graphics Adapter 



August 2, 1984 



883 
88U 
885 
886 
887 



THIS ROUTINE TESTS THE CRT CARD INTERNAL DATA BUS AND IN A LIMITED 
WAY TESTS THE CRTC VIDEO CHIP BY WRITING/READING FROM CURSOR REGISTER ; 
CARRY IS SET I F AN ERROR IS FOUND 



0205 






0205 


53 




0206 


BB 


007 F 


0209 


8R 


FB 


020B 


50 




020C 


Ffi 


022C R 


020 F 


«B 


FO 


0211 


58 




0212 


50 




0213 


t8 


0236 R 


0216 


5H 




0217 


50 




0218 


tH 


022C R 


021B 


3B 


C7 


021D 


58 




021 E 


75 


03 


0220 


l-B 


05 90 


0223 






0223 


33 


CO 


0225 


5B 




0226 


03 




0227 






0227 


B8 


0001 


022A 


5B 




022B 


C3 




0220 







0220 




022C 


52 


022D 


AH 


022 F 


BO 


0231 


FF 


0232 


»42 


0233 


tc 


0234 


5A 


0235 


C3 


0236 





0236 


50 


0237 


52 


0238 


8B DO 


023A 


84 OE 


023C 


BO 7F 


023E 


E8 0D15 R 


0241 


5A 


0242 


58 


0243 


03 


0244 





0244 


Ffl 


OCFE R 


0247 


F6 


06 0487 R 02 


024C 


75 


12 


024E 


B« 


03B4 


0251 


E8 


0205 R 


0254 


3U 


0001 


0257 


74 


03 


0259 


tv 


0317 R 


025C 






025C 


B4 


30 


025E 


hB 


10 


0260 






0260 


B8 


03 D4 


0263 


E« 


0205 R 


0266 


SB 


0001 


0269 


74 


03 


026B 


t9 


0317 R 


026E 






026E 


B4 


20 


0270 






0270 


50 




0271 


BR 


BOOO 


0274 


BA 


03B8 


0277 


BQ 


1000 


027A 


BO 


01 


027C 


«0 


FC 30 


027F 


74 


08 


0281 


B/ 


B8 


0283 


B2 


D8 


0285 


B5 


40 


0287 


FE 


08 


0289 






0289 


EE 




028A 


8B 


2E 0472 R 


028E 


81 


FD 1234 


0292 


8E 


C3 



892 
893 
894 
895 
896 
897 
898 
899 
900 
901 
902 
903 
904 
905 
906 
907 
908 
909 
910 
911 
912 
913 
914 
915 
916 
917 
918 
919 
920 
921 
922 
923 
924 
925 
926 
927 
928 
929 
930 
931 
932 
933 
934 
935 
936 
937 
938 
939 
940 
941 
942 
943 
944 
945 
946 
947 
948 
949 
950 
951 
952 
953 
954 
955 
956 
957 
958 
959 
960 
961 
962 
963 
964 
965 
966 
967 
968 
969 
970 
971 
972 
973 
974 
975 
976 
977 
978 
979 



982 
983 
984 
985 



991 

992 

993 

994 

995 

996 

997 

998 

999 

1000 

1001 

1002 

1003 

1004 

1005 

1006 

1007 

1008 



CD PRESENCE TST 


PROC NEA 


PUSH 


BX 


MOV 


BX,07FH 


MOV 


01, BX 


PUSH 


AX 


CALL 


RD CURSOR 


MOV 


SI, AX 


POP 


AX 


PUSH 


AX 


CALL 


WR CURSOR 


POP 


AX 


PUSH 


AX 


CALL 


RD CURSOR 


CMP 


AX,DI 


POP 


AX 


JNZ 


NOT PRESENT 


JMP 


TST EX 


NOT PRESENT: 




XOR 


AX, AX 


POP 


BX 


RET 




TST EX: 




MOV 


AX, 1 


POP 


BX 


RET 




CD PRESENCE TST 


ENDP 



SAVE PORT ADDRESS 

SAVE ORIGINAL VALUE 
RECOVER PORT ADDRESS 
SAVE PORT ADDRESS 
WRITE CURSOR 
RECOVER PORT ADDRESS 
SAVE PORT ADDRESS 
READ IT BACK 
SAME? 

EXIT IF NOT EQUAL 



SET NOT PRESENT 



REGISTER AX IS MODIFIED. 



RD CURSOR 


PROC NEAR 


PUSH 


DX 


MOV 


DX,AX 


MOV 


AL,C CRSR LOC HGH 


OUT 


DX,AL 



SAVE REGS USED 



C RD_CURSOR ENDP 
C 

C ; 



ALL REGISTERS PRESERVED 



WR_OURSOR 


PROC NEAR 


PUSH 


AX 


PUSH 


DX 


MOV 


DX,AX 


MOV 


AH,C CRSR LOC HGH 


MOV 


AL,07FH 


CALL 


0UT_DX 


POP 


DX 


POP 


AX 


RET 




WR CURSOR 


ENDP 



SAVE REGS USED 



INITIALIZE AND START CRT CONTROLLER (6845) 
ON COLOR GRAPHICS AND MONOCHROME CARDS 
TEST VIDEO READ/WRITE STORAGE. 
DESCRIPTION 

RESET THE VIDEO ENABLE SIGNAL. 

SELECT ALPHANUMERIC MODE, 40 * 25, B & W. 

READ/WRITE DATA PATTERNS TO STG. CHECK STG 

ADDRESSABILITY. 



ASSUME DS:ABSO,ES:ABSO 





CALL 


DDS 




TEST 


INFO, 2 




JNZ 


COLOR PRESENCE TST 




MOV 


AX,03B4H 




CALL 


CD PRESENCE TST 




CMP 


AX, 1 




JE 


C0NT1 




JMP 


P0D14 


C0NT1: 








MOV 


AH,30H 




JMP 


SHORT OVER 


COLOR 


PRESENCE 


TST: 




MOV 


AX,03D4H 




CALL 


CD PRESENCE TST 




CMP 


AX, 1 




JE 


C0NT2 




JMP 


POD 14 


C0NT2: 








MOV 


AH,20H 


OVER: 








PUSH 


AX 




MOV 


BX,0B000H 




MOV 


DX, 3B8H 




MOV 


CX,4096 




MOV 


AL, 1 




CMP 


AH,30H 




JE 


E9 




MOV 


BH,0B8H 




MOV 


DL,0D8H 




MOV 


CH,40H 




DEC 


AL 



P.DS:RESET_FLAG 



MONOCHROME CARD INSTALLED 



COLOR GRAPHICS CARD INSTALLED 

RESAVE VALUE 

BEG VIDEO RAM ADDR B/W CD 

MODE CONTROL B/W 

RAM BYTE CNT FOR B/W CD 

SET MODE FOR BW CARD 

B/W VIDEO CARD ATTACHED? 

YES - GO TEST VIDEO STG 

BEG VIDEO RAM ADDR COLOR CD 

MODE CONTROL COLOR 

RAM BYTE CNT FOR COLOR CD 

SET MODE TO FOR COLOR CD 

TEST_VIDEO_STG: 

DISABLE VIDEO FOR COLOR CD 

POD INITIALIZED BY KBD RESET 



August 2, 1984 



IBM Enhanced Graphics Adapter 111 



029 D 

029D 58 

029E 50 

029F B8 7020 

02A2 2B FF 

02AU B9 0028 

02A7 F3/ AB 



02A9 


58 




02AA 


50 




02AB 


80 


FC 30 


02AE 


BA 


03BA 


02B1 


7U 


02 


02B3 


B? 


DA 


02B5 






02B5 


m 


08 


02B7 






02B7 


?B 


C9 


02B9 






02B9 


FC 




02BA 


22 


CU 


02BC 


75 


OU 


02BE 


t'A 


F9 


02C0 


FB 


09 


02C2 






02C2 


2B 


C9 


02CU 






02CU 


k; 




02C5 


22 


CU 


02C7 


ft* 


OA 


02C9 


E2 


F9 


02CB 






02CB 


BA 


0102 


02CE 


EH 


06C8 R 


02D1 


FB 


06 


02D3 






02D3 


B1 


03 


02D5 


D2 


EC 


02D7 


/5 


DE 


02D9 






02D9 


58 




02 DA 


EB 


3B 



02 DC 






02 DC 


B9 


UOOO 


02DF 






02DF 


FC 




02E0 


8B 


D9 


02E2 


B8 


AAAA 


02 E5 


BA 


Fh55 


02E8 


2B 


Fh 


02 EA 


F3/ AA 


02 EC 






02EC 


tF 




02 ED 


H) 




02EE 






02EE 


8B 


F7 


02 FO 


8B 


CB 


02 F2 






02 F2 


AC 




02F3 


32 


CU 


02 F5 


75 


1L 


02 F7 


8A 


C2 


02 F9 


AA 




02 FA 


L2 


F6 


02 FC 


22 


FU 


02FE 


74 


13 


0300 


8A 


FO 


0302 


86 


F2 


030l| 


22 


E4 


0306 


75 


OU 


0308 


8A 


DU 


030A 


FB 


FO 


030C 






030C 
030D 


hC 

47 




030E 


7«t 


m. 


0310 


UF 




0311 


FB 


1)9 


0313 






0313 


BO 


00 


0315 






0315 


KC 




0316 


C3 




0317 







1009 
1010 
1011 
1012 
1013 
101U 
1015 
1016 
1017 
1018 
1019 
1020 
1021 
1022 
1023 
1024 
1025 
1026 
1027 
1028 
1029 
1030 
1031 
1032 
1033 
1034 
1035 
1036 
1037 
1038 
1039 
1040 
1041 
1042 
1043 
1044 
1045 
1046 
1047 
1048 
1049 
1050 
1051 
1052 
1053 
1054 
1055 
1056 
1057 
1058 
1059 
1060 
1061 
1062 
1063 
1064 
1065 
1066 
1067 
1068 
1069 
1070 
1071 
1072 
1073 
1074 
1075 
1076 
1077 
1078 
1079 
1080 
1081 
1082 
1083 
1084 
1085 
1086 
1087 
1088 
1089 
1090 
1091 
1092 
1093 
1094 
1095 
1096 
1097 
1098 
1099 
1100 
1101 
1102 



1112 
1113 
1114 
1115 
1116 
1117 
1118 
1119 
1120 
1121 
1122 
1123 
1124 
1125 
1126 
1127 
1128 
1129 
1130 
1131 
1132 
1133 



JE 


E10 


MOV 


DS,BX 


ASSUME 


OS: N0THING,ES: NOTHING 


CALL 


STGTST CNT 


JNE 


E17 



SETUP VIDEO DATA ON SCREEN FOR VIDEO LINE TEST, 
DESCRIPTION 

ENABLE VIDEO SIGNAL AND SET MODE. 
DISPLAY A HORIZONTAL BAR ON SCREEN. 



POP 


AX 


PUSH 


AX 


MOV 


AX.7020H 


SUB 


DI,DI 


MOV 


ex. 40 


REP 


STOSW 



GET VIDEO SENSE SWS (AH) 

SAVE IT 

WRT BLANKS IN REVERSE VIDEO 

SETUP STARTING LOG 

NO. OF BLANKS TO DISPLAY 

WRITE VIDEO STORAGE 



CRT INTERFACE LINES TEST 
UPTION 
SENSE ON/OFF TRANSITION OF THE VIDEO ENABLE 
AND HORIZONTAL SYNC LINES. 



POP 


AX 


PUSH 


AX 


CMP 


AH.30H 


MOV 


DX,03BAH 


JE 


Ell 


MOV 


DL,ODAH 



IN 

AND 

JNZ 

LOOP 

JMP 


AL.DX 

AL,AH 

E14 

E13 

SHORT El 7 


SUB 


CX,CX 


IN 
AND 
JZ 
LOOP 


AL,DX 
AL.AH 
E16 
E15 


MOV 
CALL 
JMP 


DX, 102H 
ERR BEEP 
SHORT El 8 


MOV 
SHR 
JNZ 


CL,3 

AH,CL 

E12 



; GET VIDEO SENSE SW INFO 

; SAVE IT 

; B/W CARD ATTACHED? 

; SETUP ADDR OF BW STATUS PORT 

; YES - GO TEST LINES 

; COLOR CARD IS ATTACHED 

; LINE_TST: 

; OFLOOP_CNT: 



READ CRT STATUS PORT 

CHECK VIDEO/HORZ LINE 

ITS ON - CHECK IF IT GOES OFF 

LOOP TILL ON OR TIMEOUT 

GO PRINT ERROR MSG 



READ CRT STATUS PORT 
CHECK VIDEO/HORZ LINE 
ITS ON - CHECK NEXT LINE 
LOOP IF OFF TILL IT GOES ON 
CRT_ERR 



SHORT P0D14 



GO BEEP SPEAKER 



GO CHECK HORIZONTAL LINE 

DISPLAY_CURSOR: 
GET VIDEO SENSE SWS (AH) 



THIS SUBROUTINE PERFORMS A READ/WRITE STORAGE TEST ON 
A 16K BLOCK OF STORAGE. 
ENTRY REQUIREMENTS: 

ES = ADDRESS OF STORAGE SEGMENT BEING TESTED 
DS = ADDRESS OF STORAGE SEGMENT BEING TESTED 
WHEN ENTERING AT STGTST_CNT, CX MUST BE LOADED WITH 
THE BYTE COUNT. 
EXIT PARAMETERS: 

ZERO FLAG = IF STORAGE ERROR (DATA COMPARE OR PARITY CHECK. 
AL = DENOTES A PARITY CHECK. ELSE AL=XOR'ED BIT 
PATTERN OF THE EXPECTED DATA PATTERN VS THE 
ACTUAL DATA READ. 
AX, BX, CX, DX, D I , AND SI ARE ALL DESTROYED. 



STGTST 


PROG 


NEAR 




MOV 


CX,4000H 


STGTST. 


CNT: 
" CLD 






MOV 


BX,CX 




MOV 


AX, OAAAAH 




MOV 


DX.0FF55H 




SUB 


DI,DI 




REP 


STOSB 


C3: 








DEC 


Dl 




STD 




C4: 








MOV 


SI,DI 




MOV 


CX,BX 


C5: 


LODSB 






XOR 


AL,AH 




JNE 


C7 




MOV 


AL,DL 




STOSB 






LOOP 


C5 




AND 


AH, AH 




JZ 


C6X 




MOV 


AH,AL 




XCHG 


DH,DL 




AND 


AH, AH 




JNZ 


C6 




MOV 


DL,AH 




JMP 


C3 



CLD 

RET 

STGTST ENDP 



SETUP CNT TO TEST A 16K BLK 

SET 01 R FLAG TO INCREMENT 
SAVE CNT (4K FOR VIDEO OR 16K) 
GET DATA PATTERN TO WRITE 
SETUP OTHER DATA PATTERNS TO USE 
Dl = OFFSET RELATIVE TO ES REG 
WRITE STORAGE LOCATIONS 

STG01 
POINT TO LAST BYTE JUST WRITTEN 
SET DIR FLAG TO GO BACKWARDS 



SETUP BYTE CNT 

INNER TEST LOOP 

READ OLD TEST BYTE [SI ]+ 

DATA READ AS EXPECTED ? 

NO - GO TO ERROR ROUTINE 
GET NEXT DATA PATTERN TO WRITE 
WRITE INTO LOCATION JUST READ 

DECREMENT COUNT AND LOOP CX 

ENDING PATTERN WRITTEN TO STG? 
YES - RETURN TO CALLER WITH AL=0 
SETUP NEW VALUE FOR COMPARE 
MOVE NEXT DATA PATTERN TO DL 
READING ZERO PATTERN THIS PASS ? 
CONTINUE TEST SEQUENCE TILL 
ELSE SET FOR END READ PATTERN 
AND MAKE FINAL BACKWARDS PASS 

SET DIR FLAG TO GO FORWARD 
SET POINTER TO BEG LOCATION 
READ/WRITE FORWARD IN STG 
ADJUST POINTER 
READ/WRITE BACKWARD IN STG 

AL=0 DATA COMPARE OK 

SET DIRECTION FLAG BACK TO INC 



134 



EGA CRT ATTACHMENT TEST 

I NIT CRT TO 40X25 - BW ***»SET TO MODE**** 

CHECK FOR VERTICAL AND VIDEO ENABLES, AND CHECK 

TIMING OF SAME 

CHECK VERTICAL INTERRUPT 

CHECK RED, BLUE, GREEN, AND INTENSIFY DOTS 



112 IBM Enhanced Graphics Adapter 



August 2, 1984 



= 00C8 




= 8D99 




= B862 




= 015E 




= 015E 




= 00U3 




= OOUO 




0317 






0317 


83 


EC OA 


031A 


8B 


EC 


031C 


E8 


OCFE R 


031 F 


BO 


30 


0321 


E6 


43 


0323 


BO 


00 


0325 


E6 


40 


0327 


F6 


06 0487 R 02 


032C 


7U 


IF 


032E 


E8 


0168 R 


0331 


C7 


46 02 015E 


0336 


C7 


46 04 8D99 


033B 


C7 


46 06 B862 


03U0 


B2 


B4 


03U2 


BU 


01 


03U4 


BO 


27 


03U6 


E8 


0D15 R 


0349 


82 


BA 


03UB 


EB 


2A 


0340 






03UD 


E8 


0148 R 


0350 


E8 


0E9A R 


0353 


73 


11 


0355 


B2 


04 


0357 


BU 


01 


0359 


BO 


14 


035B 


E8 


0D15 R 


035E 


C7 


46 02 015E 


0363 


EB 


06 90 


0366 






0366 


C7 


46 02 00C8 


036B 






036B 


C7 


46 04 AOAC 


0370 


C7 


46 06 C460 


0375 


B2 


OA 


0377 






0377 


B8 


0500 


037A 


CD 


10 


037C 


2B 


C9 


037E 






037E 


EC 




037F 


A8 


08 


0381 


75 


07 


0383 


E2 


F9 


0385 


B3 


00 


0387 


E9 


0448 R 


038A 






038A 


BO 


00 


038C 


E6 


40 


038E 


2B 


DB 


0390 


33 


C9 


0392 






0392 


EC 




0393 


A8 


08 


0395 


74 


07 


0397 


E2 


F9 


0399 


B3 


01 


039B 


E9 


0448 R 


039E 






039E 


28 


C9 


03A0 






03A0 


EC 




03A1 


A8 


01 


03A3 


74 


15 


03A5 


A8 


08 


03A7 


75 


23 


03A9 


E2 


F5 


03AB 


B3 


02 


03AD 


E9 


0448 R 


03B0 






03B0 


B3 


03 


03B2 


E9 


0448 R 


03B5 






03B5 


B3 


04 


03B7 


E9 


0448 R 


03BA 






03BA 


A8 


08 


03BC 


75 


F2 


03BE 






03BE 


EC 




03BF 


A8 


01 


03C1 


El 


FB 


03C3 


E3 


FO 



194 
195 
196 
197 
198 
199 
200 
201 
202 
203 
204 
205 
206 
207 
208 
209 
210 
211 
212 
213 
214 
215 
216 
217 
218 
219 
220 
221 
222 
223 
224 
225 
226 
227 
228 
229 
230 
231 
232 
233 
234 
235 
236 
237 
238 
239 
240 
241 
242 
243 
244 
245 
246 
247 
248 
249 
250 
251 
252 
253 
254 
255 
256 
257 
258 
259 
260 



I NIT TO 40X25 - COLOR/MONO *»**SET TO MODE**** 

- NOMINAL TIME IS B286H FOR 60 HZ. 
- NOMINAL TIME IS A2FEH FOR 50 HZ. 



C MAX_VERT_C0L0R EQU OAOACH 

C 

C MIN_VERT_COLOR EQU 0C460H 



CENAB_PER_ FRAME 


EQU 200 




MAX_VERT_M0N0 


EQU 08D99H 




MIN_VERT_M0N0 


EQU 0B862H 


. 


EENAB PER FRAME 


EQU 350 




MENAB_PER_FRAME 


EQU 350 




TIM CTL 


EQU 043H 




TIMERO 


EQU 040H 




P0D14 PROC 


NEAR 




SUB 


SP,OAH 




MOV 


BP,SP 




ASSUME 


DS:ABSO. ES;ABSO 




CALL 


DDS 




MOV 


AL,00110000B 




OUT 


TIM CTL,AL 




MOV 


AL,OOH 




OUT 


TIMERO.AL 




TEST 


INFO, 2 




JZ 


COLOR EGA V 




CALL 


ENV 3 




MOV 


WORD PTR BP 2 


MENAB PER FRAME ' 


MOV 


WORD PTR BP 4 


MAX VERT MONO 


MOV 


WORD PTR BP 6 


M 1 N_VERT_MONO 


MOV 


DL, CRTC_ADDR_B 




MOV 


AH,C HRZ DSP 




MOV 


AL,27H - 




CALL 


OUT DX 




MOV 


DL, INPUT STATUS 


.B ', 


JMP 


SHORT COMMON " 




COLOR EGA V: 






~ CALL 


ENV X 




CALL 


BRST DET 




JNC 


COLOR V 




MOV 


DL,CRTC ADDR 




MOV 


AH,1 




MOV 


AL,20 




CALL 


OUT DX 




MOV 


WORD PTR[BP][2] 


EENAB_PER_FRAME , 


JMP 


BRST_COLOR_V 




COLOR_V: 






MOV 


WORD PTR[BP)[2] 


CENAB_PER_FRAME , 


BRST COLOR V: 






~ MOV 


WORD PTR[BP][4] 


MAX VERT COLOR , 


MOV 


WORD PTR[BP]I61 


M 1 N_VERT_COLOR , 


MOV 


DL, INPUT_STATUS 




COMMON: 






MOV 


AX,0500H 





LOOK FOR VERTICAL 



TEST 
JNE 
LOOP 
MOV 
JMP 



AL,DX 

AL,00001000B 

P0D14_2 

P0D14_1 

BL,00 

P0D14_ERR 



GOT VERTICAL - START TIMER 



C P0D14_25: 



LOOP 
MOV 
JMP 



CX,CX 

AL,DX 

AL^OOOOIOOOB 

POD14_3 

P0D14_25 

BL,01H 

P0D14_ERR 



TEST 

JE 

TEST 

JNE 

LOOP 

MOV 

JMP 



CX,CX 

AL,DX 

AL, 0000000 IB 

P0D14_5 

AL,00001000B 

P0D14_75 

P0D14_4 

BL,02H 

P0D14_ERR 



MAX TIME FOR VERT/VERT 

(NOMINAL + 10%) 
MIN TIME FOR VERT/VERT 

(NOMINAL - 10%) 
NUM OF ENABLES PER FRAME 
MAX TIME FOR VERT/VERT 

(NOMINAL + 10%) 
MIN TIME FOR VERT/VERT 

(NOMINAL - 10%) 
ENHANCED ENABLES PER FRAME 
NUM OF ENABLES PER FRAME 



SET TIMER TO MODE 



SEND FIRST BYTE TO TIMER 



SET UP IN MONOCHROME 
NUM. OF FRAMES FOR MONO 
MAX TIME FOR VERT/VERT 
MIN TIME FOR VERT/VERT 
MONO CRTC REG 
HORIZ. TOTAL D I PLAY 
TO 40 COL 



NOW START LOOKING FOR ENABLE TRANSITIONS 



3BA 



SET UP IN 40X25 COLOR 

ENHANCED MODE 

NO, 40X25 

BRST MODE ONLY! 

HRZ DSP END 

MODIFY FOR TEST ONLY 

NUM. OF FRAMES FOR COLOR 



NUM. OF FRAMES FOR COLOR 

MAX TIME FOR VERT/VERT 
MIN TIME FOR VERT/VERT 
SET ADDRESSING TO VIDEO 
ATTR STATUS 

SET TO VIDEO PAGE 



GET STATUS 
VERTICAL THERE YET? 
CONTINUE IF IT IS 
KEEP LOOKING TILL COUNT 

EXHAUSTED 
NO VERTICAL 



SEND 2ND BYTE TO TIMER TO 

START IT 

INIT. ENABLE COUNTER 



; GET STATUS 

: VERTICAL STILL THERE 

; CONTINUE IF IT'S GONE 

; KEEP LOOKING TILL COUNT 

; EXHAUSTED 

; VERTICAL STUCK ON 



GET STATUS 
ENABLE ON YET? 
GO ON IF IT IS 
VERTICAL ON AGAIN? 
CONTINUE IF IT IS 
KEEP LOOKING IF NOT 

ENABLE STUCK OFF 



VERTICAL STUCK ON 



ENABLE STUCK ON 



• MAKE SURE VERTICAL WENT OFF WITH ENABLE GOING ON 



TEST AL, 00001 OOOB 
JNZ POD14_4A 
• NOW WAIT FOR ENABLE TO GO OFF 



TEST 
LOOPE 
JCXZ 



AL,DX 

AL, 00000001 B 

P0D14_6 

P0D14_4B 



VERTICAL OFF? 
GO ON IF IT IS 
(ERROR IF NOT) 

GET STATUS 
; ENABLE OFF YET? 
: KEEP LOOKING IF NOT 
YET LOW 



• ENABLE HAS TOGGLED, BUMP COUNTER AND TEST FOR NEXT VERTICAL 



August!, 1984 



IBM Enhanced Graphics Adapter 113 



03C5 






03C5 


43 




03C6 


71 


04 


03C8 


A8 


08 


03CA 


7U 


D2 


03CC 






03CC 


BO 


00 


03CE 


E6 


43 


03D0 


3B 


5E 02 


03D3 


74 


04 


03D5 


B3 


05. 


03D7 


EB 


6F 


03D9 






03D9 


E4 


40 


03DB 


8A 


EO 


03DD 


90 




03DE 


E4 


40 


03E0 


86 


EO 


03E2 


90 




03E3 


90 




03EU 


3B 


46 04 


03E7 


7D 


04 


03E9 


B3 


06 


03EB 


EB 


5B 


03ED 






03ED 


3B 


46 06 


03 FO 


7E 


04 


03 F2 


B3 


07 


03 FU 


EB 


52 



03 F6 






03 F6 


B8 


09DB 


03 F9 


BB 


000 F 


03 FC 


B9 


0050 


03FF 


CD 


10 


0401 


EC 




0402 


52 




0403 


B2 


CO 


0405 


B4 


OF 


0407 


BO 


3F 


0409 


E8 


0D15 R 


040C 


B8 


000 F 


040F 


5A 




0410 






0410 


50 




0411 


52 




0412 


B2 


CO 


0414 


B4 


32 


0416 


E8 


0015 R 


0419 


5A 




041A 


58 




041B 


2B 


C9 


041D 






041 D 


EC 




041 E 


A8 


30 


0420 


75 


09 


0422 


E2 


F9 


0424 


B3 


10 


0426 


OA 


DC 


0428 


EB 


IE 90 


042B 






042B 


2B 


C9 


0420 






042D 


EC 




042E 


A8 


30 


0430 


74 


08 


0432 


E2 


F9 


0434 


B3 


20 


0436 


OA 


DC 


0438 


EB 


OE 


043A 






043A 


FE 


C4 


043C 


80 


FC 30 


043F 


74 


25 


0441 


80 


CC OF 


0444 


8A 


C4 


0446 


EB 


C8 


0448 






0448 


B9 


0006 


044B 


BA 


0103 


044E 


E8 


06C8 R 


0451 


83 


C4 OA 


0454 


BO 


36 


0456 


E6 


43 


0458 


2A 


CO 


045A 


E6 


40 


045C 


90 




0450 


90 




045E 


E6 


40 


0460 


BO 


0001 


0463 


E9 


0091 R 


0466 






0466 


E8 


OCFE R 


0469 


B8 


0500 


046C 


CD 


10 


046 E 


BO 


36 


0470 


E6 


43 


0472 


2A 


CO 


0474 


E6 


40 


0476 


90 




0477 


90 




0478 


E6 


40 


047A 


83 


C4 OA 


047D 


BD 


0000 


0480 






0480 






0480 


IE 





1261 


C 


P0D14. 


.7: 






1262 


C 




INC 


BX 




1263 


C 




JZ 


P0D14_75 




1264 


C 










1265 


C 




TEST 


AL, 00001 OOOB 




1266 


C 










1267 


C 




JZ 


POD14_3 




1268 


C 










1269 


C 




HAVE HAD COMPLETE VERTICAL-VERTICAL 


1270 


C 


P0D14. 


75: 






1271 


C 




MOV 


AL,00 




1272 


c 




OUT 


TIM CTL,AL 




1273 


c 




CMP 


BX,WORD PTR[BP][2] 




1274 


c 










1275 


c 




JE 


P0D14 8 




1276 


c 




MOV 


BL,05H 




1277 


c 




JMP 


SHORT P0D14_ERR 




1278 


c 


POD 14. 


8: 






1279 


c 




IN 


AL,TIMERO 




1280 


c 




MOV 


AH.AL 




1281 


c 




NOP 






1282 


c 




IN 


AL,T1MER0 




1283 


c 




XCHG 


AH.AL 




1284 


c 




NOP 






1285 


c 




NOP 






1286 


c 




CMP 


AX, WORD PTR[BP][4] 




1287 


c 




JGE 


P0D14 9 




1288 


c 




MOV 


BL,06H 




1289 


c 




JMP 


SHORT P0D14_ERR 




1290 


c 


POD 14. 


-9: 






1291 


c 




CMP 


AX, WORD PTR[BP][6] 




1292 


c 




JLE 


P0D14 10 




1293 


c 




MOV 


BL,07H 




1294 


c 




JMP 


SHORT P0D14_ERR 




1295 


c 










1296 


c 




-SEE IF 


RED, GREEN, BLUE AND 


NTENSI 


1297 


c 










1298 


c 




- FIRST, 


SET A LINE OF REVERSE 


VIDEO, 


1299 


c 


P0D14. 


.10: 






1300 


c 




MOV 


AX,09DBH 




1301 


c 




MOV 


BX,OOOFH 




1302 


c 










1303 


c 




MOV 


CX,80 




1304 


c 




INT 


10H 




1305 


c 




IN 


AL,DX 




1306 


c 




PUSH 


DX 




1307 


c 




MOV 


DL,ATTR WRITE 




1308 


c 




MOV 


AH,0FH 




1309 


c 




MOV 


AL,03FH 




1310 


c 




CALL 


OUT DX 




1311 


c 




MOV 


AX,OFH 




1312 


c 




POP 


DX 




1313 


c 


P0D14. 


13: 






1314 


c 




PUSH 


AX 




1315 


c 




PUSH 


DX 




1316 


c 




MOV 


DL,ATTR WRITE 




1317 


c 




MOV 


AH,32H 




1318 


c 




CALL 


OUT DX 




1319 


c 




POP 


DX 




1320 


c 




POP 


AX 




1321 


c 




SUB 


CX.CX 




1322 


c 




■ SEE IF 


DOT COMES ON 




1323 


c 


POD 14. 


14: 






1324 


c 




IN 


AL,DX 




1325 


c 




TEST 


AL,00110000B 




1326 


c 




JNZ 


P0D14 15 




1327 


c 




LOOP 


P0D14 14 




1328 


c 




MOV 


BL,10H 




1329 


c 




OR 


BL,AH 




1330 


c 




JMP 


P0D14 ERR 




1331 


c 




SEE IF 


DOT GOES OFF 




1332 


c 


POD! 4. 


.15: 






1333 


c 




SUB 


CX,CX 




1334 


c 


POD 14. 


.16: 






1335 


c 




IN 


AL, DX 




1336 


c 




TEST 


AL,00110000B 




1337 


c 




JE 


P0D14 17 




1338 


c 




LOOP 


P0D14_16 




1339 


c 










1340 


c 




MOV 


BL,20H 




1341 


c 




OR 


BL,AH 




1342 


c 




JMP 


SHORT P0D14_ERR 




1343 


c 










1344 


c 




ADJUST 


TO POINT TO NEXT DOT 




1345 


c 










1346 


c 


POD 14. 


17: 






1347 


c 




INC 


AH 




1348 


c 




CMP 


AH,030H 




1349 


c 




JE 


P0D14 18 




1350 


c 




OR 


AH,0FH 




1351 


c 




MOV 


AL,AH 




1352 


c 




JMP 


P0D14_13 




1353 


c 


P0D14. 


ERR: 






1354 


c 




MOV 


CX,6 




1355 


c 




MOV 


DX,0103H 




1356 


c 




CALL 


ERR BEEP 




1357 


c 




ADD 


SP,OAH 




1358 


c 




MOV 


AL,00110110B 




1359 


c 




OUT 


TIM CTL,AL 




1360 


c 




SUB 


AL,AL 




1361 


c 




OUT 


TIMERO,AL 




1362 


c 




NOP 






1363 


c 




NOP 






1364 


c 




OUT 


TIMERO,AL 




1365 


c 




MOV 


BP,1 




1366 


c 




JMP 


SKIP 




1367 


c 




ASSUME DS:ABSO 




1368 


c 


P0D14. 


18: 






1369 


c 




CALL 


DOS 




1370 


c 




MOV 


AX,0500H 




1371 


c 




INT 


lOH 




1372 


c 




MOV 


AL,00110110B 




1373 


c 




OUT 


TIM CTL.AL 




1374 


c 




SUB 


AL,AL 




1375 


c 




OUT 


TIMERO,AL 




1376 


c 




NOP 






1377 


c 




NOP 






1378 


c 




OUT 


TIMERO,AL 




1379 


c 




ADD 


SP,OAH 




1380 


c 




MOV 


BP,0 




1381 


c 


POD 14 




ENDP 




1382 


c 










1383 


c 




TEST STORAGE 




1384 


c 










1385 


c 


MEM_TEST: 






1386 


c 




PUSH 


DS 





; BUMP ENABLE COUNTER 

; IF COUNTER WRAPS, 
; SOMETHING IS WRONG 

; DID ENABLE GO LOW 
; BECAUSE OF VERTICAL 

; IF NOT, LOOK FOR ANOTHER 
; ENABLE TOGGLE 

CYCLE, NOW TEST RESULTS 

J LATCH TIMERO 



; GET TIMER HIGH 

; MAXIMUM VERTICAL TIMING 

; MINIMUM VERTICAL TIMING 

FY DOTS WORK 
INTENSIFIED BLANKS INTO BUFFER 



WRITE CHARS, BLANKS 
PAGE 0, REVERSE VIDEO, 

HIGH INTENSITY 
80 CHARACTERS 



SAVE INPUT STATUS 
ATTRIBUTE ADDRESSS 
PALETTE REG ' F' 
TEST VALUE 
VIDEO STATUS MUX 
START WITH BLUE DOTS 



; SAVE 

; SAVE INPUT STATUS 

; ATTRIBUTE ADDRESSS 

; COLOR PLANE ENABLE 

; VIDEO STATUS MUX 

; RECOVER INPUT STATUS 



GET STATUS 

DOT THERE? 

LOOK FOR DOT TO TURN OFF 

CONTINUE TEST FOR DOT ON 



; GET STATUS 

; IS DOT STILL ON? 

; GO ON IF DOT OFF 

; ELSE, KEEP WAITING FOR 

; DOT TO GO OFF 

; OR IN DOT BEING TESTED 



; ALL 3 DOTS DONE? 

; GO END 

; MAKE 0F,1F,2F 

; GO LOOK FOR ANOTHER DOT 



ONE LONG AND THREE SHORT 



SET TO VIDEO PAGE 
RE- I NIT TIMER 



114 IBM Enhanced Graphics Adapter 



At^^t 2, 1984 



0U81 E8 OCFE R 



0U8U 


F6 


06 0487 R 02 


0489 


74 


12 


0488 


80 


OE 0410 R 30 


0490 


B8 


OOOF 


0493 


80 


OE 0487 R 60 


0498 


B8 


OOOF 


0U9B 


EB 


OD 


049D 






049D 


80 


26 0410 R CF 


04A2 


80 


OE 0410 R 20 


04A7 


B8 


OOOE 


OUAA 






04AA 


CD 


10 


OUAC 


83 


EC 06 


04AF 


8B 


EC 


0UB1 


B8 


AOOO 


0UB4 


8E 


D8 


0UB6 


8E 


CO 


0UB8 


C7 


46 02 0000 


OUBD 


C7 


46 04 0000 


0UC2 


B6 


03 


04CU 


B2 


C4 


04C6 


B8 


0201 


04C9 


E8 


0D15 R 


04CC 


B2 


CE 


04CE 


88 


0400 


04D1 


E8 


0D15 R 


04DU 


52 




04D5 


B2 


DA 


04D7 


EC 




0UD8 


B2 


CO 


04DA 


B8 


3200 


04DD 


E8 


0D15 R 


04E0 


E8 


068F R 


04E3 


80 


FC 00 


0UE6 


74 


03 


0UE8 


E9 


05CD R 


04EB 






OUEB 


E8 


05D9 R 


04EE 


80 


FC 00 


oun 


74 


03 


04F3 


E9 


05CD R 


04 F6 






04 F6 


5A 




04F7 


B2 


C4 


04F9 


B8 


0202 


04FC 


E8 


0D15 R 


04FF 


B2 


CE 


0501 


B8 


0401 


0504 


E8 


0D15 R 


0507 


52 




0508 


B2 


DA 


050A 


EC 




050B 


B2 


CO 


050D 


B8 


3200 


0510 


E8 


0D15 R 


0513 


C7 


46 04 0000 


0518 


E8 


068F R 


051B 


80 


FC 00 


051E 


74 


03 


0520 


E9 


05CD R 


0523 






0523 


E8 


05D9 R 


0526 


80 


FC 00 


0529 


74 


03 


052B 


E9 


05CD R 


052E 






052E 


5A 




052F 


B2 


C4 


0531 


B8 


0204 


0534 


E8 


0D15 R 


0537 


52 




0538 


B2 


CE 


053A 


B8 


0402 


053D 


E8 


0D15 R 


0540 


B2 


DA 


0542 


EC 




0543 


82 


CO 


0545 


B8 


3200 


0548 


E8 


0D15 R 


054B 


C7 


46 04 0000 


0550 


E8 


068F R 


0553 


80 


FC 00 


0556 


74 


03 


0558 


EB 


73 90 


055B 






0556 


E8 


05D9 R 


055E 


80 


FC 00 


0561 


74 


03 


0563 


EB 


68 90 


0566 






0566 


5A 




0567 


B2 


C4 


0569 


B8 


0208 


056C 


E8 


0D15 R 


056F 


B2 


CE 


0571 


B8 


0403 


0574 


E8 


0D15 R 


0577 


52 




0578 


B2 


DA 


057A 


EC 




057B 


B2 


CO 


0570 


B8 


3200 


0580 


E8 


0D15 R 


0583 


C7 


46 04 0000 


0588 


E8 


068 F R 


058B 


80 


FC 00 


058E 


75 


3D 


0590 


E8 


05D9 R 


0593 


80 


FC 00 


0596 


75 


35 


0598 


55 




0599 


BD 


0000 


059C 






059C 


5E 




059D 


5A 




059E 


E8 


OCFE R 


05A1 


36: 


88 5C 02 


05A5 


B1 


06 


05A7 


D3 


EB 


05A9 


4B 




05AA 


B1 


05 



1387 
1388 
1389 
1390 
1391 
1392 
1393 
1394 
1395 
1396 
1397 
1398 
1399 
1400 
1401 
1402 
1403 
1404 
1405 
1406 
1407 
1408 
1409 
1410 
1411 
1412 
1413 



1418 
1419 
1420 
1421 
1422 
1423 
1424 
1425 
1426 
1427 
1428 
1429 
1430 
1431 
1432 
1433 
1434 
1435 
1436 
1437 
1438 
1439 
1440 
1441 
1442 
1443 
1444 
1445 
1446 
1447 
1448 
1449 
1450 
1451 
1452 
1453 
1454 
1455 
1456 
1457 
1458 
1459 
1460 
1461 
1462 
1463 
1464 
1465 
1466 
1467 
1468 
1469 
1470 
1471 
1472 
1473 
1474 
1475 
1476 
1477 
1478 
1479 
1480 
1481 
1482 
1483 
1484 
1485 
1486 
1487 
1488 
1489 
1490 
1491 
1492 
1493 
1494 
1495 
1496 
1497 
1498 
1499 
1500 
1501 
1502 
1503 
1504 
1505 
1506 
1507 
1508 
1509 
1510 
1511 
1512 



CALL 

ASSUME 

TEST 



D_C0L0R_M: 



C D_OUT_M: 



DOS 
DSrABSO 
INFO, 2 
D_COLOR_M 
EQUIP_LOW,030H 
AX,OFH 
INFO,060H 
AX,OFH 
SHORT D_OUT_M 

EQUIP_LOW,0CFH 
EQU I P_LOW, 020H 
AX.OEH 



INT 

SUB 

MOV 

MOV 

ASSUME 

MOV 

MOV 

MOV 

MOV 

MOV 

MOV 

MOV 

CALL 

MOV 

MOV 

CALL 

PUSH 

MOV 

IN 

MOV 

MOV 

CALL 

CALL 

CMP 



JZ 
JMP 



JMP 

POP 

MOV 

MOV 

CALL 

MOV 

MOV 

CALL 

PUSH 

MOV 

IN 

MOV 

MOV 

CALL 

MOV 

CALL 

CMP 

JZ 

JMP 



JMP 

POP 

MOV 

MOV 

CALL 

PUSH 

MOV 

MOV 

CALL 

MOV 

IN 

MOV 

MOV 

CALL 

MOV 

CALL 

CMP 

JZ 

JMP 



JMP 

POP 
MOV 
MOV 
CALL 
MOV 
MOV 
CALL 
PUSH 
MOV 
IN 
MOV 
MOV 
CALL 
MOV 
CALL 
CMP 
JNZ 
CALL 
CMP 
JNZ 
PUSH 
MOV 
1_EXIT: 
POP 
POP 
CALL 
ASSUME 
MOV 
MOV 
SHR 
DEC 
MOV 



AX,OAOOOH 

DS: NOTH I NO, ES: NOTHING 

OS, AX 

ES,AX 

WORD PTR[BP][21,0 

WORD PTR[BP][4],0 

DH,3 

DL, SEQ_ADDR 

AX, 0201 H 

0UT_DX 

DL,GRAPH_ADDR 

AX,0400H 

OUT_DX 

DX 

DL,ATTR_READ 

AL,DX 

DL,ATTR_WRITE 

AX, 3200H 

0UT_DX 

H0W_B I G 



EGA_MEM_ERROR 

MEMORY_OK 

AH.O 

AA2 

EGA_MEM_ERROR 

DX 

DL, SEQ_ADDR 

AX,0202H 

OUT_DX 

DL,GRAPH_ADDR 

AX, 0401 H 

OUT_DX 

DX 

DL,ATTR_READ 

AL,DX 

DL,ATTR_WRITE 

AX,3200H 

OUT_DX 

WORD PTR [BP][4I,0 

HOW_B I G 

AH,0 

AA3 

EGA_MEM_ERR0R 

MEMORY_OK 

AH,0 

AA4 

EGA_MEM_ERROR 



DL,SEC1_ADDR 

AX,0204H 

0UT_DX 

DX 

DL,GRAPH_ADDR 

AX,0402H 

OUT_DX 

DL,ATTR_READ 

AL, DX 

DL,ATTR_WRITE 

AX,3200H 

0UT_DX 

WORD PTR[BP][4],0 

HOW_B 1 G 

AH,0 

EGA_MEM_ERR0R 

MEMORY_OK 

AH,0 

AA6 

EGA_MEM_ERROR 

DX 

DL,SEQ_ADDR 

AX,0208H 

0UT_DX 

DL,GRAPH_ADDR 

AX,0403H 

OUT_DX 

DX 

DL,ATTR_READ 

AL,DX 

DL,ATTR_WRITE 

AX,3200H 

0UT_DX 

WORD PTR[BP1[4],0 

HOW_B I G 

AH,0 

EGA_MEM_ERROR 

MEMORY_OK 

AH.O 

EGA_MEM_ERROR 



DX 

DOS 

DS:ABSO 

BX,WORD PTR SS:[SI 

CL,06H 

BX,CL 

BX 

CL,05H 



RESERVE 3 WORDS ON STACK 

SET BP 

PUT BUFFER ADDRESS IN AX 

SET UP SEG REGS TO POINT 
TO BUFFER AREA 
INITIALIZE 
INITIALIZE 



ADDRESS READ MAP SELECT 

SET UP ATTRIBUTE 
ATTRIBUTE WRITE ADDRESS 

GO FIND AMOUNT OF MEMORY 
GO TEST IT 



ADDRESS OF READ MAP 



SET UP ATTRIBUTE 
ATTRIBUTE WRITE ADDRESS 



; GO TEST IT 



ADDRESS OF READ MAP 

SET UP ATTRIBUTE 
ATTRIBUTE WRITE ADDRESS 



ADDRESS OF READ MAP 



SET UP ATTRIBUTE 
ATTRIBUTE WRITE ADDRESS 



GO TEST IT 



; SET DATA SEGMENT 

; GET EGA MEMORY SIZE 
; DIVIDE BY 64 TO GET 
NUMBER OF 64KB BLOCKS 



August 2, 1984 



IBM Enhanced Graphics Adapter 115 



05AC 


D3 


E3 


05AE 


80 


E3 60 


05B1 


80 


26 0U87 R 9F 


05B6 


08 


IE 0487 R 


05BA 


80 


OE 0487 R 04 


05BF 


8A 


IE 0488 R 


05C3 


E8 


00F3 R 


05C6 


83 


C4 06 


05C9 


IF 




05CA 


E9 


0091 R 


05CD 






05CD 


BA 


0103 


05D0 


E8 


06C8 R 


05D3 


55 




05DU 


BD 


0001 


05D7 


EB 


C3 


05D9 






05D9 


BB 


AOOO 


05DC 


8E 


DB 


05DE 


8E 


C3 


05E0 


8B 


46 04 


05E3 


8A 


E8 


05E5 


2A 


C9 


05E7 


D1 


El 


05 E9 


E8 


05FB R 


05EC 


80 


FC 00 


05EF 


75 


09 


05F1 






05F1 


8B 


46 04 


05 Fit 


01 


46 02 


05F7 


B8 


0000 


05 FA 






05 FA 


C3 




05FB 







05FB 






05FB 


55 




05FC 


FC 




05FD 


2B 


FF 


05FF 


28 


CO 


0601 


E8 


OCFE R 


0604 


8B 


IE 0472 R 


0608 


81 


FB 1234 


060C 


8C 


02 


060E 


8E 


DA 


0610 


74 


62 


0612 


81 


FB 4321 


0616 


74 


50 


0618 






0618 


88 


05 


061A 


8A 


05 


061C 


32 


04 


061 E 


75 


40 


0620 


FE 


C4 


0622 


8A 


C4 


0624 


75 


F2 


0626 


8B 


E9 


0628 


B8 


AA55 


062B 


8B 


D8 


062D 


BA 


55AA 


0630 


F3/ AB 


0632 


4F 




0633 


4F 




0634 


FD 




0635 


8B 


F7 


0637 


8B 


CD 


0639 






0639 


AD 




063A 


33 


C3 


063C 


75 


22 


063E 


8B 


C2 


0640 


AB 




0641 


E2 


F6 


0643 


8B 


CD 


0645 


FC 




0646 


46 




0647 


46 




0648 


8B 


FE 


064A 






064A 


AD 




064B 


33 


C2 


0640 


75 


11 


064F 


AB 




0650 


E2 


F8 


0652 


FD 




0653 


4E 




0654 


4E 




0655 


8B 


CD 


0657 






0657 


AD 




0658 


OB 


CO 


065A 


75 


04 


065C 


E2 


F9 


065E 


EB 


11 


0660 






0660 


8B 


C8 


0662 


32 


E4 


0664 


OA 


ED 



1513 
1514 
1515 
1516 
1517 
1518 
1519 
1520 
1521 
1522 
1523 
1524 
1525 
1526 
1527 
1528 
1529 
1530 
1531 
1532 
1533 
1534 
1535 
1536 
1537 
1538 
1539 
1540 
1541 
1542 
1543 
1544 
1545 
1546 
1547 
1548 
1549 
1550 
1551 
1552 
1553 
1554 
1555 
1556 
1557 
1558 
1559 
1560 
1561 
1562 
1563 
1564 
1565 
1566 
1567 
1568 
1569 
1570 
1571 
1572 
1573 
1574 
1575 
1576 
1577 
1578 
1579 
1580 
1581 
1582 
1583 
1584 
1585 
1586 
1587 
1588 
1589 
1590 
1591 
1592 
1593 
1594 
1595 
1596 
1597 
1598 
1599 
1600 
1601 
1602 
1603 
1604 
1605 
1606 
1607 
1608 
1609 
1610 
1611 
1612 
1613 
1614 
1615 
1616 
1617 
1618 
1619 
1620 
1621 
1622 
1623 
1624 
1625 
1626 
1627 
1628 
1629 
1630 
1631 
1632 
1633 
1634 
1635 
1636 
1637 
1638 



SHL 


BX,CL 


AND 


BL,01100000B 


AND 


INFO.IOOIIIIIB 


OR 


INFO,BL 


OR 


INFO,00000100B 


MOV 


BL, INFO 3 


CALL 


MK ENV 


ADD 


SP,6 


POP 


DS 


JMP 


SKIP 


EGA MEM ERROR: 




~ "MOV 


DX,0103H 


CALL 


ERR BEEP 


PUSH 


BP ~ 


MOV 


BP,1 


JMP 


EGA MEM_EXIT 


. THIS ROUTINE FINDS AMOUNT 


MEMORY OK 


PROC NEAR 


MOV 


BX, OAOOOH 


MOV 


DS,BX 


MOV 


ES,BX 


MOV 


AX, WORD PTR[BP][4] 


MOV 


CH,AL 


SUB 


CL,CL 


SHL 


CX,1 


CALL 


PODSTG 


CMP 


AH,0 


JNZ 


MEMORY_OK_ERR 


MEMORY OK EX: 




MOV 


AX, WORD PTR[BP][4] 


ADD 


WORD PTR[BP][2],AX 


MOV 


AX,0 


MEMORY OK ERR: 




" RET 




MEMORY_OK 


ENDP 



ISOLATE BITS 5 AND 6 



04H SET 3XX ACTIVE 

RESTORE STACK 

GO TO END 

ONE LONG AND THREE SHORT 



SET COUNT FOR 32K WORDS 
SET AMOUNT OF BUFFER 

TO BE TESTED 
MULTIPLY BY TWO 



THIS ROUTINE PERFORMS A READ/WRITE TEST ON A BLOCK OF STORAGE 
(MAX. SIZE = 32KW). IF "WARM START", FILL BLOCK WITH 0000 AND 
RETURN. 
ON ENTRY: 

ES = ADDRESS OF STORAGE TO BE TESTED 

DS = ADDRESS OF STORAGE TO BE TESTED 

CX = WORD COUNT OF STORAGE BLOCK TO BE TESTED 
(MAX. = 8000H (32K WORDS)) 
ON EXIT: 

ZERO FLAG = OFF IF STORAGE ERROR 
AX,BX,CX,DX,DI,SI ARE ALL DESTROYED. 



PODSTG PROC 


NEAR 


PUSH 


BP 


CLD 




SUB 


DI,DI 


SUB 


AX, AX 


CALL 


DOS 


ASSUME 


DS:ABSO 


MOV 


BX,DS; RESET FLAG 


CMP 


BX, 1234H 


MOV 


DX,ES 


MOV 


DS,DX 


JE 


P0DSTG_5 


CMP 


BX,4321H 


JE 


P0DSTG_5 


PODSTG 1 : 




MOV 


[01], AL 


MOV 


AL,[DI] 


XOR 


AL,AH 


JNZ 


PODSTG ERRO 


INC 


AH 


MOV 


AL,AH 


JNZ 


P0DSTG_1 


MOV 


BP,CX 


MOV 


AX, 0AA55H 


MOV 


BX,AX 


MOV 


DX,055AAH 


REP 


STOSW 


DEC 


Dl 


DEC 


Dl 


STD 




MOV 


SI,DI 


MOV 


CX,BP 


PODSTG 2: 




LODSW 




XOR 


AX,BX 


JNZ 


PODSTG ERRO 


MOV 


AX,DX 


STOSW 




LOOP 


PODSTG 2 


MOV 


CX,BP 


CLD 




INC 


SI 


INC 


SI 


MOV 


DI,SI 


PODSTG 3: 




LODSW 




XOR 


AX,DX 


JNZ 


PODSTG_ERRO 


STOSW 




LOOP 


P0DSTG_3 


STD 




DEC 


SI 


DEC 


SI 


MOV 


CX,BP 


PODSTG 4: 




LODSW 




OR 


AX, AX 


JNZ 


PODSTG ERRO 


LOOP 


P0DSTG_4 


JMP 


SHORT P0DSTG_ERR2 


PODSTG ERRO: 




MOV 


CX,AX 


XOR 


AH, AH 



SET DIR TO INCREMENT 
SET D I =0000 REL TO START 

OF SEGMENT 
INITIAL DATA PATTERN FOR 

OO-FF TEST 



; WARM START? 



RESTORE DS 

GO DO FILL WITH 0000 

IF WARM START 
DCP WARM START? 
DO F I LL IF SO 

WRITE TEST DATA 
GET IT BACK 
COMPARE TO EXPECTED 
ERROR EXIT IF MISCOMPARE 
FORM NEW DATA PATTERN 

LOOP TILL ALL 256 DATA 

PATTERNS DONE 
SAVE WORD COUNT 
LOAD DATA PATTERN 

LOAD OTHER DATA PATTERN 
FILL WORDS FROM LOW TO 

HIGH WITH AAAA 
POINT TO LAST WORD 

WRITTEN 
SET DIR FLAG TO GO DOWN 
SET INDEX REGS. EQUAL 
RECOVER WORD COUNT 
GO FROM HIGH TO LOW 
GET WORD FROM MEMORY 
EQUAL WHAT S/B THERE? 
GO ERROR EXIT IF NOT 
GET 55 DATA PATTERN AND 

STORE IN LOG JUST READ 
LOOP TILL ALL BYTES DONE 
RECOVER WORD COUNT 
BACK TO INCREMENT 
ADJUST PTRS 



LOW TO HIGH DOING WORDS 

GET A WORD 

SHOULD COMPARE TO DX 

GO ERROR I F NOT 

WRITE 0000 BACK TO LOG 

JUST READ 
LOOP TILL DONE 

BACK TO DECREMENT 
ADJUST POINTER DOWN TO 
LAST WORD WRITTEN 



GET WORD COUNT 

GET WORD 
= TO 0000 
ERROR IF NOT 
LOOP TILL DONE 



SAVE BITS IN ERROR 
HIGH BYTE ERROR? 



116 IBM Enhanced Graphics Adapter 



August 2, 1984 



0666 


74 


02 


0668 


84 


01 


066A 






066A 


OA 


C9 


066C 


74 


03 


066 E 


80 


C4 02 


0671 






0671 


5D 




0672 


FC 




0673 


C3 




067U 






067U 


50 




0675 


52 




0676 


86 


03 


0678 


82 


C4 


067A 


88 


020 F 


0670 


E8 


0D15 R 


0680 


5A 




0681 


58 




0682 


F3/ AB 


068U 


E8 


OCFE R 


0687 


89 


IE 0472 


068B 


8E 


DA 


068D 


EB 


E2 


068 F 






068 F 






068 F 


8C 


DA 


0691 


28 


D8 


0693 






0693 


8E 


C2 


0695 


2B 


FF 


0697 


88 


AA55 


069A 


88 


C8 


069C 


26 


89 05 


069 F 


80 


OF 


06A1 


26 


8B 05 


06AU 


33 


CI 


06A6 


75 


14 


06A8 


B9 


2000 


06AB 


F3/ AB 


06AD 


81 


C2 0400 


06B1 


83 


C3 10 


06BU 


80 


FE 80 


06B7 


75 


DA 


06B9 


EB 


01 90 


06BC 






06BC 


80 


FE AO 


06BF 


74 


06 


06C1 






06C1 


01 


5E 04 


teen 


88 


0000 


06C7 






06C7 


C3 




06C8 







06C8 






06C8 


90 




06C9 


FA 




06CA 


IF 




06C8 


E8 


OCFE R 


06CE 


OA 


F6 


06D0 


74 


08 


06D2 






06D2 


83 


06 


06D4 


E8 


0D20 R 


06D7 






06D7 


E2 


FE 


06D9 


Ft 


CE 


06D8 


75 


F5 


06DD 






06DD 


m 


01 


06DF 


F« 


0D20 R 


06E2 






06E2 


F? 


FE 


06 E4 


FF 


CA 


06E6 


/b 


F5 


06 E8 






06 E8 


E2 


FE 


06 EA 






06 EA 


E2 


FE 


06 EC 


U 




06ED 


pn 




06EE 


03 




06EF 







06F1 
06 F3 
06 F5 



0703 
0705 
0707 
0709 
0708 
070D 
070F 



10EF R 
1157 R 
1186 R 



1C9F R 

1D01 R 

1D85 R 

1DC5 R 

1F98 R 

0713 208F R 

0715 2118 R 



1639 
1640 
1641 
1642 
1643 
1644 
1645 
1646 
1647 
1648 
1649 
1650 
1651 
1652 
1653 
1654 
1655 
1656 
1657 
1658 
1659 
1660 
1661 
1662 
1663 
1664 
1665 
1666 
1667 
1668 
1669 
1670 
1671 
1672 
1673 
1674 
1675 
1676 
1677 
1678 
1679 
1680 
1681 
1682 
1683 
1684 
1685 
1686 
1687 
1688 
1689 
1690 
1691 
1692 
1693 
1694 
1695 
1696 
1697 
1698 
1699 
1700 
1701 
1702 
1703 
1704 
1705 
1706 
1707 
1708 
1709 
1710 
1711 
1712 
1713 
1714 
1715 
1716 
1717 
1718 
1719 
1720 
1721 
1722 
1723 
1724 
1725 
1726 
1727 
1728 
1729 
1730 
1731 
1732 
1733 
1734 
1735 
1736 
1737 
1738 
1739 
1740 
1741 
1742 
1743 
1744 
1745 
1746 
1747 
1748 
1749 
1750 
1751 
1752 
1753 
1754 
1755 
1756 
1757 
1758 
1759 
1760 
1761 
1762 
1763 
1764 



JZ 


PODSTG ERR1 


MOV 


AH,1 


PODSTG ERR1: 




OR 


CL,CL 


JZ 


P0DSTG_ERR2 


ADD 


AH, 2 


PODSTG ERR2: 




POP 


BP 


OLD 




RET 




P0DSTG_5: 




PUSH 


AX 


PUSH 


DX 


MOV 


DH,3 


MOV 


DL.SEQ ADDR 


MOV 


AX,020FH 


CALL 


OUT DX 


POP 


DX 


POP 


AX 


REP 


STOSW 


CALL 


DOS 


ASSUME 


DS:ABSO 


MOV 


DS: RESET FLAG,BX 


MOV 


DS.DX 


JMP 


PODSTG ERR2 


PODSTG ENDP 




. DETERMINE SIZE OF BUFFER 


HOW BIG 


PROC NEAR 


MOV 


DX.DS 


SUB 


BX,BX 


FILL LOOP: 




MOV 


ES,DX 


SUB 


DI.DI 


MOV 


AX,0AA55H 


MOV 


OX, AX 


MOV 


ES:[DI],AX 


MOV 


AL.OFH 


MOV 


AX,ES:[DI ] 


XOR 


AX,CX 


JNZ 


HOW BIG END 


MOV 


CX,2000H 


REP STOSW 




ADD 


DX,0400H 


ADD 


BX, 16 


CMP 


DH,OBOH 


JNZ 


FILL LOOP 


JMP 


H0W_8IG_END 


HOW BIG END: 




CMP 


DH,OAOH 


JZ 


HB_ERROR_EXIT 


RESUME: 




ADD 


WORD PTR[BP1[4].BX 


MOV 


AX,0 


HB ERROR EXIT: 




RET 




HOW_B 1 G 


ENDP 



SET HIGH BYTE ERROR 
LOW BYTE ERROR? 



SET DIR FLAG BACK TO INC 

RETURN TO CALLER 

SIMPLE FILL WITH 0000 ON 

WARM- START 
SAVE 
SAVE VALUE 

SEq_ADDR REGISTER 



; SET SEG. REG 

; TEST PATTERN 

; SEND TO MEMORY 

; PUT SOMETHING IN AL 

; GET PATTERN FROM MEMORY 

; COMPARE PATTERNS 

; GO END IF NO COMPARE 

; SET COUNT FOR 8K WORDS 

; FILL 8K WORDS 

; POINT TO NEXT 16K BLOCK 

; BUMP COUNT BY 16KB 

; AREA YET ?(BOOOOH) 



1ST 16KB OK 



SAVE BUFFER FOUND 



SUBROUTINES FOR POWER ON DIAGNOSTICS 



THIS PROCEDURE WILL ISSUE ONE LONG TONE (3 
MORE SHORT TONES (1 SEC) TO INDICATE A FAf 
BOARD ,A BAD RAM MODULE, OR A PROBLEM WITH 
ENTRY REQUIREMENTS: 

DH=NUMBER OF LONG TONES TO BEEP 
DL=NUMBER OF SHORT TONES TO BEEP, 



SEC) AND ONE OR 
LURE ON THE PLANAR 
THE CRT. 



NEAR 



DDS 

DS:ABSO 

DH,DH 



PUSH 
CALL 
ASSUME 



LOOP 
DEC 
JNZ 



LOOP G4 
DEC DL 
JNZ G3 

LOOP G5 

LOOP G6 
POP DS 
POPF 
RET 
t_BEEP ENDP 



WORD 




OFFSET 


AHO 


OFFSET 


AH1 


OFFSET 


AH2 


OFFSET 


AH3 


OFFSET 


AH4 


OFFSET 


AH5 


OFFSET 


AH6 


OFFSET 


AH7 


OFFSET 


AH8 


OFFSET 


AH9 


OFFSET 


AHA 


OFFSET 


AH8 


OFFSET 


AHO 


OFFSET 


AHD 


OFFSET 


AHE 


OFFSET 


AHF 


OFFSET 


AH10 


OFFSET 


AH11 


OFFSET 


AH12 


OFFSET 


AMI 3 


$-T2 





ANY LONG TONES TO BEEP 
NO, DO THE SHORT ONES 
LONG BEEP 
COUNTER FOR BEEPS 
DO THE BEEP 

DELAY BETWEEN BEEPS 
ANY MORE TO DO 
DO IT 

COUNTER FOR A SHORT BEEP 



DELAY BETWEEN BEEPS 
DONE WITH SHORT BEEPS 
DO MORE 

DELAY BEFORE RETURN 



MODE SET 

SET CURSOR TYPE 

SET CURSOR POSITION 

READ CURSOR POSITION 

READ LIGHT PEN POSITION 

ACTIVE DISPLAY PAGE 

SCROLL DOWN 

SCROLL UP 

READ CHAR/ATTRIBUTE 

WRITE CHAR/ATTRIBUTE 

WRITE CHARACTER ONLY 

SET COLOR PALETTE 

WRITE DOT 

READ DOT 

WRITE TTY 

CURRENT VIDEO STATE 

SET PALETTE REGISTERS 

CHAR GENERATOR ROUTINE 

ALTERNATE SELECT 

WRITE STRING 



August 2, 1984 



IBM Enhanced Graphics Adapter 117 

















1765 
























1766 


C 




INCLUDE 


V PARMS. INC 
















1767 


C 




SUBTTL 


V PARMS. INC 
















1768 


C 




PAGE 




0717 














1769 


C VIDEO 


PARMS 


LABEL BYTE 
















1770 


C 






















1771 


C 


STRUCTURE OF 


THIS TABLE 
















1772 


C 






















1773 


C 




COLUMNS, ROWS, PELS PER CHARACTER 
















1774 


C 




PAGE LENGTH 
















1775 


C 




SEQUENCER PARAMETERS 
















1776 


c 




MISCELLANEOUS REGISTER 
















1777 


c 




CRTC PARAMETERS 
















1778 


c 




ATTRIBUTE PARAMETERS 
















1779 


c 




GRAPHICS PARAMETERS 
















1780 


c 








= 0000 












1781 


C BASE 


EQU 


$ - VIDEO PARMS 


0717 














1782 


C BASE 


_L 


LABEL BYTE 
















1783 


C 






















1784 


C 




DEFAULT 


MODES 
















1785 


C 






















1786 


C 


— 0- 






0717 


28 


18 


08 








1787 


c 




DB 


40D,24D,08D 


071A 


0800 










1788 


c 




DW 


00800H 
















1789 


c 








= 0005 












1790 


C TFS LEN EQU 


$ - BASE_1_L 
















1791 


C 








071C 














1792 


C SEQ FARMS 


LABEL BYTE 


071C 


OB 


03 


00 


03 






1793 


C 




DB 


00BH,003H,0OOH,003H 


= 0004 












1794 


C Ml 


EQU 


$ - SEQ_PARMS 
















1795 


C 








0720 


23 












1796 
1797 


C 
C 




DB 


023H 


0721 














1798 


C CRT PARMS 


LABEL BYTE 


0721 


37 


27 


2D 


37 


31 


15 


1799 


C 




DB 


037H,027H,02DH,037H,031H,015H 


0727 


OU 


11 


00 


07 


06 


07 


1800 


C 




DB 


004H,011H,OOOH,007H,006H,007H 


072D 


00 


00 


00 


00 


El 


24 


1801 


C 




DB 


OOOH, OOOH, OOOH, OOOH, 0E1 H, 024H 


0733 


C7 


14 


08 


EO 


FO 


A3 


1802 


C 




DB 


0C7H, 01 4H, 008H, OEOH, OFOH, 0A3H 


0739 


FF 












1803 


C 




DB 


OFFH 


= 0019 












1804 


C M4 


EQU 


$-CRT_PARMS 
















1805 


C 








= 0023 












1806 


C 


LN_4 


EQU 


$ - BASE_1_L 
















1807 


c 








073A 














1808 


C ATTR PARMS 


LABEL BYTE 


073A 


00 


01 


02 


03 


04 


05 


1809 


C 




DB 


OOOH, 001 H, 002H, 003H, 004H, 005H 


07U0 


06 


07 


10 


11 


12 


13 


1810 


C 




DB 


006H,007H,010H,011H,012H,013H 


0746 


14 


15 


16 


17 


08 


00 


1811 


C 




DB 


014H,015H,016H,017H,008H,000H 


074C 


OF 


00 










1812 


C 




DB 


00FH,000H 


= 001U 












1813 


C M5 


EQU 


$-ATTR_ PARMS 
















1814 


C 








= 0037 












1815 


C 


LN 2 


EQU 


$ - BASE_1_L 


07UE 














1816 


C GRAPH 


PARMS 


LABEL BYTE 


07UE 


00 


00 


00 


00 


00 


10 


1817 


C 




DB 


OOOH, OOOH, OOOH, OOOH, OOOH, 010H 


0754 


OE 


00 


FF 








1818 


C 




DB 


OOEH, OOOH, OFFH 


= 0009 












1819 


C M6 


EQU 


$-GRAPH_PARMS 
















1820 


C 








= OOUO 












1821 


C M_TBL_ 


_LEN 


EQU $ - BASE_1_L 
















1822 


C 






















1823 


c 








0757 


28 


18 


08 








1824 


c 




DB 


40D,24D,08D 


075A 


0800 










1825 


c 




DW 


00800H 
















1826 


c 








075C 


08 


03 


00 


03 






1827 
1828 


c 
c 




DB 


OOBH,0O3H,0OOH,O03H 


0760 


23 












1829 
1830 


c 
c 




DB 


023H 


0761 


37 


27 


20 


37 


31 


15 


1831 


c 




DB 


037H,027H,02DH,037H,031H,015H 


0767 


04 


11 


00 


07 


06 


07 


1832 


c 




DB 


004H, 01 1 H, OOOH, 007H, 006H, 007H 


076D 


00 


00 


00 


00 


El 


24 


1833 


c 




DB 


OOOH, OOOH, OOOH, OOOH, 0E1 H, 024H 


0773 


C7 


14 


06 


EO 


FO 


A3 


1834 


c 




DB 


0C7H, 01 4H,008H, OEOH, OFOH, 0A3H 


0779 


FF 












1835 
1836 


c 
c 




DB 


OFFH 


077A 


00 


01 


02 


03 


04 


05 


1837 


c 




DB 


OOOH, 001 H, 002H, 003H, 004H, 005H 


0780 


06 


07 


10 


11 


12 


13 


1838 


c 




DB 


006H,007H,010H,011H,012H,013H 


0786 


14 


15 


16 


17 


08 


00 


1839 


c 




DB 


014H,015H,016H,017H,008H,OOOH 


078C 


OF 


00 










1840 
1841 


c 
c 




DB 


OOFH,OOOH 


078E 


00 


00 


00 


00 


00 


10 


1842 


c 




DB 


OOOH, OOOH, OOOH, OOOH, OOOH, 010H 


0791 


OE 


00 


FF 








1843 
1844 
1845 


c 
c 
c 


— 2- 


DB 


OOEH, OOOH, OFFH 


0797 


50 


18 


08 








1846 


c 




DB 


80D,24D,08D 


079A 


1000 










1847 


c 




DW 


01000H 
















1848 


c 








079C 


01 


03 


00 


03 






1849 
1850 


c 
c 




DB 


001 H,003H, OOOH, 003H 


07A0 


23 












1851 
1852 


c 
c 




DB 


023H 


07A1 


70 


4F 


5C 


2F 


5F 


07 


1853 


c 




DB 


070H, 04FH, 05CH, 02FH, 05FH, 007H 


07A7 


04 


11 


00 


07 


06 


07 


1854 


c 




DB 


004H,011H,OOOH,007H,006H,007H 


07AD 


00 


00 


00 


00 


El 


24 


1855 


c 




DB 


OOOH, OOOH, OOOH, OOOH, 0E1 H, 024H 


07B3 


C7 


28 


08 


EO 


FO 


A3 


1856 


c 




DB 


0C7H, 028H, 008H, OEOH, OFOH, 0A3H 


07 B9 


FF 












1857 
1858 


c 
c 




DB 


OFFH 


07 BA 


00 


01 


02 


03 


04 


05 


1859 


c 




DB 


OOOH, 001 H, 002H, 003H, 004H. 005H 


07C0 


06 


07 


10 


11 


12 


13 


1860 


c 




DB 


006H,007H,010H,011H,012H,013H 


07C6 


14 


15 


16 


17 


08 


00 


1861 


c 




DB 


014H,015H,016H,017H,008H,000H 


07CC 


OF 


00 










1862 
1863 


c 
c 




DB 


OOFH,OOOH 


07CE 


00 


00 


00 


00 


00 


10 


1864 


c 




DB 


OOOH, OOOH, OOOH, OOOH, OOOH, 010H 


07DU 


OE 


00 


FF 








1865 
1866 
1867 


c 
c 
c 


-.3.. 


DB 


OOEH, OOOH, OFFH 


07D7 


50 


18 


08 








1868 


c 




DB 


80D,24D,08D 


07DA 


1000 










1869 


c 




DW 


01000H 
















1870 


c 








07DC 


01 


03 


00 


03 






1871 
1872 


c 
c 




DB 


OO1H,OO3H,OOOH,O03H 


07 EO 


23 












1873 
1874 


c 
c 




DB 


023H 


07E1 


70 


4F 


5C 


2F 


5F 


07 


1875 


c 




DB 


070H, 04FH, 05CH, 02FH, 05FH, 007H 


07E7 


04 


11 


00 


07 


06 


07 


1876 


c 




DB 


004H, 01 1 H, OOOH, 007H, 006H, 007H 


07ED 


00 


00 


00 


00 


El 


24 


1877 


c 




DB 


OOOH, OOOH, OOOH, OOOH, 0E1 H, 024H 


07F3 


C7 


28 


08 


EO 


FO 


A3 


1878 


c 




DB 


0C7H, 028H, 008H, OEOH, OFOH, 0A3H 


07F9 


FF 












1879 
1880 


c 
c 




DB 


OFFH 


07 FA 


00 


01 


02 


03 


04 


05 


1881 


c 




DB 


OOOH, 001 H, 002H, 003H, 004H, 005H 


0800 


06 


07 


10 


11 


12 


13 


1882 


c 




DB 


006H,007H,010H,011H,012H,013H 


0806 


14 


15 


16 


17 


08 


00 


1883 


c 




DB 


014H,015H,016H,017H,008H,000H 


080C 


OF 


00 










1884 
1885 


c 
c 




DB 


00FH,000H 


080E 


00 


00 


00 


00 


00 


10 


1886 


c 




DB 


OOOH, OOOH, OOOH, OOOH, OOOH, 010H 


081U 


OE 


00 


FF 








1887 
1888 
1889 


c 
c 
c 


_.4_. 


DB 


OOEH, OOOH, OFFH 


0817 


28 


18 


08 








1890 


c 




DB 


40D,24D,08D 



118 IBM Enhanced Graphics Adapter 



Ai^ust 2, 1984 



081A 


4000 










1891 
















1892 


081C 


OB 


03 


00 


02 






1893 
1894 


0820 


23 












1895 
1896 


0821 


37 


27 


20 


37 


30 


14 


1897 


0827 


04 


11 


00 


01 


00 


00 


1898 


082D 


00 


00 


00 


00 


El 


24 


1899 


0833 


C7 


14 


00 


EO 


FO 


A2 


1900 


0839 


FF 












1901 
1902 


083A 


00 


13 


15 


17 


02 


04 


1903 


08U0 


06 


07 


10 


11 


12 


13 


1904 


0846 


14 


15 


16 


17 


01 


00 


1905 


08UC 


03 


00 










1906 
1907 


08UE 


00 


00 


00 


00 


00 


30 


1908 


0854 


OF 


00 


FF 








1909 
1910 
1911 


0857 


28 


18 


08 








1912 


085A 


4000 










1913 
















1914 


085C 


OB 


03 


00 


02 






1915 
1916 


0860 


23 












1917 
1918 


0861 


37 


27 


2D 


37 


30 


14 


1919 


0867 


04 


11 


00 


01 


00 


00 


1920 


086D 


00 


00 


00 


00 


El 


24 


1921 


0873 


C7 


14 


00 


EO 


FO 


A2 


1922 


0879 


FF 












1923 
1924 


087A 


00 


13 


15 


17 


02 


04 


1925 


0880 


06 


07 


10 


11 


12 


13 


1926 


0886 


14 


15 


16 


17 


01 


00 


1927 


088C 


03 


00 










1928 
1929 


088E 


00 


00 


00 


00 


00 


30 


1930 


0894 


OF 


00 


FF 








1931 
1932 
1933 


0897 


50 


18 


08 








1934 


089A 


4000 










1935 
















1936 


089C 


01 


01 


00 


06 






1937 
1938 


08A0 


23 












1939 
1940 


08A1 


70 


4F 


59 


2D 


5E 


06 


1941 


08A7 


04 


11 


00 


01 


00 


00 


1942 


08AD 


00 


00 


00 


00 


EO 


23 


1943 


08B3 


C7 


28 


00 


V 


EF 


C2 


1944 


08B9 


FF 










1945 
















1946 


08BA 


00 


17 


17 


17 


17 


17 


1947 


08C0 


17 


17 


17 


17 


17 


17 


1948 


08C6 


17 


17 


17 


17 


01 


00 


1949 


08CC 


01 


00 










1950 
1951 


08CE 


00 


00 


00 


00 


00 


00 


1952 


0804 


OD 


00 


FF 








1953 
1954 
1955 


08D7 


50 


18 


OE 








1956 


08DA 


1000 










1957 
















1958 


08DC 


00 


03 


00 


03 






1959 
1960 


08 EO 


A6 












1961 
1962 


08E1 


60 


4F 


56 


3A 


51 


60 


1963 


08 E7 


70 


IF 


00 


OD 


OB 


OC 


1964 


08ED 


00 


00 


00 


00 


5E 


2E 


1965 


08F3 


50 


28 


OD 


5E 


6E 


A3 


1966 


08 F9 


FF 












1967 
1968 


08 FA 


00 


08 


08 


08 


08 


08 


1969 


0900 


08 


08 


10 


18 


18 


18 


1970 


0906 


18 


18 


18 


18 


OE 


00 


1971 


090C 


OF 


08 










1972 
1973 


090E 


00 


00 


00 


00 


00 


10 


1974 


0914 


OA 


00 


FF 








1975 
1976 
1977 


0917 


28 


18 


08 








1978 


091A 


4000 










1979 
















1980 


091C 


00 


00 


00 


03 






1981 
1982 


0920 


23 












1983 
1984 


0921 


37 


27 


2D 


37 


31 


15 


1985 


0927 


04 


11 


00 


07 


06 


07 


1986 


092D 


00 


00 


00 


00 


El 


24 


1987 


0933 


C7 


14 


08 


EO 


FO 


A3 


1988 


0939 


FF 












1989 
1990 


093A 


00 


01 


02 


03 


04 


05 


1991 


0940 


06 


07 


10 


11 


12 


13 


1992 


0946 


14 


15 


16 


17 


08 


00 


1993 


094C 


OF 


00 










1994 
1995 


094E 


00 


00 


00 


00 


00 


10 


1996 


0954 


OE 


00 


FF 








1997 
1998 
1999 


0957 


28 


18 


08 








2000 


095A 


4000 










2001 
















2002 


095C 


00 


00 


00 


03 






2003 
2004 


0960 


23 












2005 
2006 


0961 


37 


27 


2D 


37 


31 


15 


2007 


0967 


04 


11 


00 


07 


06 


07 


2008 


096D 


00 


00 


00 


00 


El 


24 


2009 


0973 


C7 


14 


08 


EO 


FO 


A3 


2010 


0979 


FF 












2011 
2012 


097A 


00 


01 


02 


03 


04 


05 


2013 


0980 


06 


07 


10 


11 


12 


13 


2014 


0986 


14 


15 


16 


17 


08 


00 


2015 


098C 


OF 


00 










2016 



OOBH, 003H, OOOH, 002H 

023H 

037H,027H,02DH,037H,030H,014H 
004H, 01 1 H, OOOH, 001 H, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, 0E1 H, 024H 
0C7H, 014H, OOOH, OEOH, OFOH, 0A2H 
OFFH 

OOOH,013H,015H,017H,002H,004H 
006H,007H,010H,011H,012H,013H 
014H,015H,016H,017H,0O1H,O0OH 
003H,000H 



OOBH, 003H, OOOH, 002H 

023H 

037H,027H,02DH,037H,030H,014H 
004H, 01 1H, OOOH, 001 H, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, 0E1 H, 024H 
0C7H, 014H, OOOH, OEOH, OFOH, 0A2H 
OFFH 

OOOH,013H,015H,017H,002H,004H 
006H,007H,010H,011H,012H,013H 
014H,015H,016H,017H,001H,OOOH 
003H,OOOH 



001H,001H,OOOH,006H 

023H 

070H, 04FH, 059H, 02DH, 05EH, 006H 
004H, 01 1H, OOOH, 001 H, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, OEOH, 023H 
0C7H, 028H, OOOH, ODFH, OEFH, 0C2H 
OFFH 

000H,017H,017H,017H,017H,017H 
017H,017H,017H,017H,017H,017H 
017H,017H,017H,017H,001H,OOOH 
001 H, OOOH 



OOOH, 003H, OOOH, 003H 

0A6H 

060H, 04FH, 056H, 03AH, 051 H, 060H 
070H, 01 FH, OOOH, OODH, OOBH, OOCH 
OOOH, OOOH, OOOH, OOOH, 05EH, 02EH 
05DH, 028H, OODH, 05EH, 06EH, 0A3H 
OFFH 

000H,008H,008H,008H,008H,008H 
008H,008H,010H,018H,018H,018H 
018H,018H,018H,018H,00EH,000H 
00FH,008H 



OOOH, OOOH, OOOH, 003H 

023H 

037H,027H,02DH,037H,031H,015H 
004H,011H,OOOH,007H,006H,007H 
OOOH, OOOH, OOOH, OOOH, 0E1H,024H 
0C7H, 01 4H, OOBH, OEOH, OFOH, 0A3H 
OFFH 

OOOH, 001 H,002H,003H,004H,005H 
006H,007H,010H,OnH,012H,013H 
014H,015H,016H,017H,008H,OOOH 
OOFH,0O0H 



OOOH, OOOH, OOOH, 003H 

023H 

037H,027H,02DH,037H,031H,015H 
004H,011H,OOOH,007H,006H,007H 
OOOH, OOOH, OOOH, OOOH, 0E1 H, 024H 
OC7H,014H,008H, OEOH, OFOH, 0A3H 
OFFH 

OOOH, 001 H,002H,003H,004H,005H 
006H,007H,010H,011H,012H,013H 
01 4H, 01 5H, 016H, 01 7H, 008H, OOOH 
00 FH, OOOH 



August 2, 1984 



IBM Enhanced Graphics Adapter 119 

















2017 


098 E 


00 


00 


00 


00 


00 


10 


2018 


0994 


OE 


00 


FF 








2019 
2020 
2021 


0997 


28 


18 


08 








2022 


099A 


4000 










2023 
















2024 


099C 


00 


00 


00 


03 






2025 
2026 


09A0 


23 












2027 
2028 


09A1 


37 


27 


2D 


37 


31 


15 


2029 


09A7 


04 


11 


00 


07 


06 


07 


2030 


09AD 


00 


00 


00 


00 


El 


24 


2031 


09B3 


C7 


14 


08 


EO 


FO 


A3 


2032 


09 B9 


FF 












2033 
2034 


09BA 


00 


01 


02 


03 


04 


05 


2035 


09C0 


06 


07 


10 


11 


12 


13 


2036 


09C6 


14 


15 


16 


17 


08 


00 


2037 


09CC 


OF 


00 










2038 
2039 


09CE 


00 


00 


00 


00 


00 


10 


2040 


09DU 


OE 


00 


FF 








2041 
2042 
2043 


09D7 


50 


18 


08 








2044 


09DA 


1000 










2045 
















2046 


09DC 


01 


04 


00 


07 






2047 
2048 


09 EG 


23 












2049 
2050 


09E1 


70 


4F 


5C 


2F 


5F 


07 


2051 


09E7 


04 


11 


00 


07 


06 


07 


2052 


09ED 


00 


00 


00 


00 


El 


24 


2053 


09F3 


C7 


28 


08 


EO 


FO 


A3 


2054 


09F9 


FF 












2055 
2056 


09 FA 


00 


00 


00 


00 


00 


00 


2057 


OAOO 


00 


00 


00 


00 


00 


00 


2058 


0A06 


00 


00 


00 


00 


00 


00 


2059 


OAOC 


OF 


00 










2060 
2061 


OAOE 


00 


00 


00 


00 


00 


00 


2062 


OAIU 


04 


00 


FF 








2063 
2064 


0A17 


50 


18 


OE 








2065 


0A1A 


1000 










2066 
















2067 


0A1C 


00 


04 


00 


07 






2068 
2069 


0A20 


A6 












2070 
2071 


0A21 


60 


4F 


56 


3A 


51 


60 


2072 


0A27 


70 


IF 


00 


OD 


OB 


OC 


2073 


0A2D 


00 


00 


00 


00 


5E 


2E 


2074 


OA33 


5D 


28 


OD 


5E 


6E 


A3 


2075 


0A39 


FF 












2076 
2077 


0A3A 


00 


00 


00 


00 


00 


00 


2078 


OAUO 


00 


00 


00 


00 


00 


00 


2079 


0AU6 


00 


00 


00 


00 


OE 


00 


2080 


OAUC 


OF 


08 










2081 
2082 


0A4E 


00 


00 


00 


00 


00 


00 


2083 


0A5U 


04 


00 


FF 








2084 
2085 


0A57 


28 


18 


08 








2086 


0A5A 


2000 










2087 
















2088 


0A5C 


OB 


OF 


00 


06 






2089 
2090 


0A60 


23 












2091 
2092 


0A61 


37 


27 


20 


37 


30 


14 


2093 


0A67 


04 


11 


00 


00 


00 


00 


2094 


0A6D 


00 


00 


00 


00 


El 


24 


2095 


0A73 


C7 


14 


00 


EO 


FO 


E3 


2096 


0A79 


FF 












2097 
2098 


0A7A 


00 


01 


02 


03 


04 


05 


2099 


0A80 


06 


07 


10 


11 


12 


13 


2100 


0A86 


14 


15 


16 


17 


01 


00 


2101 


0A8C 


OF 


00 










2102 
2103 


0A8E 


00 


00 


00 


00 


00 


00 


2104 


0A9^ 


05 


OF 


FF 








2105 
2106 


0A97 


50 


18 


08 








2107 


0A9A 


4000 










2108 
















2109 


0A9C 


01 


OF 


00 


06 






2110 
2111 


OAAO 


23 












2112 
2113 


0AA1 


70 


4F 


59 


2D 


5E 


06 


2114 


0AA7 


04 


11 


00 


00 


00 


00 


2115 


OAAD 


00 


00 


00 


00 


EO 


23 


2116 


0AB3 


C7 


28 


00 


DF 


EF 


E3 


2117 


0AB9 


FF 












2118 
2119 


OABA 


00 


01 


02 


03 


04 


05 


2120 


OACO 


06 


07 


10 


11 


12 


13 


2121 


0AC6 


14 


15 


16 


17 


01 


00 


2122 


OACC 


OF 


00 










2123 
2124 


OACE 


00 


00 


00 


00 


00 


00 


2125 


OADU 


05 


OF 


FF 








2126 
2127 


0AD7 


50 


18 


OE 








2128 


OADA 


8000 










2129 
















2130 


OADC 


05 


OF 


00 


00 






2131 
2132 


OAEO 


A2 












2133 
2134 


0AE1 


60 


4F 


56 


1A 


50 


EO 


2135 


0AE7 


70 


IF 


00 


00 


00 


00 


2136 


OAED 


00 


00 


00 


00 


5E 


2E 


2137 


0AF3 


5D 


14 


OD 


5E 


6E 


8B 


2138 


0AF9 


FF 












2139 
2140 


OAFA 


00 


08 


00 


00 


18 


18 


2141 


OBOO 


00 


00 


00 


08 


00 


00 


2142 



OOOH, OOOH, OOOH, 003H 

023H 

037H,027H,02DH,037H,031H,015H 
004H, 01 1 H, OOOH, 007H, 006H, 007H 
OOOH, OOOH, OOOH, OOOH, 0E1 H, 024H 
0C7H, 014H, 008H, OEOH, OFOH, 0A3H 
OFFH 

OOOH, 001 H, 002H, 003H, 004H, 005H 
006H,007H,010H,011H,012H,013H 
014H,015H,016H,017H,008H,000H 
OOFH,OOOH 



001 H,004H, OOOH, 007H 

023H 

070H, 04FH, 05CH, 02FH, 05FH, 007H 
004H, 01 1 H, OOOH, 007H, 006H, 007H 
OOOH, OOOH, OOOH, OOOH, 0E1 H, 024H 
0C7H, 028H, 008H, OEOH, OFOH, 0A3H 
OFFH 

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH 
OOFH,OOOH 



OOOH, 004H, OOOH, 007H 

0A6H 

060H, 04FH, 056H, 03AH, 051 H, 060H 
070H, 01 FH, OOOH, OODH, OOBH, OOCH 
OOOH, OOOH, OOOH, OOOH, 05EH, 02EH 
05DH, 028H, OODH, 05EH, 06EH, 0A3H 
OFFH 

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, OOEH, OOOH 
00FH,008H 



OOBH, 00 FH, OOOH, 006H 

023H 

037H,027H,02DH,037H,030H,014H 
004H, 01 1 H, OOOH, OOOH, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, 0E1 H, 024H 
0C7H, 01 4H, OOOH, OEOH, OFOH, 0E3H 
OFFH 

OOOH, 001 H,002H,003H,004H,005H 
006H,007H,010H,011H,012H,013H 
014H,015H,016H,017H,001H,OOOH 
00 FH, OOOH 



001H,00FH,000H,006H 

023H 

070H, 04FH, 059H, 02DH, 05EH, 006H 
004H, 01 1 H, OOOH, OOOH, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, OEOH, 023H 
0C7H, 028H, OOOH, ODFH, OEFH, 0E3H 
OFFH 

OOOH, 001 H,002H,003H,004H,005H 
006H,007H,010H,011H,012H,013H 
014H,015H,016H,017H, 001 H, OOOH 
OOFH,OOOH 



005H,00FH, OOOH, OOOH 

0A2H 

060H,04FH,056H,01AH,050H,OEOH 
070H, 01 FH, OOOH, OOOH, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, 05EH, 02EH 
05DH,014H,OODH,05EH,06EH,08BH 
OFFH 



120 IBM Enhanced Grapbdcs Adapter 



August 2, 1984 



0B06 


00 


18 


00 


00 


OB 


00 


2143 


OBOC 


05 


00 










2144 
2145 


OBOE 


00 


00 


00 


00 


00 


10 


2146 


OBH» 


07 


OF 


FF 








2147 
2148 


0B17 


50 


18 


OE 








2149 


0B1A 


8000 










2150 
















2151 


0B1C 


05 


OF 


00 


00 






2152 
2153 


0B20 


A7 












2154 
2155 


0B21 


5B 


4F 


53 


17 


50 


BA 


2156 


0B27 


6C 


IF 


00 


00 


00 


00 


2157 


0B2D 


00 


00 


00 


00 


5E 


2B 


2158 


0B33 


5D 


14 


OF 


5F 


OA 


8B 


2159 


0B39 


FF 












2160 
2161 


0B3A 


00 


01 


00 


00 


04 


07 


2162 


0B40 


00 


00 


00 


01 


00 


00 


2163 


0BU6 


04 


07 


00 


00 


01 


00 


2164 


OBUC 


05 


00 










2165 
2166 


OBUE 


00 


00 


00 


00 


00 


10 


2167 


0B5U 


07 


OF 


FF 








2168 
2169 


= 04U0 












2170 
















2171 
















2172 
















2173 
















2174 


0B57 


50 


18 


OE 








2175 


0B5A 


8000 










2176 
















2177 


0B5C 


01 


OF 


00 


06 






2178 
2179 


0B60 


A2 












2180 
2181 


0B61 


60 


4F 


56 


3A 


50 


60 


2182 


0B67 


70 


IF 


00 


00 


00 


00 


2183 


0B6D 


00 


00 


00 


00 


5E 


2E 


2184 


0B73 


50 


28 


OD 


5E 


6E 


E3 


2185 


0B79 


FF 












2186 
2187 


0B7A 


00 


08 


00 


00 


18 


18 


2188 


0B80 


00 


00 


00 


08 


00 


00 


2189 


0B86 


00 


18 


00 


00 


OB 


00 


2190 


0B8C 


05 


00 










2191 
2192 


0B8E 


00 


00 


00 


00 


00 


00 


2193 


0B9U 


05 


OF 


FF 








2194 
2195 
2196 


0B97 


50 


18 


OE 








2197 


0B9A 


8000 










2198 
















2199 


0B9C 


01 


OF 


00 


06 






2200 
2201 


OBAO 


A7 












2202 
2203 


0BA1 


58 


4F 


53 


37 


52 


00 


2204 


0BA7 


6C 


IF 


00 


00 


00 


00 


2205 


OBAD 


00 


00 


00 


00 


5E 


2B 


2206 


0BB3 


5D 


28 


OF 


5F 


OA 


E3 


2207 


0BB9 


FF 












2208 
2209 


OBBA 


00 


01 


02 


03 


04 


05 


2210 


OBCO 


14 


07 


38 


39 


3A 


3B 


2211 


0BC6 


3C 


3D 


3E 


3F 


01 


00 


2212 


OBCC 


OF 


00 










2213 
2214 


OBCE 


00 


00 


00 


00 


00 


00 


2215 


OBDU 


05 


OF 


FF 








2216 
2217 
2218 


= OUCO 












2219 
















2220 
















2221 
















2222 
















2223 


0BD7 


28 


18 


OE 








2224 


OBDA 


0800 










2225 
















2226 


OBDC 


OB 


03 


00 


03 






2227 
2228 


OBEO 


A7 












2229 
2230 


0BE1 


20 


27 


2B 


2D 


28 


60 


2231 


0BE7 


6C 


IF 


00 


OD 


06 


07 


2232 


OBED 


00 


00 


00 


00 


5E 


2B 


2233 


0BF3 


50 


14 


OF 


5E 


OA 


A3 


2234 


0BF9 


FF 












2235 
2236 


OBFA 


00 


01 


02 


03 


04 


05 


2237 


OCOO 


14 


07 


38 


39 


3A 


3B 


2238 


0C06 


3C 


3D 


3E 


3F 


08 


00 


2239 


OCOC 


OF 


00 










2240 
2241 


OCOE 


00 


00 


00 


00 


00 


10 


2242 


OCHt 


OE 


00 


FF 








2243 
2244 
2245 


0C17 


28 


18 


OE 








2246 


0C1A 


0800 










2247 
















2248 


0C1C 


OB 


03 


00 


03 






2249 
2250 


0C20 


A7 












2251 
2252 


0C21 


20 


27 


2B 


2D 


28 


6D 


2253 


0C27 


6C 


IF 


00 


OD 


06 


07 


2254 


0C2D 


00 


00 


00 


00 


5E 


2B 


2255 


0C33 


50 


14 


OF 


5E 


OA 


A3 


2256 


0C39 


FF 












2257 
2258 


0C3A 


00 


01 


02 


03 


04 


05 


2259 


0C40 


14 


07 


38 


39 


3A 


3B 


2260 


0C46 


3C 


3D 


3E 


3F 


08 


00 


2261 


OCUC 


OF 


00 










2262 
2263 


0C4E 


00 


00 


00 


00 


00 


10 


2264 


0C54 


OE 


00 


FF 








2265 
2266 
2267 


0C57 


50 


18 


OE 








2268 



005H, OOFH, OOOH, OOOH 

0A7H 

05BH,04FH,053H,017H,050H,0BAH 
06CH, 01 FH, OOOH, OOOH, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, 05EH, 02BH 
05DH, 01 4H, OOFH, 05FH, OOAH, 08BH 
OFFH 

OOOH, 001 H, OOOH, OOOH, 004H, 007H 
OOOH, OOOH, OOOH, 001 H, OOOH, OOOH 
004H, 007H, OOOH, OOOH, 001 H, OOOH 
005H,000H 



BASE_2 EQU $ - VIDE0_PARMS 
; > 16K MODE VALUES 



001H, OOFH, OOOH, 006H 



0A2H 

060H, 04FH, 056H, 03AH, 050H, 060H 
070H, 01 FH, OOOH, OOOH, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, 05EH. 02EH 
05DH, 028H, OOOH, 05EH, 06EH, 0E3H 
OFFH 

OOOH, 008H, OOOH, OOOH, 018H,018H 
OOOH, OOOH, OOOH, 008H, OOOH, OOOH 
OOOH, 01 8H, OOOH, OOOH, OOBH, OOOH 
005H,000H 



001 H, OOFH, OOOH, 006H 

0A7H 

05BH, 04FH, 053H, 037H, 052H, OOOH 
06CH, 01 FH, OOOH, OOOH, OOOH, OOOH 
OOOH, OOOH, OOOH, OOOH, 05EH, 02BH 
05DH, 028H, OOFH, 05FH, OOAH, 0E3H 
OFFH 

OOOH, 001 H, 002H, 003H, 004H, 005H 
014H,007H,038H,039H,03AH,03BH 
03CH,03DH,03EH,03FH, 001 H, OOOH 
OOFH, OOOH 



BASE_3 EQU $ - VIDEO_PARMS 
; HI RES ALTERNATE VALUES 



OOBH,003H,OOOH,003H 



0A7H 

02DH,027H,02BH,02DH,028H,06DH 
06CH, 01 FH, OOOH, OODH, 006H, 007H 
OOOH, OOOH, OOOH, OOOH, 05EH,02BH 
05DH, 014H, OOFH, 05EH, OOAH, 0A3H 
OFFH 

OOOH, 001 H, 002H, 003H, 004H, 005H 
014H,007H,038H,039H,03AH,03BH 
O3CH,O3DH,O3EH,O3FH,OO8H,OO0H 
OOFH, OOOH 



OOBH, 003H, OOOH, 003H 

0A7H 

02DH, 027H. 02BH, 02DH, 028H, 06DH 
06CH, 01 FH, OOOH, OODH, 006H, 007H 
OOOH, OOOH, OOOH, OOOH, 05EH, 02BH 
05DH, 014H, OOFH, 05EH, OOAH, 0A3H 
OFFH 

OOOH, 001 H, 002H, 003H, 004H, 005H 
014H,007H,038H,039H,03AH,03BH 
03CH,03DH,03EH,03FH, OOBH, OOOH 
OOFH, OOOH 



August!, 1984 



IBM Enhanced Graphics Adapter 121 



0C5A 


1000 










2269 
















2270 


0C5C 


01 


03 


00 


03 






2271 
2272 


0C60 


A7 












2273 
2274 


0C61 


5B 


UF 


53 


37 


51 


58 


2275 


0C67 


6C 


IF 


00 


OD 


06 


07 


2276 


0C6D 


00 


00 


00 


00 


5E 


2B 


2277 


0C73 


50 


28 


OF 


5E 


OA 


A3 


2278 


0C79 


FF 












2279 
2280 


0C7A 


00 


01 


02 


03 


04 


05 


2281 


0C80 


14 


07 


38 


39 


3A 


3B 


2282 


0C86 


3C 


3D 


3E 


3F 


08 


00 


2283 


0C8C 


OF 


00 










2284 
2285 


0C8E 


00 


00 


00 


00 


00 


10 


2286 


0C94 


OE 


00 


FF 








2287 
2288 
2289 


0C97 


50 


18 


OE 








2290 


0C9A 


1000 










2291 
















2292 


0C9C 


01 


03 


00 


03 






2293 
2294 


OCAO 


A7 












2295 
2296 


0CA1 


58 


UF 


53 


37 


51 


5B 


2297 


0CA7 


6C 


IF 


00 


OD 


06 


07 


2298 


OCAD 


00 


00 


00 


00 


5E 


28 


2299 


0CB3 


50 


28 


OF 


5E 


OA 


A3 


2300 


0CB9 


FF 












2301 
2302 


OCBA 


00 


01 


02 


03 


04 


05 


2303 


OCCO 


1U 


07 


38 


39 


3A 


38 


2304 


0CC6 


3C 


3D 


3E 


3F 


08 


00 


2305 


OCCC 


OF 


00 










2306 
2307 


OCCE 


00 


00 


ao 


00 


00 


10 


2308 


OCDU 


OE 


00 


FF 








2309 
2310 
2311 
2312 
2313 
2314 
2315 


0CD7 














2316 


0CD7 


FB 












2317 


0CD8 


FC 












2318 


0CD9 


55 












2319 


OCDA 


06 












2320 


OCDB 


IE 












2321 


OCDC 


52 












2322 


OCDD 


51 












2323 


OCDE 


53 












2324 


OCDF 


56 












2325 


OCEO 


57 












2326 
2327 


0CE1 


50 












2328 


0CE2 


8A 


C4 










2329 


OCEU 


32 


EU 










2330 


0CE6 


01 


EO 










2331 


0CE8 


8B 


FO 










2332 


OCEA 


3D 


0028 








2333 


OCED 


72 


06 










2334 


OCEF 


58 












2335 


OCFO 


CD 


42 










2336 


0CF2 


E9 


219E R 






2337 


0CF5 














2338 
2339 


0CF5 


E8 


OCFE R 






2340 


0CF8 


58 












2341 


0CF9 


2E 


FF A4 06EF 


R 


2342 
















2343 
















2344 
















2345 
















2346 
















2347 


OCFE 














2348 


OCFE 


50 












2349 


OCFF 


2B 


CO 










2350 


0D01 


8E 


D8 










2351 


0D03 


58 












2352 


ODCt 


C3 












2353 


0D05 














2354 
2355 


0D05 














2356 
2357 


0D05 


IE 












2358 


0D06 


E8 


OCFE R 






2359 


0D09 


8B 


16 


0463 R 




2360 


ODOD 


80 


E2 


FO 








2361 


0D10 


80 


CA 


OA 








2362 


0D13 


IF 












2363 


0D1U 


C3 












2364 


0D15 














2365 
2366 


0D15 














2367 


0D15 


86 


CU 










2368 


0D17 


EE 












2369 


0D18 


42 












2370 


0D19 


86 


C4 










2371 


0D1B 


EE 












2372 


0D1C 


«tA 












2373 


0D1D 


C3 












2374 


001 E 














2375 
2376 
2377 
23 78 


001 E 














2379 


0D1E 


EE 












2380 


001 F 


C3 












2381 


0020 














2382 
2383 


0020 














2384 


0020 


52 












2385 


0021 


BA 


0043 








2386 


0D2U 


80 


B6 










2387 


0026 


E8 


0D1E R 






2388 


0029 


B8 


0533 








2389 


0D2C 


UA 












2390 


0D2D 


E8 


001 E R 






2391 


0030 


8A 


C4 










2392 


0032 


E8 


0D1E R 






2393 


0D35 


BA 


0061 








2394 



01000H 

001H,003H,000H,003H 

0A7H 

05BH,04FH,053H,037H,051H,05BH 
06CH, 01 FH, OOOH, ODDH, 006H, 007H 
OOOH, OOOH, OOOH, OOOH, 05EH. 028H 
05DH, 028H, OOFH, 05EH, OOAH, 0A3H 
OFFH 

OOOH, 001 H, 002H, 003H, 004H, 005H 
014H,007H,038H,039H,03AH,03BH 
03CH, 03DH, 03EH, 03 FH, 008H, OOOH 
OOFH, OOOH 



O01H,OO3H,O0OH,0O3H 

0A7H 

05BH,04FH,053H,037H,051H,05BH 
06CH, 01 FH, OOOH, OODH, 006H, 007H 
OOOH, OOOH, OOOH, OOOH, 05EH, 02BH 
05DH,028H, OOFH, 05EH, OOAH, 0A3H 
OFFH 

OOOH, 001 H, 002H, 003H, 004H, 005H 
01 4H, 007H, 038H, 039H, 03AH, 03BH 
03CH, 03DH, 03EH, 03FH, 008H, OOOH 
OOFH, OOOH 



■ VECTOR INTO <AH> SPECIFIED FUNCTION 



COMBO_VIDEO 



CLD 




PUSH 


BP 


PUSH 


ES 


PUSH 


OS 


PUSH 


DX 


PUSH 


CX 


PUSH 


BX 


PUSH 


SI 


PUSH 


01 


PUSH 


AX 


MOV 


AL,AH 


XOR 


AH, AH 


SAL 


AX, 1 


MOV 


SI, AX 


CMP 


AX,T2L 


JB 


M2 


POP 


AX 


INT 


42H 


JMP 


V_RET 


ASSUME 


DS:ABSO 


CALL 


DOS 


POP 


AX 


JMP 


WORD PTF 



■ OFFSET T2] 



■ UTILITY ROUTINES 

■ SET DS TO THE DATA SEGMENT 



DOS 


PROC 


NEAR 




PUSH 


AX 




SUB 


AX, AX 




MOV 


DS,AX 




POP 


AX 




RET 




DOS 


ENDP 




WHAT_BASE 


PROC NEAR 




ASSUME 


DS:ABSO 




PUSH 


DS 




CALL 


DOS 




MOV 


DX,ADDR 6845 




AND 


DL,OFOH 




OR 


DL.OAH 




POP 


DS 




RET 




WHAT_BASE 


ENDP 


OUT_DX 


PROC 


NEAR 




XCHG 


AL,AH 




OUT 


DX,AL 




INC 


DX 




XCHG 


AL,AH 




OUT 


DX,AL 




DEC 


DX 




RET 




OUi_DX 


ENDP 






ROUTINE 


10 SOUND BEEPER 


BP_1 


PROC 


NEAR 




OUT 
RET 


DX, AL 


BP_1 


ENDP 




BEEP 


PROC 


NEAR 




PUSH 


DX 




MOV 


DX,TIMER+3 




MOV 


AL,10110110B 




CALL 


BP 1 




MOV 


AX,533H 




DEC 


DX 




CALL 


BP 1 




MOV 


AL,AH 




CALL 


BP 1 




MOV 


DX,P0RT B 



INTERRUPTS ON 

SET DIRECTION FORWARD 

SAVE THE REGISTER SET 



SAVE AX VALUE 
GET INTO LOW BYTE 
ZERO TO HIGH BYTE 
* 2 FOR TABLE LOOKUP 
PUT INTO SI FOR BRANCH 
TEST FOR WITHIN RANGE 
BRANCH AROUND BRANCH 
RECOVER REGISTER 
PASS UNRECOGNIZED CALL 
RETURN TO CALLER 



SAVE REGISTER 
RESTORE REGISTER 



SAVE DATA SEGMENT 
GET LOW MEMORY SEGMENT 
GET CRTC ADDRESS 
STRIP OFF LOW NIBBLE 
SET TO STATUS REGISTER 



AH= I NDEX, AL=DATA, DX= PORT 

GET INDEX VALUE 

SET INDEX REG 

SET DX TO DATA REG 

GET DATA VALUE 

SET DATA REG 

SET DX BACK TO INDEX 



SEL TIM 2, LSB, MSB, 8 1 NARY 
: WRITE THE TIMER MODE REG 
; PIVISOR FOR 1000 HZ 

; WRITE TIMER 2 CNT - LSB 

; WRITE TIMER 2 CNT - MSB 



122 IBM Enhanced Graphics Adapter 



August 2, 1984 



0D38 


EC 


0D39 


8A EO 


0D3B 


OC 03 


0D3D 


E8 0D1E R 


ODUO 


2B C9 


0D42 




0DU2 


E2 FE 


ODI+4 


FE CB 


0DU6 


75 FA 


0DU8 


8A C4 


0D4A 


E8 0D1E R 


ODUD 


5A 


ODUE 


C3 


ODUF 





ODUF E6 OCFE R 
0D52 CU IE 0'tA8 R 
0D56 26: CU IF 



0D5A 


51 








0D5B 


52 








0D5C 


E8 


004 F R 




0D5F 


8A 


26 


0449 R 




OD63 


F6 


06 


0487 R 


60 


0D68 


7U 


18 






0D6A 


80 


PC 


OF 




0D6D 


75 


07 






0D6F 


81 


C3 


0440 




0D73 


EB 


33 


90 




0D76 










0076 


80 


FC 


10 




0D79 


75 


07 






0D7B 


81 


C3 


0480 




0D7F 


EB 


27 


90 




0082 










0082 


80 


FC 


03 




0085 


77 


14 






0087 


AO 


0488 R 




008 A 


2H 


OF 






0D8C 


3C 


03 






0D8E 


74 


07 






0090 


3C 


09 






0092 


74 


03 






0094 


EB 


05 


90 




0097 










0097 


81 


03 


04C0 




0D9B 










009B 


8A 


OE 


0449 R 




0D9F 


2A 


ED 






0DA1 


E3 


05 






0DA3 










00A3 


83 


C3 


40 




00A6 


E2 


FB 






0DA8 










00A8 










00A8 


5A 








00A9 


59 








OOAA 


C3 








ODAB 











OOAB 


E8 0D5A R 


ODAE 


83 03 05 


0DB1 


B6 03 


0DB3 


B2 C4 


0085 


B8 0001 


0DB8 


FA 


0DB9 


E8 0D15 R 


ODBC 


26: 8A 07 


ODBF 


FE C4 


00C1 


E8 0015 R 


0DC4 




0DC4 


FE C4 


0DC6 


43 


0DC7 


26: 8A 07 


ODCA 


E8 0D15 R 


ODCD 


80 FC 05 


ODDO 


72 F2 


0DD2 


26: 8A 07 


0DD5 


43 


0DD6 


B2 C2 


0DD8 


EE 


0DD9 


B2 C4 


ODDB 


B8 0003 


ODDE 


E8 0D15 R 


0DE1 


FB 


0DE2 


8B 16 0463 R 


0DE6 


2A E4 


0DE8 




ODES 


26: 8A 07 


ODEB 


E8 0D15 R 


ODEE 


43 


ODEF 


FE C4 


0DF1 


80 FC 19 



2395 
2396 
2397 
2398 
2399 
2400 
2401 
2402 
2403 
2404 
2405 
2406 
2407 
2408 
2409 
2410 
2411 
2412 
2413 
2414 
2415 
2416 
2417 
2418 
2419 
2420 
2421 
2422 
2423 
2424 
2425 
2426 
2427 
2428 
2429 
2430 
2431 
2432 
2433 
2434 
2435 
2436 
2437 
2438 
2439 
2440 
2441 
2442 
2443 
2444 
2445 
2446 
2447 
2448 
2449 
2450 
2451 
2452 
2453 
2454 
2455 
2456 
2457 
2458 
2459 
2460 
2461 
2462 
2463 
2464 
2465 
2466 
2467 
2468 
2469 
2470 
2471 
2472 
2473 
2474 
2475 
2476 
2477 
2478 
2479 
2480 
2481 
2482 
2483 
2484 
2485 
2486 
2487 
2488 
2489 
2490 
2491 
2492 
2493 
2494 
2495 
2496 
2497 
2498 
2499 
2500 
2501 
2502 
2503 
2504 
2505 
2506 
2507 
2508 
2509 
2510 
2511 
2512 
2513 
2514 
2515 
2516 
2517 
2518 
2519 
2520 



AL,DX 
AH,AL 
AL,03 



LOOP 
DEC 
JNZ 
MOV 
CALL 
POP 



GET SETTING OF PORT 
SAVE THAT SETTING 
TURN SPEAKER ON 

SET CNT TO WAIT 500 MS 

DELAY BEFORE TURNING OFF 
DELAY CNT EXPIRED? 
NO-CONTINUE BEEPING SPK 
RECOVER VALUE OF PORT 



RETURN TO CALLER 



FIND THE PARAMETER TABLE VECTOR IN THE SAVE TABLE 



ASSUME 

CALL 

LES 

LES 

RET 



PROC NEAR 

DS:ABSO 

DDS 

BX, SAVE_PTR 

BX, DWORD PTR ES: | 

ENDP 



ESTABLISH ADDRESSING TO THE CORRECT MODE TABLE ENTRY 



PUSH 
PUSH 
CALL 
MOV 
TEST 
JZ 



• WE HAVE A MEMORY EXPANSION OPTION HERE 



SET_BASE 

AH,CRT_MODE 

INF0,060H 



GET PARM TBL PTR 



CMP 
JNE 
ADD 
JMP 

CMP 
JNE 
ADD 
JMP 



AH,OFH 

B_M_2 

BX,BASE_2 - BASE_1 

B_M_OUT 



AH,010H 

B_M_1 

BX, BASE_2 • 

B_M_0UT 



M_TBL_LEN • 



• CHECK THE SWITCH SETTING FOR ENHANCEMENT 



MOV 
AND 
CMP 
JE 
CMP 
JE 
JMP 



AL, INF0_3 

AL,OFH 

AL, 03H 

BRS 

AL,09H 

BRS 

B_M_3 



• WE WILL PERFORM ENHANCEMENT 



BRS: 
B_M_3; 



BX,BASE_3 - BASE_1 

CL, CRT_M0DE 

CH,CH 

B_M_4 



SKIP ENHANCED PORTION 



SECONDARY EMULATE SETTING 
PRIMARY EMULATE SETTING 



VECTOR TO ENHANCEMENT TBL 



MOV 
SUB 
JCXZ 

•THIS LOOP WILL MOVE THE PTR TO THE INDIVIDUAL MODE ENTRY 



LENGTH OF ONE MODE ENTRY 



B_M_4: 

B_M_OUT: 

POP 
POP 
RET 

MAKE_BASE 



ENDP 
PROGRAM THE EGA REGISTERS FROM THE PARAMETER TABLE 



PROGRAM THE SEQUENCER 



CALL 
ADD 
MOV 
MOV 
MOV 
CLI 



MOV 
CALL 
CMP 



MAKE_BASE 
BX,TFS_LEN 
DH,3 

DL,SEQ_ADDR 
AX, 0001 H 



AL, ES:[BX] 

0UT_DX 

AH,M1+1 



GET SEQUENCER VALUE 
NEXT INDEX 
SET IT 



MOV 


DL,MISC OUTPUT 


OUT 


DX,AL 


MOV 


DL,SEQ ADDR 


MOV 


AX,0003H 


CALL 


OUT DX 



PROGRAM THE CRT CONTROLLER 
MOV DX,ADDR_6845 



GET VALUE FROM TABLE 
SET CRTC REGISTER 
; NEXT TABLE ENTRY 
; NEXT INDEX VALUE 
; TEST REGISTER COUNT 



August 2, 1984 



IBM Enhanced Graphics Adapter 123 



ObFU 


n F2 


0bF6 


Z6'. 8b 47 F1 


ODFA 


86 EG 


ObFC 


A3 GU6b R 


ODFF 


88 F3 


0E01 


E8 GDG5 R 


0E04 


EC 


0E05 


82 CG 


0E07 


2A EU 


0E09 




0E09 


26:. 8A 07 




86 EG 




EE ..,, 


PEOF 


86 EG 




EE 


QEi2 


'»3 , 


0E13 


FE C4 


t)E15 


80 Ffe Mi 


OEIS 


72 EE 


OEIA 


80 Ob 


GE1C 


Ee 


0E1D 


IE 


(3E1E 


06 


dEIF 


C4 3E 04A8 R 


0E23 


26: CU 70 04 


0E27 


8C CO 


bE29 


08 C7 


0E2B 


74 09 


0E2D 


IF 


0E2E 


IE . 


0E2F 


89 001b 


bE32 


F3/ Ait 


bE3U 


146 


bE35 


A4 


0E36 




GE36 


07 


bE37 


1F 


bE:39 


6^ ec 


0E3A 


Bb 00 


bE3C 


EE 


bE30 


82 CA 


GE3F 


80 01 


OEUl 


EE 


oEta 


82 CE 


GEW 


2A E4 


0,E46 




0EU6 


26: 8A 07 


GEH9 


E8 0015 R 


0E4C 


U3 


GEUD 


FE C4 


GEUF 


80 FC 09 


GE52 


72 F2 


0E54 


C3 


0E55 





bE55 


AO 


0487 n 


bE58 


A6 


80 


GE5A 


75 


39 


GESC 


6A 


B800 . 


pE5F 


^G 


0449 R 


bE62 


3C 


06 


GE64 


76 


OA 


bE66 


BA 


BOOG 


bE6S» 


3C 


07 


0E6B 


74 


03 


bE6P 


BA 


AGOG 


0E7O 






0E70 


^B 


072b 


OE73 


3C 


G4 


bE75 


72 


06 


bE77 


3C 


07 


bE79 


74 


02 


0E78 


28 


DB 


GE7D 






GE7D 


8E 


C2 


0E7F 


8B 


OE 044C R 


0E83 


E3 


10 


GE85 


B9 


8G0G 


0E88 


80 


FE AG 


bE8B 


74 


m 


§11? 


63 


40 






m\ 


it 


% 


0£t>3 


F3/ AB 


bE9$ 






GE9i5 


fc3 




0E96 






OESie 






bE96 


E8 


lbB7 R 


0E99 


C3 




0E9A 







PE9A 


50 


GE^B 


IE , 


OESIC 


E8 OCFE R 


bE9F 


AO 0488 R 


bEA2 


IF , 


0EA3 


24 OF 


0EA5 


3C 03 


PEA7 


74 07 


GEA9 


3C 09 


bEAB 


74 b3 



21521 
2522 
2523 
2524 
2525 
2526 
2527 
2528 
2529 
2530 
2531 
2532 
2533 
2534 
2535 
2536 
2537 
2538 
2539 
2540 
2541 
2542 
25U3 
25Uii 
25U5 
2546 
2547 
2548 
2549 
2550 
2551 
2552 
2553 
2554 
2555 
2556 
2557 
2558 
2559 
2560 
2561 
2562 
2563 
2564 
2?65 
2566 
2567 
2568 
25(59 
2570 
2571 
2572 
2573 
2574 
2575 
2576 
2577 
2578 
2579 
2580 
2581 
2582 
2583 
2584 
2585 
2586 
2587 
2588 
2589 
2590 
2591 
2592 
2593 
2594 
2595 
2596 
2597 
2598 
2599 
25GG 
?6til 
2602 
2603 
2604 
2605 
2606 
2607 
2606 
2609 
2iS1G 
2611 
2612 
2613 
2614 
2615 
§616 
2S17 
2618 
2619 
2820 
2621 
2622 
2523 
262U 
2625 
^526 
262? 
2628 
2629 
2630 
2631 
2p32 

263^ 
2635 
2636 
2637 
2638 
2639 
2(540 
2541 
2642 
2643 
2644 
2645 
2646 



JB XI 

MOV AXiES:[BXI[-bFH] 

XCHG AH,AL 

MGV eURS0R_MbDE>A;^ 

PROGRAM THE ATTRIBUTE CHIP 

MOV SI,8X 

CALL WhaT_BASE 

I N AL, DX 

MOV DL,ATTR_WRITE 

SUB Ah, AH 



MOV 


AL,ES:(8X] 


XCHG 


AH,AL 


bUT 


g;Jt 


XCHG 


OUT 


bx,AL 


m 


BX 


s 


AH . 


AH;M5 


JB 


D3 


MOV 


AL,b 


OUT 


DX,AL 


;— — CHECK 1 


F PALETTE REGISTER V/ 


PUSH 


DS 


PUSH 


ES 


LES 


DI,SAVE PTR 


LES 


Dl, DWORD PTR ES:[D 


MOV 


AX,ES 


OR 


AX,DI 


JZ 


SAVE OUT 


; STORE AWAY THE PALETTE VALU 


POP 


DS 


PUSH 


PS 


Mbv . 


CX,16b 


REP MbVSB 




INC, 


SI 


MOVSB 




SAVE OUT: , 




POP 


ES 


POP 


DS 


;— — I>(^0GRAm 


THE GRAPHICS CHIPS 


MGV 


DL. GRAPH 1 POS 


MOV 


AL;o 


GUT 


EjX,AL 


MOV 


bL,GRAPH_2 POS 


MOV 


ALil. 


OUT 


OX,AL 


MOV 


DL, GRAPH ADDR 


SUB 


AH, AH 


04: 




MOV 


AL,ES:[Bxi 


CALL 


OUT_DX 



SET LOW RAM VALUE 



INDEX COUNTER 
GET DATA VALUE 



NEXT DATA value 
NEXT INDEX VALUE . 
TEST REGISTER COUNT 
DO THE REST 



IF ZERO, NO SAVE OCCURS 



SAVE THfe PALETTE REGS 
SAVE THE OVERSCAN ^Eb 



SET_REGS 


ENDP 




MODE SET 


REGEN CLEAR ROUTIN 


6hANk 


PROG, 


NEAR ,, , 




ASSUME 


DS:ABSG,ES: NOTHING 




Mbv 


AL, INFO 




TEST 


AL,b80H 




JNZ 


GUT 1 , 




MOV 


DX,OB8bOH 




MOV 


AL,CRT MODE 




CMP 


AL,6 




JBE 


CGO 




MOV 


DX,OB0O0H 




CMP 


AL,7 




JE 


CGO 




MOV 


DX,GAbGOH 


CGO: 








MOV 


BX,0720H 




CMP 


al:4 




JB 


WWI. 




CMP 


AL,7 




JE 


WWI 




SUB 


8X,BX 


Wwi: 








SRLOAb 


ES 




MGV 


ES,DX 




MOV 


CX,CRT_LEN 




JCXZ 


c?<j^qpbH 

pHj^pAOH 




mt 




r. 




Mbv 


cII,046h 


fi_i3A: 








m 


AX,B>( 




S 


Di;bl 




STOSW 


8ut_l : 








REt 




ILank 


ENDP 




PH_5 


PROC 


NEAR 




GALL 
RET 


PAL_ON 


pH_5 


ENDP 






See if we are to Support 64 


Bf?ST_DfeT ..,. 


PROC NEAR 




ASSUME 


DS:A8S0 




l?USH 


Ax 




PUSH 


DS 




CALL 


DOS 




Mbv 


AL, INFO 3 




POP 


DS 




AND 


AL,GFH 




CM*> 


AL,G3H 




JE 


B YES 




CMP 


AL,09H 




JE 


B YES 



PARAMETER BYTE 



FILL i^EGEN WITH BLANKS 

SEE IF -BLANK IS TO OCCUR 
MODE SEt HIGH BIT 
SKIP BLANK FOR, REGEN 

COLOR Mode regen address 
CURRENT Mode set 

0-6 AI^E COLOR MODES 



remaining Modes 

ali>ha. blank 
alpHamodEs ( 

alpHa Moot 

graphics blank value 

SET the regen segment 



; BLANK VALUE 
; CLEAR POINTER 
CLEAR THE PAGE 

; RETURN TO CALLER 



) A 640 X 200 MODE 



i emulAtE mode 

; EMULATE MODE 



124 IBM Enhanced Graphics Adapter 



August 2, 1984 



DEAD 


58 








2647 


OEAE 


F8 








2648 


OEAF 


C3 








2649 


OEBO 










2650 


OEBO 


59 








2651 


0EB1 


F9 








2652 


0EB2 


C3 








2653 


GEB3 










2654 
2655 
2656 
2657 


0EB3 










2658 
2659 


0EB3 


FA 








2660 


OEB«t 


C7 


06 dioc 


R 


0000 E 


2661 


OEBA 


8C 


OE dIdE 


R 




2662 


OEBE 


FB 








2663 


OEBF 


8d 


26 d487 


R 


F3 


2664 
2665 


0EC4 


5d 








2666 


0EC5 


F6 


06 dU87 


R 


02 


2667 


OECA 


7U 


2C 






2668 


OECC 


A1 


0U1O R 






2669 


OECF 


2»» 


30 






2670 


0ED1 


3C 


30 






2671 


0ED3 


7U 


48 






2672 
2673 
2674 
2675 


0ED5 


C6 


06 0U8U 


R 


18 


2676 


OEOA 


C7 


06 0485 


R 


0008 


26t7 


OEEO 


58 








2678 


0EE1 


8d 


OE 0487 


R 


08 


2679 


0EE6 


3C 


01 






2680 


0EE8 


76 


09 






2681 


OEEA 


3C 


04 






2682 


OEEC 


73 


05 






2683 


OEEE 


8d 


OE 0487 


R 


04 


2684 


0EF3 










2685 


0EF3 


CD 


42 






2686 


0EF5 


E9 


219E R 






2687 
2688 
2689 
269d 


0EF8 










2691 


0EF8 


A1 


0410 R 






2692 


OEFB 


24 


30 






2693 


OEFD 


3C 


30 






2694 


OEFF 


75 


40 






2695 
2696 
2697 
2698 


dFdi 


C6 


06 d484 


R 


18 


2699 


bF06 


C7 


d6 0485 


R 


OOOE 


27dd 


OFOC 


58 








27d1 


OFOO 


CD 


42 






2702 


OFOF 


C7 


06 0460 


R 


OBOC 


27d3 


0F15 


8G 


OE 0487 


R 


08 


27d4 


0F1A 


E9 219E R 






27d5 












27d6 












27d7 












27d8 


0F1D 










27d^ 


0F1D 


58 








2710 


0F1E 


50 








2711 


0F1F 


B6 


03 






2712 


0F21 


2H 


80 






2713 


0F23 


8d 


26 0487 


R 


7F 


2714 


0F28 


08 


06 0487 


R 




2715 


0F2C 


58 








2716 


0F2D 


2U 


if 






2717 


0F2F 


3C 


OF 






2718 


0F31 


7H 


02 






2719 


OF33 


BO 


07 






272d 


0F35 










2721 


0F35 


A2 


0449 R 






2722 


0F38 


B2 


B4 






2723 


0F3A 


89 


16 0463 


R 




2724 


0F3E 


EB 


10 90 






2725 
2726 
2727 
2728 


OFlJl 










2729 


OFUI 


58 








2730 


0F42 


50 








2731 


0FU3 


B6 


03 






2732 


0FU5 


2U 


80 






2733 


0FU7 


80 26 dU87 


R 


7F 


2734 


0F4C 


d8 


06 G487 


R 




2735 


0F50 


58 








2736 


0F51 


2U 


7F 






2737 


0F53 


A2 


0449 R 






2738 


0F56 


B2 


D4 






2739 


0F58 


89 


16 0463 


R 




2740 


0F5C 










2741 


0F5C 


C7 


06 044E 


R 


0000 


2742 


0F62 


G6 


06 0462 


R 


00 


2743 
2744 


0F67 


89 


0008 






2745 


0F6A 


BF 


0450 R 






2746 


dF6D 


IE 








2747 


OF§E 


d7 








2748 


OFfiF 


2B 


CO 






2749 


0F71 


F3/ 


AB 






2750 
2751 


0F73 


E8 


0D5A R 






2752 
2753 


0F76 


26 


8A 07 






2754 


0F79 


2A 


E4 






2755 


0F7B 


A3 


044A R 






2756 
2757 


0F7E 


26 


8A 47 01 




2758 


0F82 


A2 


0484 R 






2759 
2760 


0F85 


26 


8A 47 02 




2761 


0F89 


2A 


E4 






2762 


0F8B 


A3 


0485 R 






2763 
2764 


0F8E 


26 


&B 47 03 




2765 


0F92 


A3 


044C R 






2766 
2767 


dF95 


28 


DB 






2768 


GF97 


BO 


01 






2769 


dF99 


8A 


26 0449 


R 




2770 


dF9D 


80 


FC 07 






2771 


dFAO 


7«t 


00 






2772 



POP AX 

CLC 

RET 
B_YES: 

POP AX 

STC 

RET 
BRST_DET ENDP 

.__„- MODE SET 

AHO: 

ASSUME DS:ABSO 



MOV 
AND 
CMP 



INF0,11110011B 



AX, EQU I P_FLAG 
AL,030H 
AL,030H 
ST_2 



TURN OFF RETRACE BIT 

EGA ACTIVE BIT 
SAVE 

THERE IS NO MONOCHROME 
THERE IS A MONOCHROME 
CHECK THE EQUIPMENT FLAG 

FOR MONOCHROME CALL 
It IS A MONOCHROME CALL 



FALL THROUGH => REGULAR COLOR CARD SETUP 

MOV ROWS, 024D 
MOV POINTS, 8 
POP 



CMP 
JBE 
CMP 
JAE 



INFO, 00001 OOOB 

AL.1 

5T_7 

ALi4 

ST_7 

INFO, 000001 OOB 



JMP V_RET 
AT THIS POINT THERE IS NO MONOCHROME ATTACHED TO THE ADAPTED 



MOV AX, EQU I P_FLAG 

AND AL,d3dH 

CMP AL,d3dH 

JNE ST_3 



i TEST THE EQUIPMENT FLAG 
TO SEE IF THIS ISA 
MONOCHROME SETUP CALL 

; MUST BE COLOR TO CARD 



FALL THROUiSH => REGULAR MONOCHROME CARD SETUP 



MOV 


ROWS,024D 


MOV 


POINTS, d14D 


POP 


AX 


INT 


42H 


MOV 


CURSOR MODE,OBOCH 


OR 


INfO,8 


JMP 


V RET 



• MONOCHROME SETUP TO THE ADAPTER 



POP 


AX 


PUSH 


AX 


MdV 


bH,3 


AND 


AL,080H 


And 


INF0,d7FH 


OR 


iNfo,al 


POP 


AX 


and 


AL,d7FH 


CMP 


AL,dFH 


JE 


ST 2A 


MOV 


AL,7 


MOV 


CRT MODE.AL 


MOV 


DL,CRTC ADDR B 


MdV 


ADDR 6845, DX 


JMP 


QQ1 



• COLOR SETUP TO THE ADAPTER 



PUSH 


AX 


MOV 


DH,3 


AND 


AL,08dH 


AND 


iNFd,d7FH 


OR 


INFd,AL 


POP 


AX 


AND 


AL,d7FH 


MOV 


CRT MODE,AL 


MOV 


bL,CRTC ADDR 


MOV 


ADDR_6845,DX 


MOV 


CRT START, 


MOV 


ACTIVE PAGE,d 


ASSUME 


ES: NOTHING 


MOV 


CX,8 


MOV 


Dl, OFFSET CURSOR POSN 


PUSH 


bs 


POP 


ES 


SUB 


AX>AX 


REP 


STOSW 


CALL 


MAkE.bASE 


MOV 


AL,ES:iBX) 


SUB 


Ah, AH 


MOV 


CRT_COLS,AX 


MdV 


AL,ES:[BX][1] 


MOV 


ROWS,AL 


MOV 


AL,ES:[BX][2l 


SUB 


AH, AH 


MOV 


PdlNTS>AX 


MOV 


AX,ES:[BX][3] 


MOV 


CRT_LEN,AX 


SUB 


8X,BX 


MOV 


Al, 1 


MOV 


AH,dRT_MODE 


CMP 


AH, 7 


JE 


ENTRY 2 



; RECdVER 

; OTHER ADAPTER MODE CALL 

; FIX PLANAR VALUE 

; THE EGA IS NOT ACTIVE 

j BACK TO CALLER 



; PICK OFF tHe CLEAR BIT 

; MASK OFF THE OTHER BITS 

J SAVE REGEN CLEAR BIT 

; RECOVER TRUE CALL VALUE 

; ALREADY DEALT WITH 07 

J A MONOCHROME MODE 

; DO THIS MODE 

• REGULAR MONOCHROME 



isAVE MODE VALUE 



; Isolate regen clear bit 

; PREPARE INFO BYTE 

; SET IT, OR NOT 

; RECOVER TRUE MODE CALL 

', DONE WITH b7 

} SAVE THIS Mode 

J 3-D-X 

j SAVE CRTC ADDRESS 



8 PAGES OF CURSOR VALUES 

OFFSET 

ESTABLISH 

AbDRESSING 
d THOSE CURSOR LOCATIONS 
CLEAR OUT SAVtb VALUES 



GET COLUMN COUNT 
ZERO HIGH BYTE 
STORE COLUMN VALUE 



; GET THE BYTES/CHAR 
J ZERO HIGH BYTE 
j STORE BYTES/CHAR 



; ZERO 

5 MONOCHROME ALPHA CHAR GEN 

I GET CURRENT MObE! 

; IS IT MONOCHROME 

I 9X14 FONT 



August 2, 1984 



IBM Enhanced Graphics Adapter 125 



0FA2 


80 FC 03 




2773 


0FA5 


77 35 




2774 
2775 


0FA7 


E8 0E9A R 




2776 


OFAA 


72 02 




2777 
2778 


OFAC 


BO 02 




2779 


OFAE 






2780 


OFAE 


E8 1EAE R 




2781 


0FB1 


E8 OCFE R 




2782 


OFBU 


8A 26 0449 


R 


2783 


0FB8 


80 FC 07 




2784 


OFBB 


74 03 




2785 


OFBD 


EB ID 90 




2786 


OFCO 






2787 


OFCO 


BD 0000 E 




2788 


0FC3 


BB OEOO 




2789 


0FC6 






2790 


0FC6 


OE 




2791 


0FC7 


07 




2792 


0FC8 


26: 8B 56 


00 


2793 


OFCC 


OB D2 




2794 


OFCE 


74 OC 




2795 


OFDO 


B9 0001 




2796 


0FD3 


45 




2797 


OFDI* 


E8 1EF6 R 




2798 


0FD7 


83 C5 OE 




2799 


OFDA 


EB EA 




2800 


OFDC 






2801 


OFDC 


E8 ODAB R 




2802 


OFDF 


E8 0E55 R 




2803 


0FE2 


E8 0E96 R 




2804 
2805 
2806 


0FE5 


E8 OCFE R 




2807 


0FE8 


80 3 E 0449 


R OF 


2808 


OFED 


72 06 




2809 


OFEF 


C7 06 01 OC 


R 0000 E 


2810 


0FF5 






2811 


0FF5 


80 3E 0449 


R 07 


2812 


OFFA 


77 09 




2813 


OFFC 


74 4B 




2814 


OFFE 


80 3E 0449 


R 03 


2815 


1003 


76 44 




2816 


1005 






2817 


1005 


C4 IE 04A8 


R 


2818 


1009 


83 C3 OC 




2819 


100C 


26: C4 IF 




2820 


100F 


8C CO 




2821 


1011 


OB C3 




2822 


1013 


74 32 




2823 


1015 


BE 0007 




2824 


1018 






2825 


1018 


26: 8A 00 




2826 


101B 


3C FF 




2827 


101D 


74 7A 




2828 


101F 


3A 06 0449 


R 


2829 


1023 


74 03 




2830 


1025 


46 




2831 


1026 


EB FO 




2832 


1028 






2833 


1028 


FA 




2834 


1029 


26: 8A 07 




2835 


102C 


FE C8 




2836 


102E 


A2 0484 R 




2837 


1031 


26: 8B 47 


01 


2838 


1035 


A3 0485 R 




2839 


1038 


26: 8B 47 


03 


2840 


103C 


A3 01 OC R 




2841 


103F 


26: 8B 47 


05 


2842 


1043 


A3 010E R 




2843 


loue 


FB 




2844 


1047 






2845 


1047 


EB 50 




2846 


10U9 






2847 


101+9 


C4 IE 04A8 


R 


2848 


10UD 


83 C3 08 




2849 


1050 


26: C4 IF 




2850 


1053 


8C CO 




2851 


1055 


OB C3 




2852 


1057 


74 40 




2853 


1059 


BE OOOB 




2854 


105C 






2855 


105C 


26: 8A 00 




2856 


105F 


3C FF 




2857 


1061 


74 36 




2858 


1063 


3A 06 0449 


R 


2859 


1067 


74 03 




2860 


1069 


46 




2861 


106A 


EB FO 




2862 


106C 






2863 


106C 


26: 8A 27 




2864 


106F 


26: 8A 47 


01 


2865 


1073 


26: 8B 4F 


02 


2866 


1077 


26: 8B 57 


04 


2867 


107B 


26: 8B 6F 


06 


2868 


107F 


26: 8E 47 


08 


2869 


1083 


53 




2870 


108U 


8B 08 




2871 


1086 


B8 1110 




2872 


1089 


CD 10 




2873 


108B 


5B 




2874 


108C 


26: 8A 47 


OA 


2875 


1090 


3C FF 




2876 


1092 


74 05 




2877 


1094 


FE C8 




2878 


1096 


A2 0484 R 




2879 
2880 
2881 
2882 


1099 






2883 


1099 


E8 OCFE R 




2884 


109C 


80 3E 0449 


R 07 


2885 


10A1 


77 IE 




2886 


10A3 


BB 10C8 R 




2887 


10A6 


AO 0449 R 




2888 


10A9 


2A E4 




2889 


10AB 


03 D8 




2890 


10AD 


2E: 8A 07 




2891 


10B0 


A2 0465 R 




2892 


10B3 


BO 30 




2893 


1085 


80 3 E 0449 


R 06 


2894 


10BA 


75 02 




2895 


10BC 


BO 3F 




2896 


10BE 






2897 


10BE 


A2 0466 R 




2898 



CMP 


AH,03H 




JA 


ENTRY_1 




CALL 


BRST DET 




JC 


ENTRY_2 




MOV 


AL,2 




ENTRY 2: 






CALL 


CH GEN 




CALL 


DOS 




MOV 


AH, CRT MODE 




CMP 


AH, 7 ~ 




JE 


FDG IT 




JMP 


ENTRY_1 




FDG_IT: 






MOV 


BP, OFFSET CGMN FDG 




MOV 


BX.OEOOH 




FDG: 






PUSH 


CS 




POP 


ES 




MOV 


DX,ES:IBP] 




OR 


DX,DX 




JZ 


ENTRY 1 




MOV 


CX,1 




INC 


BP 




CALL 


DO MAP2 




ADD 


BP,014D 




JMP 


FDG 




ENTRY 1: 






CALL 


SET REGS 




CALL 


BLANK 




CALL 


PH_5 




ASSUME 


DS:ABSO 




CALL 


DOS 




CMP 


CRT MODE,OFH 




JB 


MS_1 




MOV 


WORD PTR GRX_SET , OFFSET 


CGMN 


MS 1: 






CMP 


CRT MODE, 7 




JA 


SAVE GRPH 




JE 


SAVE_ALPH 




CMP 


CRT MODE, 3 




JBE 


SAVE_ALPH 




SAVE GRPH: 






LES 


BX,SAVE PTR 




ADD 


BX.OCH 




LES 


BX, DWORD PTR ES:[BX] 




MOV 


AX,ES 




OR 


AX,BX 




JZ 


J4J 




MOV 


SI,07H 




SG 1: 






MOV 


AL,ES:[BX][SI1 




CMP 


AL,OFFH 




JE 


AHO DONE 




CMP 


AL,CRT MODE 




JE 


SG_2 





; COLOR ALPHA CHAR GEN 

; LOAD ALPHA CHAR GEN 

; GET CURRENT MODE 

; IS IT MONOCHROME 

; 9X14 FONT 



; GET THE ROM SEGMENT 
INTO ES 

; GET THE CHAR HEX CODE 
ZERO = NO MORE CHARS 
NO MORE 

DO ONE CHAR AT A TIME 
MOVE TO FIRST CODE POINT 
STORE THE CODE POINT 

; ADJUST BP TO NEXT CODE 
DO ANOTHER 



; CLEAR OUT THE BUFFER 



; JMP AHO_DONE 





MOV 


AL,BYTE PTR ES:[BX] 




DEC 


AL 




MOV 


ROWS,AL 




MOV 


AX, WORD PTR ES:[BX][11 




MOV 


POINTS, AX 




MOV 


AX,WORD PTR ES:[BX][3] 




MOV 


WORD PTR GRX SET, AX 




MOV 


AX.WORD PTR ES:[BX][5] 




MOV 


WORD PTR GRX_SET + 2,AX 




STI 




J4J: 








JMP 


SHORT AH0_DONE 


SAVE_ALPH: 






LES 


BX,SAVE PTR 




ADD 


BX,08H 




LES 


BX, DWORD PTR ES:[BX] 




MOV 


AX, ES 




OR 


AX.BX 




JZ 


AHO DONE 




MOV 


SI,OBH 


SA_1: 








MOV 


AL,ES:(BX][SI ] 




CMP 


AL,OFFH 




JE 


AHO DONE 




CMP 


AL,CRT MODE 




JE 


SA_2 - 




INC 


SI 




JMP 


SA_1 


SA_2: 








MOV 


AH,ES: BX 






MOV 


AL,ES: BX 


1 




MOV 


CX,ES: BX 


2 




MOV 


DX,ES: BX 


4 




MOV 


BP,ES: BX 


6 




MOV 


ES,ES: BX 


8 




PUSH 


BX 




MOV 


BX.AX 




MOV 


AX,inOH 




INT 


10H 




POP 


BX 




MOV 


AL,ES:(BX][OAH] 




CMP 


AL,OFFH 




JE 


AHO DONE 




DEC 


AL 




MOV 


ROWS,AL 




SET THE 


LOW RAM VALUES FOR C0MPA1 


AH0_DONE: 






CALL 


DDS 




CMP 


CRT MODE, 7 




JA 


DNDCS 




MOV 


BX, OFFSET COMPAT MODE 




MOV 


AL,CRT MODE 




SUB 


AH, AH 




ADD 


BX,AX 




MOV 


AL,CS:[BXI 




MOV 


CRT MODE SET,AL 




MOV 


AL,030H 




CMP 


CRT MODE, 6 




JNE 


DO PAL 




MOV 


AL,03FH 


D0_PAL: 







CRT_PALETTE,AL 



126 IBM Enhanced Graphics Adapter 



August 2, 1984 



10C1 








2899 


10C1 


8B 


OE 


0460 R 


2900 


10C5 


EB 


28 


90 


2901 
2902 


10C8 








2903 


10C8 


2C 


28 


2D 29 2A 2E 


2904 


10CE 


IE 


29 




2905 
2906 
2907 
2908 
2909 
2910 


10D0 








2911 
2912 


10D0 


80 


FD 


00 


2913 


10D3 


75 


01* 




2914 


10D5 


FE 


CI 




2915 


10D7 


EB 


OA 




2916 


1009 








2917 


10D9 


FE 


CI 




2918 


lODB 


3A 


OE 


0485 R 


2919 


10DF 


72 


02 




2920 


10E1 


2A 


C9 




2921 


10E3 








2922 


10E3 


51 






2923 


10E4 


2A 


CD 




2924 


10E6 


80 


F9 


10 


2925 


10E9 


59 






2926 


10EA 


75 


02 




2927 


10EC 


FE 


CI 




2928 


10EE 








2929 


10EE 


C3 






2930 


10EF 








2931 
2932 
2933 
2934 
2935 
2936 
2937 
2938 
2939 
2940 


= OOOU 






2941 


10EF 








2942 
2943 


10EF 


BU 


OA 




2944 


10F1 


89 


OE 


0460 R 


2945 


10F5 


F6 


06 


0487 R 08 


2946 


10FA 


75 


33 




2947 
2948 
2949 
2950 


10FC 


8A 


C5 




2951 


10FE 


24 


60 




2952 


1100 


3C 


20 




2953 


1102 


75 


05 




2954 


nou 


B9 


1E00 


2955 


1107 


EB 


26 




2956 
2957 
2958 
2959 


1109 








2960 


1109 


F6 


06 


0487 R 01 


2961 


110E 


75 


IF 




2962 


1110 


80 


3E 


0449 R 03 


2963 


1115 


77 


15 




2964 


1117 


E8 


0E9A R 


2965 


111A 


73 


10 




2966 


111C 


80 


FD 


04 


2967 


111F 


76 


03 




2968 


1121 


80 


C5 


05 


2969 


1124 








2970 


1124 


80 


F9 


04 


2971 


1127 


76 


03 




2972 


1129 


80 


CI 


05 


2973 


112C 








2974 


112C 


E8 


10D0 R 


2975 


112F 








2976 


112F 


E8 


1135 R 


2977 


1132 


E9 


219E R 


2978 










2979 










2980 










2981 


1135 








2982 


1135 


8B 


16 


0463 R 


2983 


1139 


8A 


C5 




2984 


113B 


E8 


0D15 R 


2985 


113E 


FE 


C4 




2986 


11U0 


8A 


CI 




2987 


11U2 


E8 


0D15 R 


2988 


11U5 


C3 






2989 
2990 
2991 
2992 
2993 
2994 
2995 
2996 
2997 
2998 
2999 


1146 








3000 


11U6 


53 






3001 


1147 


8B 


D8 




3002 


11U9 


8A 


C4 




3003 


HUB 


F6 


26 


044A R 


3004 


11UF 


32 


FF 




3005 


1151 


03 


C3 




3006 


1153 


D1 


EO 




3007 


1155 


5B 






3008 


1156 


C3 






3009 


1157 








3010 
3011 
3012 
3013 
3014 
3015 
3016 
3017 
3018 
3019 
3020 
3021 
3022 


1157 








3023 


1157 


E8 


1150 R 


3024 



MOV 


CX, CURSOR MODE 


JMP 


AHl 


COMPAT MODE 


LABEL BYTE 


DB 


02CH, 028H, 02DH, 029H, 02AH, 02EH 


DB 


01EH,029H 


INCLUDE 


V1-5. INC 


SUBTTL 


VI -5. INC 


PAGE 




CALC CURSOR 


PROC NEAR 


ASSUME 


DS:ABS0 


CMP 


CH.O 


JNE 


CC 1 


INC 


CL 


JMP 


SHORT CALC OUT 


CC 1: 




INC 


CL 


CMP 


CL,BYTE PTR POINTS 


JB 


CALC OUT 


SUB 


CL,CL 


CALC OUT: 




PUSH 


CX 


SUB 


CL,CH 


CMP 


CL,010H 


POP 


CX 


JNE 


COMP 4 


INC 


CL 


COMP 4: 




RET 




CALC CURSOR 


ENDP 



CHECK FOR FULL HEIGHT 
NORMAL CHECK 
ADJUST END VALUE 



ADJUST FOR EGA REGISTERS 

WILL IT WRAP 

NO, ITS OK 

EGA METHOD FOR CURSOR END 

SAVE CURSOR TYPE VALUE 

END - START 

LOW NIBBLE EQUAL 

RESTORE 

ADD 1 FOR CORRECT CURSOR 



BACK TO CALLER 



SET_CTYPE SET CURSOR TYPE 

THIS ROUTINE SETS THE CURSOR VALUE 
INPUT 

(CX) HAS CURSOR VALUE CH-START LINE, CL-STOP LINE 
OUTPUT 

NONE 



CUT_OFF 

ASSUME 

MOV 

MOV 

TEST 

JNZ 



EQU i 

DS:ABSO 

AH,C_CRSR_START 

CURSOR_MODE,CX 

INFO, 8 

DO_SET 





THIS SE 
MOV 


CTION WILL EMU 
AL,CH 




AND 


AL,060H 




CMP 


AL,020H 




JNE 


AHl A 




MOV 


CX,01E00H 




JMP 


SHORT DO SET 




THIS SECTION : ADJUST 


AHl A: 








TEST 


INF0,1 




JNZ 


DO SET 




CMP 


CRT MODE, 3 




JA 


AHl S 




CALL 


BRST DET 




JNC 


AHl S 




CMP 


CH,CUT OFF 




JBE 


AHl B 




ADD 


CH,5 


AHl B: 








CMP 


CL,CUT OFF 




JBE 


AHl S 




ADD 


CL,5 


AHl S: 








CALL 


CALC CURSOR 


DO SET 








CALL 


M16 




JMP 
THIS RC 


V_RET 
UTINE OUTPUTS 



CRTC REG FOR CURSOR SET 
SAVE IN DATA AREA 
EGA ACTIVE BIT 
0=EGA, 1=0LD CARDS 



GET START VALUE 
TURN OFF CURSOR ? 
TEST THE BITS 
SKIP CURSOR OFF 
EMULATE CURSOR OFF 



ADJUST THE CURSOR AND TEST FOR ENHANCED OPERATION 



CURSOR EMULATE BIT 

0=EMULATE, 1=VALUE AS- I S 

POSSIBLE EMULATION 

NO, SET THE CURSOR TYPE 

SEE IF EMULATE MODE 

NOT EMULATING 

TEST START 

SKIP ADJUST 

ADJUST 



ADJUST END REGISTER 



THIS ROUTINE OUTPUTS THE CX REGISTER TO THE CRTC REGS NAMED IN AH 



MOV 
MOV 
CALL 
INC 
MOV 
CALL 
RET 



DX,ADDR_6845 

AL,CH 

OUT_DX 



ADDRESS REGISTER 

DATA 

OUTPUT THE VALUE 

NEXT REGISTER 

SECOND DATA VALUE 

OUTPUT THE VALUE 

ALL DONE 



POSITION 

THIS SERVICE ROUTINE CALCULATES THE REGEN BUFFER 

ADDRESS OF A CHARACTER IN THE ALPHA MODE 
INPUT 

AX = ROW, COLUMN POSITION 
OUTPUT 

AX = OFFSET OF CHAR POSITION IN REGEN BUFFER 



POSITION 


PROC NEAR 


PUSH 


BX 


MOV 


BX,AX 


MOV 


AL,AH 


MUL 


BYTE PTR CRT COLS 


XOR 


BH.BH 


ADD 


AX,BX 


SAL 


AX, 1 


POP 


BX 


RET 




POSITION 


ENDP 



SAVE REGISTER 

ROWS TO AL 

DETERMINE BYTES TO ROW 

ZERO OUT 

ADD IN COLUMN VALUE 

* 2 FOR ATTRIBUTE BYTES 

RESTORE REGISTER 



SET_CPOS SET CURSOR POSITION 

THIS ROUTINE SETS THE CURRENT CURSOR POSITION TO THE 

NEW X-Y VALUES PASSED 
INPUT 

DX - ROW, COLUMN OF NEW CURSOR 

BH - DISPLAY PAGE OF CURSOR 
OUTPUT 

CURSOR IS SET AT CRTC IF DISPLAY PAGE IS CURRENT 

DISPLAY 



August!, 1984 



IBM Enhanced Graphics Adapter 127 



115A 


E9 219E R 




115D 






115D 


8A CF 




115F 


32 ED 




1161 


D1 El 




1163 


SB F1 




1165 


89 94 0450 


R 


1169 


38 3 E 0462 


R 


116D 


75 05 




116F 


dB C2 




1171 

117*4 

1174 


EB 1175 R 




C3 




^^^'i 






1175 


EB 1146 R 




1178 


8B C8 




117a 


03 OE 044E 


R 


117E 


D1 F9 




1180 


B4 OE 




1182 


£8 1135 R 





1190 
1194 
11SI5 
1196 
1197 
1198 
1199 
119A 
119B 
119C 



119D 
119D 
11A0 
11 A2 



11AB 
HAD 
11AF 



116E 
116F 
11 CO 



11CD 
1103 
1109 



8A DF 

32 FF 

01 E3 

8B 97 0450 R 

8S OE 0460 R 

5F 

5E 



AO 0449 R 
3G 07 
77 37 



3C 07 
74 2C 
EB 05 90 



06 06 07 07 05 05 
04 05 00 OO 00 00 
00 05 06 04 04 04 
04 06 06 04 07 04 

07 04 



11D6 


8B 16 0463 ft 


11DF 


83 C2 06 


11E2 


EC 


11E3 


A8 04 


11E5 


B4 00 


11F7 


74 03 


11E9 


E9 12$1 ft 



11 EC A8 02 



3025 
3026 
3027 
3028 
3029 
3030 
3031 
3032 
3033 
3034 
3035 
3036 
3037 
3038 
3039 
3040 
3041 
3042 
3043 
3044 
3045 
3046 
3047 
3048 
3049 
3050 
3051 
3052 
3053 
3054 
3055 
3056 
3057 
3058 
3059 
3060 
3061 
3062 
3063 
3064 
3065 
3066 
3067 
3068 
3069 
3070 
3071 
3072 
3073 
3074 
3075 
3076 
3077 
3078 
3079 
3080 
3081 
3082 
3083 
3084 
3085 
3086 
3087 
3088 
3089 
3090 
3091 
3092 
3093 
3094 
3095 
3096 
3097 
3098 
3099 
3100 
3101 
3102 
3103 
3104 
3105 
3106 
3107 
3108 
3109 
3110 
3111 
3112 
3113 
3114 
3115 
3116 
3117 
3118 
3119 
3120 
3121 
3122 
3123 
3124 
3125 
3126 
3127 
3128 
3129 
3130 
3131 
3132 
3133 
3134 
3135 
3136 
3137 
3138 
3139 
3140 
3141 
3142 
3143 
3144 
3145 
3146 
3147 
3148 
3149 
3150 



C SET_CPOS: 



MOV 
XOR 
SAL 
MOV 
MOV 
CMP 
JNZ 
MOV 
CALL 

RET 

SET CURSOR POSITION, AX HAS ROW/COLUMN FOR CURSOR 



CL,BH 
CH,CH 
CX, 1 

[SWOFFSET CURS0R_P0SN ] , DX 

ACTIVE_PAGE,BH 

M17 

AX,DX 

M18 



ESTABLISH LOOP COUNT 
WORD OFFSET 
USE INDEX REGISTER 
SAVE THE POINTER 

; SET_CPOS_RETURN 
GET ROW/COLUMN TO AX 
CURSOR_SET 
SET_CPOS_RETURN 



PROC 
CALL 
MOV 
ADD 

SAR 
MOV 
CALL 
RET 
ENDP 



NEAR 

POSITION 

CX,AX 

CX, CRT_START 

CX,1 

AH.C_CRSR_LOC_HGH 

M16 



DETERMINE LOG IN REGEN 

ADO IN THE START ADDR 

FOR THIS PAGE 
/ 2 FOR CHAR ONLY COUNT 
REGISTER NUMBER FOR CURSOR 
SET VALUE TO CRTC 



READ CURSOR 

THIS ROUTINE READS THE CURRENT CURSOR VALUE FROM 

MEMORY AND SENDS IT BACK TO THE CALLER 
INPUT 

BH - PAGE OF CURSOR 
OUTPUT 

OX - ROW, COLUMN OF THE CURRENT CURSOR POSITION 

CX - CURRENT CURSOR MODE 



MOV 


BL,BH 


XOR 


BH,BH 


SAL 


BX,1 


MOV 


DX, [BX + OFFSET CURSOR POSN 


MOV 


CX, CURSOR^MODE 


POP 


Dl 


POP 


SI 


POP 


BX 


POP 


AX 


POP 


AX 


POP 


DS 


POP 


ES 


POP 


BP 


IRET 




;—— READ L 


GHT PEN POSITION 


AH4: 

MOV 


AL,CRT_MODE 


CMP 


AL,07H 


JA 


READ_LPEN 


TEST 


INFO, 2 


JZ 


EGA^IS^COLOR 


; MONOCHROME HERE (MONOC BIT 1) 


CMP 


AL,07H 


JE 


READ LPEN 


JMP 


OLD_LP 


; EGA IS 


COLOR HERE (MONOC BIT 0) 


EGA IS COLOR: 




CMP 


AL,06H 


JBE 


READ_LPEN 


OLD LP: 




INT 


42H 


POP 


Dl 


POP 


SI 


ADD 


SP,6 


POP 


DS 


POP 


ES 


POP 


BP 


IRET 





; PAGE VALUE 
ZERO UPPER BYTE 
WORD OFFSET 

GET CURSOR FOR THIS PAGE 
GET THE CURSOR MODE 



CALL EXISTING CODE 



DISCARD SAVED BX,CX,DX 



LIGHT PEN 

THIS ROUTINE TESTS THE LIGHT PEN SWITCH AND THE LIGHT 
PEN TRIGGER. IF BOTH ARE SET, THE LOCATION OF THE LIGHT 
PEN IS DETERMINED. OTHERWISE, A RETURN WITH NO 
INFORMATION IS MADE, 
ON EXIT 

(AH) =0 IF NO LIGHT PEN INFORMATION IS AVAILABLE 

BX,CX,DX ARE DESTROYED 
(AH) a 1 IF LIGHT PEN IS AVAILABLE 

(OH,DL) « ROW, COLUMN OF CURRENT LIGHT PEN 

POSITION 
(CH) = RASTER POSITION (OLD MODES) 
(CX) « RASTER POSITION (NEW MODES) 
(BX) = BEST GUESS AT PIXEL HORIZONTAL POSITION 



ASSUME CS:CODE,DS:ABS0 
SUBTRACT_TABLE 

LABEL BYTE 

DB 006H,006H,007H,007H,005H,005H 

DB 0O4H,O05H,0OOH,0OOH,OOOH,OOOH 

DB OOOH,005H,006H,004H,004H,004H 

DB 004H,006H,006H,004H,007H,004H 

DB 007H,004H 



READ^LPEN 



PROC 



NEAR 



' WAIT FOR LIGHT PEN TO BE DEPRESSED 

MOV DX,ADDR_6845 

ADD DX, 6 

I N AL, DX 

TEST AL,4 

MOV AH,0 

JZ V9 

JMP V6 

' NOW TEST FOR LIGHT PEN TRIGGER 



0-5 

6-B 

C-11 

12-17 

18-19 



GET BASE ADDRESS OF 6845 
POINT TO STATUS ftEGISTER 
GET STATUS REGISTER 
TEST LIGHT PEN SWITCH 
SET NO LIGHT PEN RETURN 

CODE 
NOT SET, RETURN 



TEST LIGHT PEN TRIGGER 



128 IBM Enhanced Graphics Adapter 



August 2, 1984 



11EE 


75 03 




11F0 


E9 129B R 




11F3 






11F3 


B4 10 




11F5 


8B 16 0U63 


R 


11F9 


8A CU 




11FB 


EE 




HFC 


42 




IIFD 


50 




11FE 


EC 




11FF 


8A E8 




1201 


58 




1202 


4A 




1203 


FE C4 




1205 


8A C4 




1207 


EE 




1208 


42 




1209 


EC 




120A 


8A E5 




120C 


8A IE 0449 


R 


1210 


2A FF 




1212 


2E: 8A 9F 


1C1 F 


1217 


2B C3 




1219 


8B 1E 044E 


R 


121D 


D1 EB 




121F 


2B C3 




1221 


79 02 




1223 


2B CO 




1225 






1225 


B1 03 




1227 


80 3E 0449 


R 04 


122C 


72 4D 




122E 


80 3 E 0449 


R 07 


1233 


74 46 




1235 


80 3 E 0449 


R 06 


123A 


77 28 




123C 


75 02 




123E 


D1 E8 




1240 






1240 


B2 28 




1242 


F6 F2 





1244 


8A 


E8 




1246 


02 


ED 




1248 


8A 


DC 




124A 


2A 


FF 




124C 


80 


3E 


0449 R 06 


1251 


75 


04 




1253 


B1 


04 




1255 


DO 


E4 




1257 








1257 


D3 


E3 




1259 


8A 


D4 




125B 


8A 


FO 




1250 


DO 


EE 




125F 


DO 


EE 




1261 


EB 


2C 


90 


1264 








1264 


99 






1265 


F7 


36 


044A R 


1269 


8B 


DA 




1268 


03 


E3 




126D 


8B 


C8 




126F 


52 






1270 


99 






1271 


F7 


36 


0485 R 


1275 


5A 






1276 


8A 


FO 




1278 


EB 


15 


90 


127B 








127B 


F6 


36 


044A R 


127F 


8A 


FO 




1281 


8A 


D4 




1283 


8A 


DC 




1285 


32 


FF 




1287 


D3 


E3 




1289 


F6 


26 


0485 R 


128D 


8B 


C8 




128F 








128F 


B4 


01 




1291 








1291 


52 






1292 


8B 


16 


0463 R 


1296 


83 


C2 


07 


1299 


EE 






129A 


5A 






129B 








129B 


5F 






129C 


5E 






1290 


83 


04 


06 


12A0 


IF 






12A1 


07 






12A2 


50 






12A3 


CF 






12A4 









3151 
3152 
3153 
3154 
3155 
3156 
3157 
3158 
3159 
3160 
3161 
3162 
3163 
3164 
3165 
3166 
3167 
3168 
3169 
3170 
3171 
3172 
3173 
3174 
3175 
3176 
3177 
3178 
3179 
3180 
3181 
3182 
3183 
3184 
3185 
3186 
3187 
3188 
3189 
3190 
3191 
3192 
3193 
3194 
3195 
3196 
3197 
3198 
3199 
3200 
3201 
3202 
3203 
3204 
3205 
3206 
3207 
3208 
3209 
3210 
3211 
3212 
3213 
3214 
3215 
3216 
3217 
3218 
3219 
3220 
3221 
3222 
3223 
3224 
3225 
3226 
3227 
3228 
3229 
3230 
3231 
3232 
3233 
3234 
3235 
3236 
3237 
3238 
3239 
3240 
3241 
3242 
3243 
3244 
3245 
3246 
3247 
3248 
3249 
3250 
3251 
3252 
3253 
3254 
3255 
3256 
3257 
3258 
3259 
3260 
3261 
3262 
3263 
3264 
3265 
3266 
3267 
3268 
3269 
3270 
3271 
3272 
3273 
3274 
3275 
3276 



JNZ V7A 
JMP V7 

• TRIGGER HAS BEEN SET, READ THE VALUE IN 

MOV AH, 16 

• INPUT REGS Pointed to by ah, and convert 



MOV 


DX,ADDR 6845 


MOV 


AL,AH 


OUT 


DX,AL 


INC 


dx 


PUSH 


AX 


IN 


AL,DX 


MOV 


CH,AL 


POP 


AX 


DEC 


DX 


INC 


AH 


MOV 


AL,AH 


OUT 


DX,AL 


INC 


DX 


IN 


AL,DX 


MOV 


AH,CH 


\K HAS 


THE VALUE READ 


MOV 


BL,CRT_MODE 


SUB 


BH,8H 


MOV 


BL,CS:V1IBX) 


SUB 


AX,BX 


MOV 


BX,CRT START 


SHR 


BX,1 


SUB 


AX,BX 


JN8 


V2 


SUB 


AX, AX 



■ DETEf$MINE MODE OF OPERATION 



MOV 


CL, 3 


CMP 


CRT MODE. 4 


JB 


V4 


CMP 


CRT MODE, 7 


JE 


V4 


CMP 


CRT„M0DEi06H 


JA 


V8 


JNE 


V8X 


SHR 


AX, 1 



• OLD GRAPHICS MODES 



■ DETERMINE GRAPHIC ROW POSITION 



MOV 


CH,AL 


ADD 


CH,CH 


MOV 


BL,AH 


SUB 


BH,BH 


CMP 


CRT MODE, 6 


JNE 


V3 


MOV 


CL,4 


SAL 


AH,1 



• DETERMINE ALPHA CHAR POSITION 



MOV 
MOV 
SHR 



DL,AH 
DH,AL 
DH,1 
DH,1 



• NEW GRAPHICS MODES 



DIV 


CRT COLS 


MOV 


BX,5X 


SAL 


BX,CL 


MOV 


GX,AX 


PUSH 


DX 


CWD 




DIV 


POINTS 


POP 


DX 


MOV 


DHjAL 


JMP 


V5 



■ ALPHA MODE ON LIGHT PEN 



DIV 


BYTE PTR CRT COLS 


MOV 


DH,AL 


MOV 


DL,AH 


MOV 


BL,AH 


XOR 


BH,BH 


SAL 


BX,CL 


MUL 


BYTE PTR POINTS 


MOV 


CX,AX 



MOV 


DX>ADBR 6845 


ADD 


BX,7 


OUT 


DXjAL 


POP 


DX 


POP 


Dl 


POP 


Si 


ADD 


SP,g 


POP 


DS 


POP 


ES 


POP 


gP 


iRET 




LP6N 


ENbP 



RETURN WITHOUT RESETTING 

TRIGGER 
EXIT LIGHT PEN ROUTINE 



j LIGHT PEN REGISTERS 

TO ROW COLUMN IN DX 

; ADDRESS REGISTER 

; REGISTER TO READ 

; SET IT UP 

; DATA REGISTER 



; ADDRESS REGISTER 

J SECOND DATA REGISTEFi 

} POINT TO DATA REGISTER 

J t3ET THE 2ND DATA VALUE 

J AX HAS INPUT VALUE 



} MODE VALUE TO BX 

J AMOUNT TO SUBTRACT 

} TAKE IT AWAY 

} SCREEN ADDRESS 

; DlVICiE BY 2 

} ADJUST TO 2ER0 START 

; IF POSITIVE, GET MODE 

; <0 PLAYS AS 



} DETERMINE_MODE 

; SET *8 SHIFT COUNT 

; GRAPHICS OR ALpHa 

; ALPHA_PEN 



I ALPMA^i*EH 



i DiViSOR FOR GRAPHICS 

) ROW(AL) AND COLUMN (AH) 

} AL RANGE 0-99; 

i AH RANGE O-'Sg 



j SAVE ROW VALUE IN CH 
J "2 FOR eVEN/ODD field 

COLUMN VALUE TO BX 

*8 FOR MEDIUM RES 

MEDIUM OR HIGH RES 

NOT_HIGH_RES 

SHIFT VALUE FOR HIGH RES 

COLUMN VALUE *2 FOR HIGH RES 

NOT_HIGH_RES 

*16 FOR HIGH RES 



COLUMN VALUE FOR RETURN 

ROW Value 

DIVIDE BY 4 
FOR VALUE IN 6-24 FtANGE 

L I ght_peN_reTurn_set 



j PREPARE TO DIV* IDE 

J Ax = ROW, DX = COLUMN 

5 Save Remainder 

5 pel column 

) PEL ROW 

J save From Divide 

; Prepare tG divide 

} BiVibE bY esYTes/ChAr 

* RECOVER 

; CHARACTER ROW 



ALPHA_PEN 
ROW, COLUMN VALUE 
ROWS TO DH 
COLS TO DL 
COLUMN VALUE 
TO BX 



L I GHT_PEN_RETURN_SET 
INDICATE EVERTHING SET 

light_peN return 

SAVE RETUMN value 

( IN CASE) 
GET BASE ADDRESS 

poiNt TO Reset parm 

ADDRESS, NOT DATA, 

IS IMPORTANT 
RECOVER VALUE 
RETURN_NG_RESET 



5 DISCARD SAVED BX,CX,DX 



August 2, 1984 



IBM Inh^ced Graphics Adapter 129 



12AU 








12AU 


A2 


0462 R 




12A7 


8B 


OE 044C 


R 


12AB 


98 






12AC 


50 






12AD 


F7 


El 




12AF 


A3 


OUUE R 




12B2 


8B 


C8 




1284 


8A 


IE 0449 


R 


12B8 


80 


FB 07 




12BB 


77 


02 




12BD 








12BD 


D1 


F9 




12BF 








12BF 


BU 


OC 




12C1 


E8 


1135 R 




12C4 


5B 






12C5 


D1 


E3 




12C7 


8B 


87 0450 


R 


12CB 


E8 


1175 R 




12CE 


E9 


219E R 





12D1 






12D1 


50 




12D2 


8A 


E6 


12D4 


2A 


E5 


12D6 


FE 


C4 


12D8 


3A 


EO 


12DA 


58 




12DB 


75 


02 


12DD 


2A 


CO 


12DF 






12DF 


C3 




12E0 






12E0 






12E0 


53 




12E1 


IE 




12E2 


E8 


OCFE R 


12E5 


8B 


IE 044A R 


12E9 


IF 




12EA 






12EA 


51 




12EB 


8A 


CA 


12ED 


2A 


ED 


12EF 


56 




12F0 


57 




12F1 


F3/ A4 


12F3 


5F 




12F4 


5E 




12F5 


03 


F3 


12F7 


03 


FB 


12F9 


59 




12FA 


E2 


EE 


12FC 


5B 




12FD 


C3 




12FE 






12FE 






12FE 


53 




12FF 


IE 




1300 


E8 


OCFE R 


1303 


8B 


IE 04UA R 


1307 






1308 






1308 


51 




1309 


8A 


CA 


130B 


2A 


ED 


130D 


56 




130E 


57 




130F 


F3/ A4 


1311 


5F 




1312 


5E 




1313 


2B 


F3 


1315 


2B 


FB 


1317 


59 




1318 


E2 


EE 



131C 




131C 


52 


131D 


B6 03 


131F 


B2 C4 


1321 


B8 020 F 


1324 


E8 0D15 R 


1327 


5A 


1328 


2B CO 


132A 


8A CA 


132C 


2A ED 


132E 


57 


132F 


F3/ AA 


1331 


5F 


1332 


8A C6 


1334 


52 


1335 


B6 03 


1337 


B2 C4 


1339 


B4 02 


133B 


E8 0D15 R 


133E 


5A 


133F 


BO FF 


1341 


8A CA 


1343 


57 


1344 


F3/ AA 



3277 
3278 
3279 
3280 
3281 
3282 
3283 
3284 
3285 
3286 
3287 
3288 
3289 
3290 
3291 
3292 
3293 
3294 
3295 
3296 
3297 
3298 
3299 
3300 
3301 
3302 
3303 
3304 
3305 
3306 
3307 
3308 
3309 
3310 
3311 
3312 
3313 
3314 
3315 
3316 
3317 
3318 
3319 
3320 
3321 
3322 
3323 
3324 
3325 
3326 
3327 
3328 
3329 
3330 
3331 
3332 
3333 
3334 
3335 
3336 
3337 
3338 
3339 
3340 
3341 
3342 
3343 
3344 
3345 
3346 
3347 
3348 
3349 
3350 
3351 
3352 
3353 
3354 
3355 
3356 
3357 
3358 
3359 
3360 
3361 
3362 
3363 
3364 
3365 
3366 
3367 
3368 
3369 
3370 
3371 
3372 
3373 
3374 
3375 
3376 
3377 
3378 
3379 
3380 
3381 
3382 
3383 
3384 
3385 
3386 
3387 
3388 
3389 
3390 
3391 
3392 
3393 
3394 
3395 
3396 
3397 
3398 
3399 
3400 
3401 
3402 



ACT_DISP_PAGE SELECT ACTIVE DISPLAY PAGE 

THIS ROUTINE SETS THE ACTIVE DISPLAY PAGE, ALLOWING 
FOR MULTIPLE PAGES OF DISPLAYED VIDEO. 

INPUT 

AL HAS THE NEW ACTIVE DISPLAY PAGE 

OUTPUT 

THE CRTC IS RESET TO DISPLAY THAT PAGE 





MOV 


ACTIVE PAGE.AL 




MOV 


CX,CRT_LEN 




CBW 






PUSH 


AX 




MUL 


CX 




MOV 


CRT_START,AX 




MOV 


CX,AX 




MOV 


BL.CRT MODE 




CMP 


bl;7 - 




JA 


ADP_1 


ADP_2 








SAR 


CX,1 


ADP_1 








MOV 


AH,C STRT HGH 




CALL 


M16 




POP 


BX 




SAL 


BX,1 




MOV 


AX, [BX + 0FFSE1 




CALL 


M18 




JMP 


V_RET 




SUBTTL 






INCLUDE 


VSCROLL. INC 




SUBTTL 


VSCROLL. INC 




PAGE 




FLTA 


PROC 


NEAR 




PUSH 


AX 




MOV 


AH,DH 




SUB 


AH,CH 




INC 


AH 




CMP 


AH,AL 




POP 


AX 




JNE 


LTA 




SUB 


AL,AL 


LTA: 


RET 




FLTA 


ENDP 




CRANK 


PROC 


NEAR 




PUSH 


BX 




ASSUME 


DS.-ABSO 




PUSH 


DS 




CALL 


DDS 




MOV 


BX,CRT_COLS 




POP 


DS 


CRANK_ 


A: 






PUSH 


CX 




MOV 


CL,DL 




SUB 


CH,CH 




PUSH 






PUSH 


Dl 




REP 


MOVSB 




POP 


Dl 




POP 


SI 




ADD 


SI,BX 




ADD 


DI,BX 




POP 


CX 




LOOP 


CRANK A 




POP 


BX 




RET 




CRANK 


ENDP 




CRANK. 


4 PROC 


NEAR 




PUSH 


BX 




ASSUME 


DS:ABSO 




PUSH 


DS 




CALL 


DDS 




MOV 


BX, CRT_COLS 




POP 


DS 


CRANK. 


.B: 






PUSH 


CX 




MOV 


CL,DL 




SUB 


CH,CH 




PUSH 


SI 




PUSH 


Dl 




REP 


MOVSB 




POP 


Dl 




POP 


SI 




SUB 


S1,BX 




SUB 


DI,BX 




POP 


CX 




LOOP 


CRANK B 




POP 


BX - 




RET 




CRANK. 


.4 ENDP 




PART_ 


PROC 


NEAR 




PUSH 


DX 




MOV 


DH.3 




MOV 


DL,SEQ ADDR 




MOV 


AX,020FH 




CALL 


OUT DX 




POP 


DX 




SUB 


AX, AX 




MOV 


CL,DL 




SUB 


CH.CH 




PUSH 


Dl 




REP 


STOSB 




POP 


Dl 




MOV 


AL,DH 




PUSH 


DX 




MOV 


DH.3 




MOV 


DL.SEQ ADDR 




MOV 


AH,02H 




CALL 


OUT DX 




POP 


DX 




MOV 


AL,OFFH 




MOV 


CL,DL 




PUSH 


Dl 




REP 


STOSB 



SAVE ACTIVE PAGE VALUE 
GET SAVED LENGTH OF 

REGEN BUFFER 
CONVERT AL TO WORD 
SAVE PAGE VALUE 
DISPLAY PAGE TIMES 

REGEN LENGTH 
SAVE START ADDRESS FOR 

LATER REQUIREMENTS 
START ADDRESS TO CX 

DO NOT DIVIDE BY TWO 



/ 2 FOR CRTC HANDLING 

REG FOR START ADDRESS 

RECOVER PAGE VALUE 

*2 FOR WORD OFFSET 

GET CURSOR FOR THIS PAGE 

SET THE CURSOR POSITION 



CHECK FOR SCROLL COUNT 

LOWER ROW 
UPPER ROW 
NUMBER TO SCROLL 
SAME AS REQUESTED 



YES, SET TO FOR BLANK 



MOVE ROWS OF PELS UP 



SAVE MOVE COUNT 
COLUMN COUNT 
CLEAR HIGH BYTE 
SAVE POINTERS 



NEXT ROW 
NEXT ROW 

RECOVER ROW COUNT 
DO MORE 



RETURN TO CALLER 



; MOVE ROWS OF PELS DOWN 



SAVE MOVE COUNT 
COLUMN COUNT 
CLEAR HIGH BYTE 
SAVE POINTERS 



NEXT ROW 
NEXT ROW 

RECOVER ROW COUNT 
DO MORE 

RETURN TO CALLER 



FILL ROW AFTER SCROLL 

SEQUENCER 
MAP MASK 
ALL MAPS ON 



SAVE POINTER 

CLEAR ONE ROW OF PELS 

RECOVER POINTER 

GET COLOR VALUE 



SEQUENCER 
MAP MASK 
SET THE COLOR 

ALL BITS ON 
COLUMN COUNT 
SAVE POINTER 
TURN ON THOSE BITS ! 



130 IBM Enhanced Graphics Adapter 



Ai^st2,1984 



latte 


5F 




13U7 


C3 




1348 






1348 






1348 


86 


03 


134A 


82 


C4 


134C 


88 


020 F 


134F 


E8 


0D15 R 


1352 


C3 




1353 






1353 






1353 


IE 




1354 


E8 


OCFE R 


1357 


8A 


F7 


1359 


2A 


FF 


135B 


50 




135C 


52 




135D 


8B 


C3 


135F 


F7 


26 0485 R 


1363 


8B 


08 


1365 


5A 




1366 


58 




1367 


IF 




1368 






1368 


E8 


131C R 


136B 


IE 




136C 


E8 


OCFE R 


136F 


03 


3E 044A R 


1373 


IF 




1374 


4B 




1375 


75 


F1 


1377 


E8 


1348 R 


137A 


C3 




137B 






137B 






137B 


IE 




137C 


E8 


OCFE R 


137F 


8A 


F7 


1381 


2A 


FF 


1383 


50 




1384 


52 




1385 


8B 


03 


1387 


F7 


26 0485 R 


138B 


8B 


D8 


1380 


5A 




138E 


58 




138F 


IF 




1390 






1390 


E8 


131C R 


1393 


IE 




1394 


E8 


OCFE R 


1397 


28 


3E 044A R 


139B 


IF 




139C 


48 




139D 


75 


F1 


139F 


E8 


1348 R 


13A2 


C3 




13A3 







13A3 






13A3 


8A 


08 


13A5 


E8 


16EB R 


13A8 


80 


FC 04 


13AB 


72 


08 


13AD 


80 


FC 07 


13B0 


74 


03 


13B2 


E9 


1474 R 


13B5 






13B5 


53 




13B6 


8B 


01 


13B8 


E8 


13F2 R 


13BB 


74 


31 


13BD 


03 


FO 


13BF 


8A 


E6 


1301 


2A 


E3 


13C3 






13C3 


E8 


1432 R 


13C6 


03 


F5 


1308 


03 


FD 


13CA 


FE 


CC 


13CC 


75 


F5 


13CE 






13CE 


58 




13CF 


BO 


20 


1301 






13D1 


E8 


1438 R 


1304 


03 


FD 


13D6 


FE 


CB 


13D8 


75 


F7 


13DA 






13DA 


E8 


OCFE R 


1300 


80 


3E 0449 R 07 


13E2 


74 


07 


13E4 


AC 0465 R 


13E7 


BA 


03D8 


13EA 


EE 




13EB 






13EB 


E9 


219E R 



3403 
3404 
3405 
3406 
3407 
3408 
3409 
3410 
3411 
3412 
3413 
3414 
3415 
3416 
3417 
3418 
3419 
3420 
3421 
3422 
3423 
3424 
3425 
3426 
3427 
3428 
3429 
3430 
3431 
3432 
3433 
3434 
3435 
3436 
3437 
3438 
3439 
3440 
3441 
3442 
3443 
3444 
3445 
3446 
3447 
3448 
3449 
3450 
3451 
3452 
3453 
3454 
3455 
3456 
3457 
3458 
3459 
3460 
3461 
3462 
3463 
3464 
3465 
3466 
3467 
3468 
3469 
3470 
3471 
3472 
3473 
3474 
3475 
3476 
3477 
3478 
3479 
3480 
3481 
3482 
3483 
3484 
3485 
3486 
3487 
3488 
3489 
3490 
3491 
3492 
3493 
3494 
3495 
3496 
3497 
3498 
3499 
3500 
3501 
3502 
3503 
3504 
3505 
3506 
3507 
3508 
3509 
3510 
3511 
3512 
3513 
3514 
3515 
3516 
3517 
3518 
3519 
3520 
3521 
3522 
3523 
3524 
3525 
3526 
3527 
3528 





POP 


01 




RET 




PART_1 


ENDP 




PART_2 


PROC 


NEAR 




MOV 


DH,3 




MOV 


DL.SEQ ADDR 




MOV 


AX,020FH 




CALL 


OUT_DX 




RET 




PART_2 


ENDP 




BLNK_3 


PROC 


NEAR 




PUSH 


DS 




ASSUME 


DS:ABSO 




CALL 


DOS 




MOV 


DH,BH 




SUB 


BH,BH 




PUSH 


AX 




PUSH 


DX 




MOV 


AX,BX 




MUL 


POINTS 




MOV 


BX,AX 




POP 


DX 




POP 


AX 




POP 


DS 




ASSUME 


DS: NOTHING 


S13: 








CALL 


PART 1 




ASSUME 


DS:ABSO 




PUSH 


DS 




CALL 


DOS 




ADD 


DI,CRT COLS 




POP 


DS 




DEC 


BX 




JNZ 


S13 




CALL 


PART_2 




RET 




BLNK_3 


ENDP 




BLNK_4 


• PROC 


NEAR 




PUSH 


DS 




ASSUME 


DS:ABSO 




CALL 


DDS 




MOV 


DH,BH 




SUB 


BH,BH 




PUSH 


AX 




PUSH 


DX 




MOV 


AX,BX 




MUL 


POINTS 




MOV 


BX,AX 




POP 


DX 




POP 


AX 




POP 


DS 




ASSUME 


DS: NOTHING 


S13_4: 








CALL 


PART 1 




ASSUME 


DS:ABSO 




PUSH 


DS 




CALL 


DDS 




SUB 


DI,CRT COLS 




POP 


DS 




DEC 


BX 




JNZ 


SI 3 4 




CALL 


PART 2 




RET 




BLNK_4 


ENDP 





ENABLED PLANES 
RECOVER POINTER 
RETURN TO CALLER 



: SEQUENCER 

; MAP MASK, ALL MAPS 

; ENABLE THE MAPS 

; RETURN TO CALLER 



; GET LOW MEMORY SEGMENT 

ATTRIBUTE FOR BLANK LINE 
; CLEAR HIGH BYTE 

SAVE 

SAVE BECAUSE OF MULTIPLY 

ROW COUNT 

CHARACTER HEIGHT 

NET VALUE TO BX 

RECOVER 



BLANK OUT ROW WITH COLOR 

SAVE SEGMENT 

LOW MEMORY SEGMENT 

NEXT ROW 

RECOVER 

NEXT 

DO MORE 

RETURN TO CALLER 



GET LOW MEMORY SEGMENT 

ATTRIBUTE FOR BLANK LINE 

CLEAR HIGH BYTE 

SAVE 

SAVE BECAUSE OF MULTIPLY 

ROW COUNT 

CHARACTER HEIGHT 

NET VALUE TO BX 

RECOVER 



BLANK OUT ROW WITH COLOR 

SAVE SEGMENT 

LOW MEMORY SEGMENT 

NEXT ROW 

RECOVER 

NEXT 

DO MORE 



RETURN TO CALLER 



SCROLL UP 

THIS ROUTINE MOVES A BLOCK OF CHARACTERS I 
ON THE SCREEN 

INPUT 

(AH) = CURRENT CRT MODE 

(AL) = NUMBER OF ROWS TO SCROLL 

(CX) = ROW/COLUMN OF UPPER LEFT CORNER 

(DX) = ROW/COLUMN OF LOWER RIGHT CORNER 

(BH) = ATTRIBUTE TO BE USED ON BLANKED L\f 

(DS) = DATA SEGMENT 

(ES) = REGEN BUFFER SEGMENT 

OUTPUT 

NONE — THE REGEN BUFFER IS MODIFIED 



MOV 


BL,AL 


CALL 


MK ES 


CMP 


AH, 4 


JB 


N1 


CMP 


AH, 7 


JE 


N1 


JMP 


GRAPH ICS_UP 


PUSH 


BX 


MOV 


AX.CX 


CALL 


SCROLL_POSITION 


JZ 


N7 


ADD 


SI, AX 


MOV 


AH,DH 


SUB 


AH,BL 


CALL 


N10 


ADD 


SI,BP 


ADD 


01, BP 


DEC 


AH 


JNZ 


N2 


POP 


AX 


MOV 


AL, • • 


CALL 


Nil 


ADD 


DI,BP 


DEC 


BL 


JNZ 


N4 


CALL 


DDS 


CMP 


CRT MODE, 7 


JE 


N6 


MOV 


AL,CRT M0DE_SET 


MOV 


DX,03D8H 


OUT 


DX,AL 



SAVE LINE COUNT IN BL 

TEST FOR GRAPHICS MODE 
HANDLE SEPERATELY 
TEST FOR BW CARD 



UP_CONTINUE 

SAVE FILL ATTR IN BH 

UPPER LEFT POSITION 

DO SETUP FOR SCROLL 

BLANK_FIELD 

FROM ADDRESS 

# ROWS IN BLOCK 

# ROWS TO BE MOVED 
ROW_LOOP 

MOVE ONE ROW 

NEXT LINE IN BLOCK 

COUNT OF LINES TO MOVE 

ROW_LOOP 

CLEAR_ENTRY 

RECOVER ATTRIBUTE IN AH 

FILL WITH BLANKS 

CLEAR_LOOP 

CLEAR THE ROW 

POINT TO NEXT LINE 

LINES TO SCROLL 

CLEAR_LOOP 

SCROLL_END 

IS THIS THE B/W CARD 
SKIP THE MODE RESET 
GET THE MODE SET 
ALWAYS SET COLOR CARD 

VIDEO_RET_HERE 



August 2, 1984 



IBM Enhanced Graphics Adapter 131 



13EE 






13EE 


8A 


DE 


13F0 


EB 


DC 


13F2 






13F2 






13F2 


F6 


06 0487 R 04 


13F7 


74 


12 


13F9 


52 




13 FA 


86 


03 


13FC 


B2 


DA 


13FE 


50 




13FF 






13FF 


EC 




1400 


A8 


08 


1U02 


74 


FB 


UOU 


BO 


25 


1U06 


B2 


D8 


1U08 


EE 




1U09 


58 




140A 


5A 




1U0B 






lUOB 


E8 


1146 R 


lUOE 


03 


06 044 E R 


1412 


8B 


F8 


lUlU 


8B 


FO 


1416 


2B 


D1 


1418 


FE 


C6 


141A 


FE 


C2 


141C 


32 


ED 


141E 


8B 


2E 044A R 


1422 


03 


ED 


1424 


8A 


C3 


1426 


F6 


26 044A R 


142A 


03 


CO 


142C 


06 




142D 


IF 




142E 


80 


FB 00 



1432 
1432 
1434 
1435 
1436 
1438 
1439 
143A 
143B 



143B 
143B 
143D 
143E 
1440 
1441 
1442 



1442 








1442 


Fl) 






1443 


8A 


D8 




1445 


L« 


16EB 


K 


1448 


•>3 






1449 


»B 


C? 




144B 


F8 


13h2 


R 


144E 


74 


20 




1450 


2B 


hO 




1452 


8A 


E6 




1454 


?A 


h3 




1456 








1456 


E8 


1432 


R 


1459 


J'B 


hS 




145B 


2B 


FD 




145D 


FE 


CO 




145F 


/5 


h-j 




1461 








1461 


^8 






1462 


BO 


?() 




1464 








1464 


F8 


143B 


R 


1467 


2B 


FD 




1469 


FE 


CB 




146B 


/5 


F7 




146D 


L9 


13UA 


R 


1470 








1470 


8A 


DF 




1472 


FB 


ED 




1474 









3531 
3532 
3533 
3534 
3535 
3536 
3537 
3538 
3539 
3540 
3541 
3542 
3543 
3544 
3545 
3546 
3547 
3548 
3549 
3550 
3551 
3552 
3553 
3554 
3555 
3556 
3557 
3558 
3559 
3560 
3561 
3562 
3563 
3564 
3565 
3566 
3567 
3568 
3569 
3570 
3571 
3572 
3573 
3574 
3575 
3576 
3577 
3578 
3579 
3580 
3581 
3582 
3583 
3584 
3585 
3586 
3587 
3588 
3589 
3590 
3591 
3592 
3593 
3594 
3595 
3596 
3597 
3598 
3599 
3600 
3601 
3602 
3603 
3604 
3605 
3606 
3607 
3608 
3609 
3610 
3611 
3612 
3613 
3614 
3615 
3616 
3617 
3618 
3619 
3620 
3621 
3622 
3623 
3624 
3625 
3626 
3627 
3628 
3629 
3630 
3631 
3632 
3633 
3634 
3635 
3636 
3637 
3638 
3639 
3640 
3641 
3642 
3643 
3644 
3645 
3646 
3647 
3648 
3649 
3650 
3651 
3652 
3653 
3654 



MOV BL, DH 
JMP N3 
._UP ENDP 

• HANDLE COMMON SCROLL SET UP HERE 



'"""" 


- 80X25 
PUSH 


COLOR CARD SCROLL 
DX 




MOV 


DH,3 




MOV 


DL,ODAH 




PUSH 


AX 


■ 


IN 


AL,DX 




TEST 


AL,8 




JZ 


N8 




MOV 


AL,25H 




MOV 


DL.0D8H 




OUT 


DX,AL 




POP 


AX 




POP 


DX 


N9: 


CALL 


POSITION 




ADD 


AX, CRT START 




MOV 


DI,AX 




MOV 


SI, AX 




SUB 


DX,CX 




INC 


DH 




INC 


DL 




XOR 


CH,CH 




MOV 


BP,CRT COLS 




ADD 


BP,BP 




MOV 


AL,BL 




MUL 


BYTE PTR CRT COLS 




ADD 


AX, AX 




PUSH 


ES 




POP 


OS 




CMP 


BL,0 




RET 




SCROL 


L_POS 1 T 1 


ON ENDP 




- MOVE_ROW 


N10 


PROC 


NEAR 




MOV 


CL,DL 




PUSH 


SI 




PUSH 


Dl 




REP 


MOVSW 




POP 


Dl 




POP 


SI 




RET 




N10 


ENDP 






- CLEAR_ 


ROW 


Nil 


PROC 


NEAR 




MOV 


CL,DL 




PUSH 


Dl 




REP 


STOSW 




POP 


Dl 




RET 




Nil 


ENDP 





; BLANK_FIELD 

I GET ROW COUNT 

! GO CLEAR THAT AREA 



; COLOR CARD HERE 
; WAIT_DISP_ENABLE 



DX=3D8 

TURN OFF VIDEO 
DURING VERTICAL RETRACE 



CONVERT TO REGEN POINTER 
OFFSET OF ACTIVE PAGE 
TO ADDRESS FOR SCROLL 
FROM ADDRESS FOR SCROLL 
DX = #ROWS, #COLS 

INCREMENT FOR ORIGIN 
ZERO HIGH BYTE OF COUNT 
NUM OF COLS IN DISPLAY 
TIMES 2 FOR ATTR BYTE 
GET LINE COUNT 
OFFSET TO FROM ADDRESS 
*2 FOR ATTRIBUTE BYTE 
ESTABLISH ADDRESSING 

FOR BOTH POINTERS 
MEANS BLANK FIELD 
RETURN WITH FLAGS SET 



GET # OF COLS TO MOVE 



: RECOVER ADDRESSES 



; GET # COLUMNS TO CLEAR 
STORE THE FILL CHARACTER 



SCROLL_DOWN 

THIS ROUTINE MOVES THE CHARACTERS WIT 
DEFINED BLOCK DOWN ON THE SCREEN, FIL 
TOP LINES WITH A DEFINED CHARACTER 
INPUT 

(AH) = CURRENT CRT MODE 

(AL) = NUMBER OF LINES TO SCROLL 

: UPPER LEFT CORNER OF REGION 

: LOWER RIGHT CORNER OF REGION 

FILL CHARACTER 
: DATA SEGMENT 
: REGEN SEGMENT 



(CX) = 
(DX) = 
(BH) = 
(DS) = 
(ES) = 
IT 
NONE • 



SCREEN IS SCROLLED 



MOV 

CALL 

PUSH 

MOV 

CALL 

JZ 

SUB 

MOV 

SUB 

CALL 
SUB 
SUB 
DEC 
JNZ 



CALL 
SUB 
DEC 
JNZ 
JMP 



BX 

AX, DX 

SCROLL_POSITION 

N16 

SI, AX 

AH,DH 

AH,BL 

N10 



SAVE ATTRIBUTE IN BH 
LOWER RIGHT CORNER 
GET REGEN LOCATION 

SI IS FROM ADDRESS 

GET TOTAL # ROWS 

COUNT TO MOVE IN SCROLL 

MOVE ONE ROW 



RECOVER ATTRIBUTE IN AH 



SCROLL_END 



MOV 

JMP 

SCROLL_DOWN 



BL,DH 

N14 

ENDP 



SCROLL UP 

THIS ROUTINE SCROLLS UP THE INFORMATION ON THE CRT 
ENTRY 

CH,CL = UPPER LEFT CORNER OF REGION TO SCROLL 

DH,DL = LOWER RIGHT CORNER OF REGION TO SCROLL 
BOTH OF THE ABOVE ARE IN CHARACTER POSITIONS 

BH = FILL VALUE FOR BLANKED LINES 

AL =# LINES TO SCROLL (AL=0 MEANS BLANK THE ENTIRE 
FIELD) 

DS = DATA SEGMENT 



132 IBM Enhanced Graphics Adapter 



Ai^[ust 2, 1984 



H»74 

M^lk 8A D8 

1Jt76 8B CI 



147D 
1U7F 
1U83 



2B D1 

81 C2 0101 

DO E6 



1U87 


80 


3E 0449 R 06 


1t8C 


73 


04 


msE 


DO 


E2 


1490 


D1 


E7 


1492 






1492 


06 




1493 


IF 




1494 


2A 


ED 


1496 


DO 


E3 


1498 


DO 


E3 


149A 


74 


2D 


149C 


8A 


C3 


149E 


B4 


50 


14A0 


F6 


E4 


14A2 


8B 


F7 


14A4 


03 


FO 


14A6 


8A 


E6 


14A8 


2A 


E3 


14AA 






14AA 


E8 


14CD R 


14AD 


81 


EE 1FB0 


14B1 


81 


EF 1FB0 


14B5 


FE 


CC 


14B7 


75 


F1 



14B9 8A C7 



14BB 


E8 


14E6 R 


14BE 


81 


EF 1FB0 


14C2 


FE 


CB 


14C4 


75 


F5 


14C6 


E9 


219E R 


14C9 






14C9 


8A 


DE 


14CB 


EB 


EC 


14CD 






14CD 






14CD 


8A 


CA 


14CF 






14D0 






14D1 


F3/ A4 


14D3 






14D4 






14D5 




C6 2000 


14D9 




C7 2000 


14DD 






14DE 






14DF 




CA 


14E1 




A4 


14E3 






14E4 






14E5 


C3 




14E6 






14E6 






14E6 


8A 


CA 


14E8 


57 




14E9 


F3/ 


AA 


14EB 


5F 




14EC 


81 


C7 2000 


14F0 


57 




14F1 


8A 


CA 


14F3 


F3/ 


AA 


14F5 


5F 




14F6 


C3 




14F7 






14F7 






14F7 


50 




14F8 


IE 




14F9 


E8 


OCFE R 


14FC 


8A 


26 0487 R 


1500 


80 


E4 60 


1503 


IF 




1504 


58 




1505 


74 


02 


1507 


F9 




1508 


C3 




1509 






1509 


F8 




150A 


C3 





3655 
3656 
3657 
3658 
3659 
3660 
3661 
3662 
3663 
3664 
3665 
3666 
3667 
3668 
3669 
3670 
3671 
3672 
3673 
3674 
3675 
3676 
3677 
3678 
3679 
3680 
3681 
3682 
3683 
3684 
3685 
3686 
3687 
3688 
3689 
3690 
3691 
3692 
3693 
3694 
3695 
3696 
3697 
3698 
3699 
3700 
3701 
3702 
3703 
3704 
3705 
3706 
3707 
3708 
3709 
3710 
3711 
3712 
3713 
3714 
3715 
3716 
3717 
3718 
3719 
3720 
3721 
3722 
3723 
3724 
3725 
3726 
3727 
3728 
3729 
3730 
3731 
3732 
3733 
3734 
3735 
3736 
3737 
3738 
3739 
3740 
3741 
3742 
3743 
3744 
3745 
3746 
3747 
3748 
3749 
3750 
3751 
3752 
3753 
3754 
3755 
3756 
3757 
3758 
3759 
3760 
3761 
3762 
3763 
3764 
3765 
3766 
3767 
3768 
3769 
3770 
3771 
3772 
3773 
3774 
3775 
3776 
3777 
3778 
3779 
3780 



ES = REGEN SEGMENT 

NOTHING, THE SCREEN IS SCROLLED 



GRAPHICS_UP PROC 
MOV BL,AL 
MOV AX,CX 



GRAPH_POSN 



DETERMINE SIZE OF WINDOW 



SUB 
ADO 
SAL 



DX,CX 

DX,101H 

DH,1 



DETERMINE CRT MODE 
CMP CRT_M0DE,6 



MEDIUM RES UP 



SAVE LINE COUNT IN BL 
GET UPPER LEFT POSITION 
INTO AX REG 



ADJUST VALUES 

MULTIPLY # ROWS BY 4 
SINCE 8 VERT DOTS/CHAR 
AND EVEN/ODD ROWS 



SINCE 2 BYTES/CHAR 



• DETERMINE THE SOURCE ADDRESS IN THE BUFFER 



PUSH 


ES 






POP 


DS 






SUB 


CH 


CH 




SAL 


BL 


1 




SAL 


Bl 


1 




JZ 


R1 






MOV 


AL 


BL 




MOV 


AH 


80 




MUL 


AH 






MOV 


SI 


Dl 




ADD 


SI 


AX 




MOV 


AH 


DH 




SUB 


AH 


BL 




LOOP THROUGH, MOV 


NG 


8: 

CALL 


R17 




SUB 


SI 


2000H 


-80 


SUB 


Dl 


2000H 


-80 


DEC 


AH 






JNZ 
FILL l^ 


R8 

THE 


VACAT 


:d 





CALL 


R18 




SUB 


DI,2000H 




DEC 


BL 




JNZ 


RIO 




JMP 


V_RET 


R11: 








MOV 


BL,DH 




JMP 


R9 


GRAPH 


CS_UP 


ENDP 


; 


- ROUTINE 


TO MOVE 


R17 


PROC 


NEAR 




MOV 


CL,DL 




PUSH 


SI 




PUSH 


01 




REP 


MOVSB 




POP 


Dl 




POP 


SI 




ADD 


SI,2000H 




ADD 


0I,2000H 




PUSH 


SI 




PUSH 


Dl 




MOV 


CL,DL 




REP 


MOVSB 




POP 


Dl 




POP 


SI 




RET 




R17 


ENDP 






- CLEAR A 


SINGLE ROV 


R18 


PROC 


NEAR 




MOV 


CL,DL 




PUSH 


01 




REP 


STOSB 




POP 


Dl 




ADD 


DI,2000H 




PUSH 


Dl 




MOV 


CL,DL 




REP 


STOSB 




POP 


Dl 




RET 




R18 


ENDP 




MEM_DET PROC 


NEAR 




ASSUME 


DS:ABSO 




PUSH 


AX 




PUSH 


DS 




CALL 


DOS 




MOV 


AH, INFO 




AND 


AH,060H 




POP 


DS 




POP 


AX 




JZ 


MIN 




STC 






RET 




MIN: 


CLC 
RET 





FIND_SOURCE 

GET SEGMENTS BOTH 

POINTING TO REGEN 
TO HIGH OF COUNT REG 
NUMBER OF LINES *4 

IF 0, BLANK ENTIRE FIELD 
NUMBER OF LINES IN AL 
80 BYTES/ROW 
OFFSET TO SOURCE 
SET UP SOURCE 

ADD IN OFFSET TO IT 
NUMBER OF ROWS IN FIELD 
DETERMINE NUMBER TO MOVE 

MOVING ONE ROW AT A TIME, BOTH EVEN AND ODD FIELDS 

ROW_LOOP 
MOVE ONE ROW 
MOVE TO NEXT ROW 



CLEAR THAT ROW 
POINT TO NEXT LINE 
NUMBER OF LINES TO FILL 
CLEAR_LOOP 

BLANK_F1ELD 

SET BLANK COUNT TO 

EVERYTHING IN FIELD 
CLEAR THE FIELD 



INFORMATION 



NUM OF BYTES IN THE ROW 



POINT TO THE ODD FIELD 

SAVE THE POINTERS 

COUNT BACK 

MOVE THE ODD FIELD 



NUMBER OF BYTES IN Fl 

SAVE POINTER 

STORE THE NEW VALUE 

POINTER BACK 

POINT TO ODD FIELD 



FILL THE ODD FIELD 



RETURN TO CALLER 



August 2, 1984 



IBM Enhanced Graphics Adapter 133 



150B 






3781 


C 


MEM_DET ENDP 










3782 


C 














3783 


C 




SCROLL ACTIVE PAGE UP 








3784 


C 








150B 






3785 


C 


SC_2: 






150B 


E9 


13A3 R 


3786 
3787 


C 
C 




JMP 


SCROLL_UP 


150E 






3788 


C 


AH6: 












3789 


C 




ASSUME 


DS:ABSO 


150E 


E8 


12D1 R 


3790 


C 




CALL 


FLTA 


1511 


8A 


26 0449 R 


3791 


C 




MOV 


AH, CRT MODE 


1515 


80 


FC 07 


3792 


C 




CMP 


AH,07H 


1518 


76 


F1 


3793 


C 




JBE 


SC 2 


151A 


80 


FC OD 


3794 


c 




CMP 


AH,ODH 


151D 


73 


17 


3795 


c 




JAE 


GRAPH ICS_UP_2 


151F 


E9 


219E R 


3796 
3797 


c 
c 




JMP 


V_RET 


1522 






3798 


c 


GR_ST. 


1 PROC 


NEAR 


1522 


BA 


AOOO 


3799 


c 




MOV 


DX,OAOOOH 


1525 


BO 


0511 


3800 


c 




MOV 


BP,0511H 


1528 


80 


FC OF 


3801 


c 




CMP 


AH.OFH 


1528 


72 


08 


3802 


c 




JB 


VV1 


152D 


E8 


14F7 R 


3803 


c 




CALL 


MEM_DET 


1530 


73 


03 


3804 


c 




JNC 


VV1 


1532 


BD 


0501 


3805 


c 




MOV 


BP,0501H 


1535 






3806 


c 


W1: 






1535 


C3 




3807 


c 




RET 




1536 






3808 
3809 


c 
c 


GR_ST. 


.1 ENDP 




1536 






3810 


c 


GRAPH 


CS_UP_2 


PROC NEAR 








3811 


c 




ASSUME 


DS:ABS0 


1536 


52 




3812 


c 




PUSH 


DX 


1537 


E8 


1522 R 


3813 


c 




CALL 


GR ST 1 








3814 


c 




SRLOAD 


ES 


153A 


8E 


02 


3815 


c+ 




MOV 


ES.DX 


153C 


5A 




3816 


c 




POP 


DX 


153D 


8A 


D8 


3817 


c 




MOV 


BL.AL 


153F 


8B 


CI 


3818 


c 




MOV 


AX,CX 


1541 


53 




3819 


c 




PUSH 


BX 


1542 


8A 


3E 0462 R 


3820 


c 




MOV 


BH, ACTIVE PAGE 


1546 


E8 


16C6 R 


3821 


c 




CALL 


GRX PSN 


1549 


5B 




3822 


c 




POP 


BX 


154A 


8B 


F8 


3823 


c 




MOV 


DI,AX 


154C 


2B 


01 


3824 


c 




SUB 


DX,CX 


154E 


81 


C2 0101 


3825 


c 




ADD 


DX,0101H 


1552 


2A 


E4 


3826 


c 




SUB 


AH, AH 


1554 


8A 


C3 


3827 


c 




MOV 


AL,BL 


1556 


52 




3828 


c 




PUSH 


DX 


1557 


F7 


26 0485 R 


3829 


c 




MUL 


POINTS 


155B 


F7 


26 044A R 


3830 


c 




MUL 


CRT COLS 


155F 


8B 


F7 


3831 


c 




MOV 


SI.DI 


1561 


03 


FO 


3832 


c 




ADD 


SI, AX 








3833 


c 




ASSUME 


DS: NOTHING 


1563 


06 




3834 


c 




PUSH 


ES 


1564 


IF 




3835 


c 




POP 


DS 


1565 


5A 




3836 


c 




POP 


DX 


1566 


OA 


DB 


3837 


c 




OR 


BL, BL 


1568 


74 


3F 


3838 


c 




JZ 


AR9 


156A 


8A 


CE 


3839 


c 




MOV 


CL,DH 


156C 


2A 


CB 


3840 


c 




SUB 


CL, BL 


156E 


2A 


ED 


3841 
3842 


c 
c 




SUB 


CH,CH 








3843 


c 




ASSUME 


DS:ABSO 


1570 


IE 




3844 


c 




PUSH 


DS 


1571 


E8 


OCFE R 


3845 


c 




CALL 


DOS 


1574 


50 




3846 


c 




PUSH 


AX 


1575 


52 




3847 


c 




PUSH 


DX 


1576 


8B 


CI 


3848 


c 




MOV 


AX,CX 


1578 


F7 


26 0485 R 


3849 


c 




MUL 


POINTS 


157C 


8B 


C8 


3850 


c 




MOV 


CX,AX 


157E 


5A 




3851 


c 




POP 


DX 


157F 


58 




3852 


c 




POP 


AX 








3853 


c 




ASSUME 


DS: NOTHING 


1580 


IF 




3854 
3855 


c 
c 




POP 


DS 


1581 


52 




3856 


c 




PUSH 


DX 


1582 


8B 


C5 


3857 


c 




MOV 


AX,BP 


1584 


B6 


03 


3858 


c 




MOV 


DH.3 


1586 


B2 


CE 


3859 


c 




MOV 


DL, GRAPH ADDR 


1588 


E8 


0D15 R 


3860 


c 




CALL 


OUT DX 


158B 


B2 


C4 


3861 


c 




MOV 


DL,SEq ADDR 


158D 


B8 


020 F 


3862 


c 




MOV 


AX,020FH 


1590 


E8 


0D15 R 


3863 


c 




CALL 


OUT DX 


1593 


5A 




3864 


c 




POP 


DX 


1594 


E8 


12E0 R 


3865 
3866 


c 
c 




CALL 


CRANK 


1597 


52 




3867 


c 




PUSH 


DX 


1598 


4D 




3868 


c 




DEC 


BP 


1599 


8B 


C5 


3869 


c 




MOV 


AX,BP 


159B 


B6 


03 


3870 


c 




MOV 


DH,3 


159D 


B2 


CE 


3871 


c 




MOV 


DL, GRAPH ADDR 


159F 


E8 


0D15 R 


3872 


c 




CALL 


OUT DX 


15A2 


5A 




3873 


c 




POP 


DX 


15A3 






3874 


c 


AR10: 






15A3 


E8 


1353 R 


3875 


c 




CALL 


BLNK_3 


15A6 


E9 


219E R 


3876 


c 




JMP 


V_RET 


15A9 






3877 


c 


AR9: 






15A9 


8A 


DE 


3878 


c 




MOV 


BL,DH 


15AB 


EB 


F6 


3879 


c 




JMP 


AR10 


15AD 






3880 
3881 


c 
c 


GRAPH 


CS_UP_2 


ENDP 








3882 


c 




SCROLL ACTIVE DISPLAY P 








3883 


c 








15AD 






3884 


c 


SC_3: 






liJAD 


E9 


1442 R 


3885 
3886 


c 
c 




JMP 


SCR0LL_D0WN 


15B0 






3887 


c 


AH7: 












3888 


c 




ASSUME 


DS:ABSO 


15B0 


E8 


12D1 R 


3889 


c 




CALL 


FLTA 


15B3 


8A 


26 0449 R 


3890 


c 




MOV 


AH,CRT_MODE 


15B7 


80 


FC 03 


3891 


c 




CMP 


AH,03H 


15BA 


76 


F1 


3892 


c 




JBE 


SC 3 


15BC 


80 


FC 07 


3893 


c 




CMP 


AH,07H 


15BF 


74 


EC 


3894 
3895 


c 
c 




JE 


SC_3 


15C1 


80 


FC OD 


3896 


c 




CMP 


AH,0DH 


15C4 


73 


OC 


3897 


c 




JAE 


GRAPHICS DN 2 


15C6 


80 


FC 06 


3898 


c 




CMP 


AH,06H 


15C9 


77 


04 


3899 


c 




JA 


M 


15CB 


B4 


07 


3900 


c 




MOV 


AH,07H 


15CD 


CD 


42 


3901 


c 




INT 


42H 


15CF 






3902 


c 


M_0: 






15CF 


E9 


219E R 


3903 
3904 


c 
c 




JMP 


V_RET 


15D2 






3905 


c 


GRAPH 


CS_DN_2 


PROC NEAR 


15D2 


FD 




3906 


c 




STD 





GET CURRENT MODE 
ANY OF THE OLD MODES 



GRAPHICS WRITE MODE 



SET POINTER 

DETERMINE WINDOW 

ADJUST 

ZERO HIGH BYTE 

LINE COUNT 

BYTES PER CHARACTER 

COLUMNS 

SET UP SOURCE INDEX 

ADJUST 



LINE COUNT 



LOW MEMORY SEGMENT 



SCROLL THE SCREEN 



BLANK ENTIRE WINDOW 



OLD COLOR ALPHA 
MONOCHROME ALPHA 

NEW GRAPHICS MODES 
OLD GRAPHICS MODES 



DIRECTION TO DECREMENT 



134 IBM Enhanced Graphics Adapter 



August 2, 1984 



15D3 


8A 


D8 


15D5 


52 




15D6 


E8 


1522 R 


15D9 


8E 


C2 


15DB 


5A 




15DC 


88 


C2 


15DE 


FE 


C4 


15E0 


53 




15E1 


8A 


3E 0U62 R 


15E5 


E8 


16C6 R 


15E8 


58 




15E9 


28 


06 04UA R 


15ED 


88 


F8 


15EF 


28 


D1 


15F1 


81 


C2 0101 


15F5 


2A 


Et 


15F7 


8A 


C3 


15F9 


52 




15FA 


F7 


26 0U85 R 


15FE 


F7 


26 OttUA R 


1602 


88 


F7 


160U 


28 


FO 


1606 


06 




1607 


IF 




1608 


5A 




1609 


OA 


DB 


160B 


71* 


»»0 


160D 


8A 


CE 


160F 


2A 


CB 


1611 


2A 


ED 


1613 


IE 




161U 


E8 


OCFE R 


1617 


50 




1618 


52 




1619 


88 


CI 


161B 


F7 


26 0U85 R 


161F 


88 


C8 


1621 


5A 




1622 


58 




1623 


IF 




162U 


52 




1625 


88 


C5 


1627 


B6 


03 


1629 


82 


CE 


162B 


E8 


0D15 R 


162E 


82 


CH 


1630 


88 


020 F 


1633 


E8 


0D15 R 


1636 


5A 




1637 


E8 


12FE R 


163A 


52 




163B 


40 




163C 


88 


C5 


163E 


B6 


03 


16lt0 


B2 


CE 


16U2 


E8 


0D15 R 


16«45 


5A 




16U6 






16U6 


E8 


137B R 


16U9 


FC 




164A 


E9 


219E R 


164D 






16UD 


8A 


DE 


16UF 


EB 


F5 


1651 







1651 




1651 


8A CF 


1653 


32 ED 


1655 


8B F1 


1657 


D1 E6 


1659 


88 8t» 0450 R 


165D 


33 DB 


165F 


E3 06 


1661 




1661 


03 IE 0U4C R 


1665 


E2 FA 


1667 




1667 


E8 1146 R 


166A 


03 08 


1660 


C3 



166D 




166D 


80 E3 03 


1670 


8A C3 


1672 


51 


1673 


B9 0003 


1676 




1676 


DO EO 


1678 


DO EO 


167A 


OA 08 


1670 


E2 F8 


167E 


8A FB 


1680 


59 


1681 


C3 


1682 





3907 
3908 
3909 
3910 
3911 
3912 
3913 
391U 
3915 
3916 
3917 
3918 
3919 
3920 
3921 
3922 
3923 
3924 
3925 
3926 
3927 
3928 
3929 
3930 
3931 
3932 
3933 
3934 
3935 
3936 
3937 
3938 
3939 
3940 
3941 
3942 
3943 
3944 
3945 
3946 
3947 
3948 
3949 
3950 
3951 
3952 
3953 
3954 
3955 
3956 
3957 
3958 
3959 
3960 
3961 
3962 
3963 
3964 
3965 
3966 
3967 
3968 
3969 
3970 
3971 
3972 
3973 
3974 
3975 
3976 
3977 
3978 
3979 
3980 
3981 
3982 
3983 
3984 
3985 
3986 
3987 
3988 
3989 
3990 
3991 
3992 
3993 
3994 
3995 
3996 
3997 
3998 
3999 
4000 
4001 
4002 
4003 
4004 
4005 
4006 
4007 
4008 
4009 
4010 
4011 
4012 
4013 
4014 
4015 
4016 
4017 
4018 
4019 
4020 
4021 
4022 
4023 
4024 
4025 
4026 
4027 
4028 
4029 
4030 
4031 
4032 



MOV 


BL,AL 


PUSH 


DX 


CALL 


OR ST 1 


SRLOAD 


ES 


MOV 


ES,DX 


POP 


DX 


MOV 


AX,DX 


INC 


AH 


PUSH 


BX 


MOV 


BH,ACTIVE_PAGE 


CALL 


GRX PSN 


POP 


BX " 


SUB 


AX, CRT COLS 


MOV 


DI.AX 


SUB 


DX,CX 


ADD 


DX,0101H 


SUB 


AH, AH 


MOV 


AL,BL 


PUSH 


DX 


MUL 


POINTS 


MUL 


CRT COLS 


MOV 


SI, 01 


SUB 


SI, AX 


ASSUME 


OS: NOTHING 


PUSH 


ES 


POP 


DS 


POP 


DX 


OR 


BL,BL 


JZ 


DXR9 


MOV 


CL,DH 


SUB 


CL,BL 


SUB 


CH,CH 


ASSUME 


DS:ABSO 


PUSH 


DS 


CALL 


DOS 


PUSH 


AX 


PUSH 


DX 


MOV 


AX.CX 


MUL 


POINTS 


MOV 


CX,AX 


POP 


DX 


POP 


AX 


ASSUME 


DS: NOTHING 


POP 


DS 


PUSH 


DX 


MOV 


AX.BP 


MOV 


DH,3 


MOV 


DL, GRAPH ADDR 


CALL 


OUT DX 


MOV 


DL, SEQ_ADDR 


MOV 


AX,020FH 


CALL 


OUT DX 


POP 


DX 


CALL 


CRANK_4 


PUSH 


DX 


DEC 


BP 


MOV 


AX,BP 


MOV 


DH,3 


MOV 


DL, GRAPH ADDR 


CALL 


OUT DX 


POP 


DX 


CALL 


BLNK_4 


OLD 




JMP 


V_RET 


MOV 


BL,DH 


JMP 


DXR10 


CS_DN_2 


ENDP 



ASSUME DS:ABSO 



FIND_ 


POSITION 


PROC NEAR 




MOV 


CL,BH 




XOR 


CH,CH 




MOV 


SI.CX 




SAL 


Sl,1 




MOV 


AX,[SI+ OFFSET CURSOR POSN] 




XOR 


BX,BX 




JCXZ 


P5 


■ 


ADD 


BX.CRT LEN 




LOOP 


P4 


P5: 








CALL 


POSITION 




ADD 


BX,AX 




RET 




FIND_ 


POSITION 


ENDP 



; SET REGEN SEGMENT 

; MOV CHAR ROW UP BY ONE 

; ADDRESS IN REGEN 

; ONE SCAN OVERSHOOT 



BYTES PER CHAR 



SCROLL THE SCREEN 



BLANK ENTIRE WINDOW 



DISPLAY PAGE TO CX 

MOVE TO SI FOR INDEX 

• 2 FOR WORD OFFSET 

ROW/COLUMN OF THAT PAGE 

SET START ADDRESS TO 

N0_PAGE 

PAGE_LOOP 

LENGTH OF BUFFER 

NO_PAGE 

DETERMINE LOG IN REGEN 

ADD TO START OF REGEN 



EXPAND_MED_COLOR 

THIS ROUTINE EXPANDS THE LOW 2 BITS IN BL TO 

FILL THE ENTIRE BX REGISTER 
ENTRY 

BL = COLOR TO BE USED ( LOW 2 BITS ) 
EXIT 

BX = COLOR TO BE USED ( 8 REPLICATIONS OF THE 

2 COLOR BITS ) 



PROC 


NEAR 


AND 


BL,3 


MOV 


AL,BL 


PUSH 


CX 


MOV 


CX,3 


SAL 


AL, 1 


SAL 


AL,1 


OR 


BL,AL 


LOOP 


S20 


MOV 


BH,BL 


POP 


CX 


RET 




ENDP 





ISOLATE THE COLOR BITS 
COPY TO AL 
SAVE REGISTER 
NUMBER OF TIMES 



LEFT SHIFT BY 2 
ANOTHER COLOR VERSION 

INTO BL 
FILL ALL OF BL 
FILL UPPER PORTION 
REGISTER BACK 
ALL DONE 



EXPAND_BYTE 

THIS ROUTINE TAKES THE BYTE IN AL AND DOUBLES 
ALL OF THE BITS, TURNING THE 8 BITS INTO 



August 2, 1984 



IBM Enhanced Graphics Adapter 135 



1682 








1682 


■>2 






1683 


•jl 






168U 


53 






1685 


?K 


D2 




1687 


B9 


0001 




168A 








168A 


«B 


08 




168C 


23 


09 




168E 


OB 


03 




1690 


D1 


EO 




1692 


1)1 


El 




169t 


BB 


08 




1696 


23 


09 




1698 


OB 


03 




169A 


D1 


El 




169C 


73 


EC 




169E 


8B 


C2 




16A0 


5B 






16A1 


•jV 






16A2 


■JA 






16A3 


C3 






16A4 








16A«t 








16A14 


A1 


0U50 R 




16A7 








16A7 


53 






16A8 


«B 


08 




16AA 


8A 


Ck 




16AC 


F6 


26 OUUA 


R 


16B0 


1)1 


EO 




16B2 


D1 


EO 




16BU 


?A 


FF 




16B6 


03 


C3 





U033 
U03U 
U035 
U036 
U037 
4038 
4039 
UOUO 
U0U1 
kOkZ 
U0U3 
40UU 

tous 

40U6 

I40U8 
U0U9 
4050 
4051 
4052 
4053 
4054 
4055 
4056 
4057 
4058 
4059 
4060 
4061 
4062 
4063 
4064 
4065 
4066 
4067 
4068 
4069 
4070 
4071 
4072 
4073 
4074 
4075 
4076 
4077 
4078 
4Q79 



16 BITS. THE RESULT IS LEFT IN AX 

PROC NEAR 

PUSH OX 

PUSH CX 

PUSH BX 

SUB OX, OX 

MOV CX, 1 



BX.AX 
BX,CX 
DX.BX 
AX, 1 
CX, 1 
BX,AX 
BX,CX 
DX,BX 
CX, 1 

S22 



SHL 
SHL 
MOV 
AND 



MOV 
POP 
POP 
POP 
RET 
ENDP 

PROC 
MOV 
LPOSN 
PUSH 
MOV 
MOV 
MUL 
SHL 
SHL 
SUB 
ADD 
POP 
RET 
ENDP 



NEAR 

AX,CURSOR_POSN 
LABEL NEAR 



BYTE PTR CRT_COLS 



AX, 1 

BH,BH 

AX,BX 



SAVE REGISTERS 



BASE INTO TEMP 

USE MASK TO EXTRACT BIT 

PUT INTO RESULT REGISTER 

SHIFT BASE AND MASK BY 1 
BASE TO TEMP 
EXTRACT THE SAME BIT 
PUT INTO RESULT 
SHIFT ONLY MASK NOW, 

MOVING TO NEXT BASE 
USE MASK BIT COMING OUT 

TO TERMINATE 
RESULT TO PARM REGISTER 

RECOVER REGISTERS 



GET CURRENT CURSOR 

SAVE REGISTER 

SAVE A COPY OF CURSOR 

GET ROWS TO AL 

MULTIPLY BY BYTES/COLUMN 

*4 SINCE 4 ROWS/BYTE 

ISOLATE COLUMN VALUE 
DETERMINE OFFSET 
REC0VE;R POINTER 
ALL DONE 



= DISPLAY PAGE 

= CURSOR POSITION FOR REQUESTED PAGE 



16BA 


53 


16BB 


8A OF 


16BD 


2A FF 


16BF 


D1 E3 


16C1 


8B 87 0450 R 


16C5 


5B 



16C6 
16C6 


53 






16C7 


51 






16C8 


52 






16C9 


2A 


FU 




16CB 


8A 


CF 




16CD 


8B 


!)« 




16CF 


8A 


C4 




1601 


FA 


26 


044A R 


1605 


F7 


?6 


0485 R 


1609 


?A 


FF 




1606 


03 


C3 




1600 


8B 


1L 


044C R 


16E1 


F3 


04 




16E3 








16E3 


03 


C3 




16E5 


F2 


k; 




16E7 








16E7 


5A 






16E8 


59 






16E9 


58 






16EA 


C3 






16EB 








16EB 








16EB 


BF 


B800 


16EE 


8B 


3E 


0410 R 


16F2 


81 


F/ 


0030 


16F6 


83 


FF 


30 


16F9 


75 


03 




16FB 


BF 


BOOO 


16FE 








16FE 


8E 


C6 




1700 


C3 







1701 . , 

1701 Eg 16EB R 

1704 E8 16^1 R 

1707 8B F3 



1710 F6 06 0487 R 04 



4085 
4086 
4087 
4088 
4089 
4090 
4091 
4092 
4093 
4094 
4095 
4096 
4097 
4098 
4099 
4100 
4101 
4102 
4103 
4104 
4105 
4106 
4107 
4108 
4109 
4110 
4111 
4112 
4113 
4114 
4115 
4116 
4117 
4118 
4119 
4120 
4121 
4122 
4123 
4124 
4125 
4126 
4127 
4128 
4129 
4130 
4131 
4132 
4133 
41 3f* 
4135 
4136 
4131 
413^ 
4139 
4140 
41ttl 
4142 
4143 
4144 
4145 
4146 
4147 
4148 
4149 
4150 
4151 
4152 
4153 
4154 
4155 
4156 
4157 
4158 



ASSUME 


DS:ABSO 


PUSH 


BX 


MOV 


BL,BH 


SUB 


BH,BH 


SAL 


BX,1 


MOV 


AX, [ BX H 


POP 


BX 


GRX PSN 




ENTRY 





OFFSET CURSOR_POSN] 

IN DESIRED PAGE 
■■ BYTE OFFSET INTO REGEN 



PUSH 
PUSH 
SUB 
MOV 
MOV 
MOV 
MUL 
MUL 
SUB 
ADD 
MOV 
JCXZ 



POP 
POP 
POP 



C GRX_PSN ENDP 



MOV 
MOV 
AND 
CMP 
JNE 
MOV 



CH,CH 

CL, BH 

BX,AX 

AL,AH 

BYTE PTR CRT_C0LS 

POINTS 

BH,BH 

AX, BX 

BX,CRT_LEN 

GP_2 



SI,OB800H 

DI,EQUIP_FLAG 

DI,030H 

DI,030H 

P6_A 

St,0B000H 



ES,SI 



; SAVE REGISTER 

; GET TO LOW BYTE 

; ZERO HIGH BYTE 

I *2 FOR WORD COUNT 

; CURSOR, REQUESTED PAGE 

; RECOVER REGISTER 



SAVE 

SAVE 

SAVE 

ZERO 

PAGE NUMBER 

ROW, COLUMN 

ROW 

ROW * COLUMNS/ROW 

BYTES PER ROW 

ZERO TO LEAVE COL VALUE 

ADD IN COLUMN 

PAGE LENGTH 

NO PAGE OFFSET 



RECOVER 
RECOVER 
RECOVER 



READ 


AC CURRENT 








THIS 


ROUTINE READS THE ATTRIBUTE AND CHARACTER : 




AT THE CURRENT CURSOR POSIT 


ON AND RETURNS 


THEM : 




TO THE CALLER 






INPUT 


(AH 


= CURRENT CRT MODE. 








(BH 


=i 01 SPLAY PAGE ( ALPHA 


MODES ONLY ) 






(OS 


^ DATA SEGMENT 








(ES 


= REGEN SEGMENT 






OUTPUT 


(AL) 
(AH) 


= CHAR READ 

= ATTRIBUTE READ 







ASSUME CS : CODE, OS -.ABSOjES: NOTHING 
READ_AC_CURRENT PROC NEAR 
CALL MK_ES 
CALL FIND_POSITION 



DX,ADDR_6845 



ADDRESSING IN SI 



136 IBM Enhanced Graphics Adapter 



August 2, 1984 



1719 




1719 


EC 


171A 


A8 01 


171C 


75 FB 


171E 


FA 


171F 




171F 


EC 


1720 


A8 01 


1722 


7»4 FB 


1724 




1724 


AD 


1725 


E9 219E R 


1728 





1728 






1728 


8A 


24 


172A 


8A 


44 01 


172D 


89 


COOO 


1730 


B? 


00 


1732 






1732 


«■> 


CI 


1734 


F8 




1735 


74 


01 


1737 


h9 




1738 






1738 


DO 


D2 


173A 


D1 


E9 


173C 


D1 


E9 


i73E 


73 


F2 


!?!|i 


8fi 


56 00 


45 




1744 


(;;s 




1745 






1745 






1745 


!•« 


16EB R 


1748 


E8 


16A4 R 


1748 


8B 


FO 


174D 


83 


EC 08 



1750 88 EC 



1752 
1757 
1758 
1759 



80 3 E 0449 R 06 



175B 


B6 04 


175D 




175D 


8A 04 


175F 


88 46 00 


1762 


45 


1763 


8A 84 2000 


1767 


88 46 00 


176A 


45 


176B 


83 C6 50 


176E 


FE CE 


1770 


75 EB 


1772 


EB 17 90 



1775 






1775 


01 


E6 


1777 


86 


04 


1779 






1779 


E8 


1728 R 


177C 


81 


C6 2000 


1780 


E8 


1728 R 


1783 


81 


EE 1FB0 


1787 


FE 


CE 


1789 


75 


EE 


i78B 






178B 


IE 




178C 


E8 


OCFE R . , 


178F 


C4 


3E 010C R 


1793 


IF 




1794 


83 


ED ds 


•i797 


8B 


F5 


1799 


FC 




179A 


80 


00 


179C 






179C 


16 




1790 


IF 




179E 


BA 0080 


17A1 






17A1 


^k 




17A2 


57 





4159 
4160 
4161 
4162 
4163 
4164 
4165 
4166 
4167 
4168 
4169 
4170 
4171 
4172 
4173 
4174 
4175 
4176 
4177 
4178 
4179 
4180 
4181 
4182 
4183 
4184 
4185 
4186 
4187 
4188 
4189 
4190 
4191 
4192 
4193 
4194 
4195 
4196 
4197 
4198 
4199 
4200 
4201 
4202 
4203 
4204 
4205 
4206 
4207 
4208 
4209 
4210 
4211 
^212 
4213 
4214 
4215 
4216 
4217 
4218 
4219 
4220 
4221 
4222 
4223 
4224 
4225 
4226 
4227 
4228 
4229 
4230 
4231 
4232 
4233 
4234 
4235 
4236 
4237 
4238 
4239 
4240 
4241 
4242 
4243 
4244 
4245 
4246 
4247 
4248 
4249 
4250 
4251 
4252 
4253 
4254 
4255 
4256 
4257 
4258 
4259 
4260 
4261 
4262 
4263 
4264 
4265 
4266 
4267 
4268 
4269 
4270 
4271 
4272 
4273 
4274 
4275 
4276 
4277 
4278 
4279 
4280 
428.T 
4282 
42i3 
4284 



•WAIT FOR HORIZONTAL RETRACE 



SEGMENT FOR QUICK ACCESS 



WAIT FOR RETRACE LOW 

GET STATUS 

IS HORZ RETRACE LOW 

WAIT UNTIL IT IS 

NO MORE INTERRUPTS 

WAIT FOR RETRACE HIGH 

GET STATUS 

IS IT HIGH 

WAIT UNTIL IT IS 

GET THE CHAR/ATTR 



C READ_AC_CURRENT ENDP 



MED_READ_BYTE 

THIS ROUTINE WILL TAKE 2 BYTES FROM THE REGEN 
BUFFER, COMPARE AGAINST THE CURRENT FOREGROUND 
COLOR, AND PLACE THE CORRESPONDING ON/OFF BIT 
PATTERN INTO THE CURRENT POSITION IN THE SAVE 
AREA 



ENTRY 



l,DS = POINTER TO REGEN AREA OF INTEREST 
X = EXPANDED FOREGROUND COLOR 
P = POINTER TO SAVE AREA 

PIS INCREMENT AFTER SAVE 



PROC 
MOV 
MOV 
MOV 



NEAR 
AH,[SII 
AL,[SI+1] 
CX,OCOOOH 



RCL 


DL,1 


SHR 


CX,1 


SHR 


CX,1 



GRAPHICS_READ 
CALL 
CALL 
MOV 



PROC 
MK_ES 
S26 
SI, AX 
SP,8 

BP,SP 



• DETERMINE GRAPHICS MODES 

CMP CRT_M0DE,6 
PUSH ES 
POP DS 



GET FIRST BYTE 
GET SECOND BYTE 
2 BIT MASK TO TEST 

THE ENTRIES 
RESULT REGISTER 

IS THIS BACKGROUND? 
CLEAR CARRY IN HOPES 
THAT IT IS 

IF 0, IT IS BACKGROUND 
wasn't, SO SET CARRY 

MOVE THAT BIT INTO THE 

RESULT 
MOVE THE MASK TO THE 

RIGHT BY 2 BITS 
DO IT AGAIN IF MASK 

DIDN'T FALL OUT 
STORE RESULT IN SAVE 
ADJUST POINTER 
ALL DONE 



CONVERTED TO OFFSET 

SAVE IN SI 

ALLOCATE SPACE TO SAVE 

THE READ CODE POINT 
POINTER TO SAVE AREA 



■HIGH RESOLUTION READ 

• GET VALUES FROM REGEN BUFFER AND CONVERT TO CODE POINT 

NUMBEft OF PASSES 

GET FIRST BYTE 

SAVE IN STORAGE AREA 

NEXT LOCATION 

GET LOWER REGION BYTE 

ADJUST AND STORE 

POINTER INTO REGEN 
LOOP CONTROL 
DO IT SOME MORE 
GO MATCH THE SAVED CODE 
PO I NTS 



MOV 


AL, SI 


MOV 


[BPl.AL 


INC 


BP 


MOV 


AL,[SI+2000H 


MOV 


[BP],AL 


INC 


BP 


ADD 


SI, 80 


DEC 


DH 


JNZ 


S12P 


JMP 


S15P 



■ MEDIUM RESOLUTION READ 



CALL 

ADD 
CALL 
SUB 
DEC 
JNZ 



■ SAVE AREA HAS CHARACTER II<I IT, MATCH IT 



SI,2000H 

S23 

SI,2000H-80 



IK 

SUB 


DS 

DDS 

Dl.GRX SET 

DS 

BP,8 


Mbv 


SI,BP 
AL,0 


PUSH 
POP 
MOV 


SS 
DS 
DX, 128 


PUSH 
PUSH 


i! 



MED_RES_READ 
0FFSET*2, 2 BYTES/CHAR 
NUMBER OF PASSES 

GET PAIR BYTES 

INTO SINGLE SAVE 
GO TO LOWER REGION . , 
GET THIS PAIR INTO SAVE 
ADJUST POINTER BACK INTO 

UPPER ,. 

kEEP GOING UNTIL 8 DONE 



ESTABLISH ADDRESSING 



ENSURE DIRECTION 
CURRENT CODE POINT EtEING 

MATCHED , ., 
ADDRESSING TO STACK 
FOR THE STRING ebMI*ARE 
NUMBER TO TEST AGAlNSt 



SAVE CODE POII 



August i, 1984 



IBM Enhailli:6d Graphics Adapter 11*7 



17A3 


B9 0008 


17A6 


F3/ A6 


17A8 


5F 


17A9 


5E 


17AA 


71 ID 


17AC 


FE CO 


17AE 


83 C7 08 


17B1 


4A 


17B2 


75 ED 



17Blt 3C 00 



17B8 


E8 


OCFE R 


17BB 


CU 


3E 007C R 


17BF 


8C 


CO 


17C1 


OB 


C7 


17C3 


7U 


OU 


17C5 


BO 


80 


17C7 


EB 


D3 


17C9 






17C9 


83 


c^ 08 


17CC 


E9 


219E R 


17CF 







17CF 






17CF 


E9 


1701 R 


17D2 






17D2 


8A 


26 0U49 R 


17D6 


80 


FC 07 


17D9 


74 


FU 


17DB 


80 


FC 03 


17DE 


76 


EF 


17E0 


80 


FC 06 


17E3 


77 


03 


17E5 


E9 


17U5 R 


17E8 






17E8 


80 


FC OF 


17EB 


72 


52 


17ED 


E8 


mF7 R 


17F0 


72 


UD 


17F2 


EB 


OA 


17Fit 


80 


FC OD 


17F7 


73 


U6 


17F9 


BO 


00 


17FB 


E9 


219E R 



7FE 


BA AOOO 


801 


8E C2 


803 


E8 16BA R 


806 


8B FO 


«()8 


8B IE 0U85 R 


80C 


2B E3 



180E 8B EC 



1810 


53 


1811 


24 01 


1813 


8A C8 


1815 


BO 05 


1817 


D2 EO 


1819 


B4 07 


181B 


B6 03 


1810 


B2 CE 


181F 


E8 0D15 R 


1822 


B8 0518 


1825 


E8 0D15 R 


1828 




1828 


26: 8A 04 


182B 


F6 DO 


182D 


88 46 00 


1830 


45 


1831 


03 36 044A R 


1835 


4B 


1836 


75 FO 


1838 


5B 


1839 


B8 0510 


183C 


EB 32 90 


183F 





183F 


BA AOOO 


1842 


8E C2 


1844 


E8 16BA R 


1847 


8B FO 


1849 


8B IE 0485 R 


184D 


2B E3 



184F 8B EC 



1851 


B6 03 


1853 


B2 CE 


1855 


B8 0508 


1858 


E8 0D15 R 


185B 


53 


185C 




185C 


26: 8A 04 


185F 


F6 DO 


1861 


88 46 00 


1864 


45 


1865 


03 36 044A R 


1869 


4B 


186A 


75 FO 



4285 
4286 
4287 
4288 
4289 
4290 
4291 
4292 
4293 
4294 
4295 
4296 
4297 
4298 
4299 
4300 
4301 
4302 
4303 
4304 
4305 
4306 
4307 
4308 
4309 
4310 
4311 
4312 
4313 
4314 
4315 
4316 
4317 
4318 
4319 
4320 
4321 
4322 
4323 
4324 
4325 
4326 
4327 
4328 
4329 
4330 
4331 
4332 
4333 
4334 
4335 
4336 
4337 
4338 
4339 
4340 
4341 
4342 
4343 
4344 
4345 
4346 
4347 
4348 
4349 
4350 
4351 
4352 
4353 
4354 
4355 
4356 
4357 
4358 
4359 
4360 
4361 
4362 
4363 
4364 
4365 
4366 
4367 
4368 
4369 
4370 
4371 
4372 
4373 
4374 
4375 
4376 
4377 
4378 
4379 
4380 
4381 
4382 
4383 
4384 
4385 
4386 
4387 
4388 
4389 
4390 
4391 
4392 
4393 
4394 
4395 
4396 
4397 
4398 
4399 
4400 
4401 
4402 
4403 
4404 
4405 
4406 
4407 
4408 
4409 
4410 



MOV 


ex. 8 


REPE 


CMPSB 


POP 


Dl 


POP 


SI 


JZ 


S18P 


INC 


AL 


ADD 


Dl,8 


DEC 


DX 


JNZ 


SUP 



NUMBER OF BYTES TO MATCH 
COMPARE THE 8 BYTES 
RECOVER THE POINTERS 

IF ZERO FLAG SET, 
THEN MATCH OCCURRED 
NO MATCH, MOVE TO NEXT 
NEXT CODE POINT 
LOOP CONTROL 
DO ALL OF THEM 



■ CHAR NOT MATCHED, MIGHT BE IN USER SUPPLIED SECOND HALF 



ASSUME 


DS:ABSO 


CALL 


DDS 


LES 


DI,EXT PTR 


MOV 


AX, ES 


OR 


AX,DI 


JZ 


S18P 


MOV 


AL,128 


JMP 


S16P 


CHARACTER IS FOUND 



IF NOT FOUND ) 



AL <> IF ONLY 1ST 

HALF SCANNED 
IF = 0, THEN ALL HAS 

BEEN SCANNED 



GET POINTER 

SEE IF THE PNTR EXISTS 
IF ALL 0, DOESN'T EXIST 
NO SENSE LOOKING 
ORIGIN FOR SECOND HALF 
GO BACK AND TRY FOR IT 



READJUST THE STACK, 

THROW AWAY SAVE 
ALL DONE 



READ CHARACTER/ATTRIBUTE AT CURRENT CURSOR POSITION 



READ_AC_CURRENT 





ASSUME 


DS:ABSO 




MOV 


AH, CRT MODE 




CMP 


AH,07H 




JE 


AH8S 




CMP 


AH,03H 




JBE 


AH8S 




CMP 


AH,06H 




JA 


Z 1 




JMP 


GRAPH ICS_READ 


Z_1 








CMP 


AH,OFH 




JB 


GRX RD2 




CALL 


MEM DET 




JC 


GRX RD2 




JMP 


sHORT GRX RD1 




CMP 


AH,ODH 




JAE 


GRX RD2 




MOV 


AL,0 




JMP 


V_RET 


GRX_ 


RD1 PROC 


NEAR 




ASSUME 


DS:ABSO 




SRLOAD 


ES,OAOOOH 




MOV 


DX, OAOOOH 




MOV 


ES,DX 




CALL 


GR CUR 




MOV 


SI, AX 




MOV 


BX, POINTS 




SUB 


SP,BX 




MOV 


BP.SP 


; — 


— GET VALUES FROM REGEN E 




PUSH 


BX 




AND 


AL, 1 




MOV 


CL,AL 




MOV 


AL,5 




SHL 


AL,CL 




MOV 


AH,G COLOR 




MOV 


DH,3 




MOV 


DL, GRAPH ADDR 




CALL 


OUT DX 




MOV 


AX,518H 




CALL 


OUT_DX 


S12_ 


1: 






MOV 


AL,ES:[SI ] 




NOT 


AL 




MOV 


SS:[BP],AL 




INC 


BP 




ADD 


SI, CRT COLS 




DEC 


BX 




JNZ 


S12 1 




POP 


BX 




MOV 


AX,510H 




JMP 


GRX_RECG 


GRX_ 


RD1 ENDP 




GRX_ 


RD2 PROC 


NEAR 




ASSUME 


DS:ABSO 




SRLOAD 


ES. OAOOOH 




MOV 


DX, OAOOOH 




MOV 


ES,DX 




CALL 


GR CUR 




MOV 


SI, AX 




MOV 


BX, POINTS 




SUB 


SP,BX 




MOV 


BP,SP 


.... 


— GET VALUES FROM REGEN E 




MOV 


DH,3 




MOV 


DL, GRAPH ADDR 




MOV 


AX, 508H 




CALL 


OUT DX 




PUSH 


BX 


S12 








MOV 


AL,ES:[SI] 




NOT 


AL 




MOV 


SS:[BP],AL 




INC 


BP 




ADD 


SI, CRT COLS 




DEC 


BX 




JNZ 


312 



GET THE CURRENT MODE 



REGEN SEGEMNT 



BYTE OFFSET INTO REGEN 
SAVE IN SI 
BYTES PER CHARACTER 
ALLOCATE SPACE TO SAVE 

THE READ CODE POINT 
POINTER TO SAVE AREA 



SAVE BYTES PER CHARACTER 

ODD OR EVEN BYTE 

USE FOR SHIFT 

COLOR COMP VALUE ( C0-C2 ) 

(C1-C3) IF ODD BYTE 

COLOR COMPARE REGISTER 



SET GRAPHICS CHIP 

READ MODE 

SET GRAPHICS CHIP 

GET FIRST BYTE 

SAVE IN STORAGE AREA 
NEXT LOCATION 
POINTER INTO REGEN 
LOOP CONTROL 
DO IT SOME MORE 
RECOVER BYTES PER CHAR 
UNDO READ MODE 
CHAR REGONTION ROUTINE 



REGEN SEGMENT 

BYTE OFFSET INTO REGEN 
SAVE IN SI 
BYTES PER CHARACTER 
ALLOCATE SPACE TO SAVE 

THE READ CODE POINT 
POINTER TO SAVE AREA 



GRAPHICS CHIP 

COLOR COMPARE 

SET THE REGISTER 

SAVE BYTES PER CHARACTER 

GET COLOR COMPARED BYTE 

ADJUST 

SAVE IN STORAGE AREA 

NEXT LOCATION 

POINTER INTO REGEN 

LOOP CONTROL 

DO IT SOME MORE 



138 IBM Enhanced Graphics Adapter 



August 2, 1984 



186C 
186D 
1870 



1870 


E8 0D15 R 


1873 


CU 3E 010C 


1877 


2B EB 


1879 


8B F5 


187B 


PC 


187C 


BO 00 


187E 


16 


187F 


IF 


1880 


BA 0100 


1883 




1883 


56 


188U 


57 


1885 


8B CB 


1887 


F3/ A6 


1889 


5F 


188A 


5E 


188B 


7U 07 


188D 


FE CO 


188F 


03 FB 


1891 


4A 


1892 


75 EF 


1894 




1894 


03 E3 


1896 


E9 219E R 



1899 


E8 


OCFE R 




189C 


8A 


26 


0449 R 




18A0 


80 


FC 


04 




18A3 


72 


08 






18A5 


80 


FC 


07 




18A8 


74 


03 






18AA 


EB 


74 


90 




18AD 










18AD 


E8 


16EB R 




18B0 


8A 


E3 






18B2 


50 








18B3 


51 








18B4 


E8 


1651 R 




18B7 


8B 


FB 






18B9 


59 








18BA 


5B 








18BB 


8B 


16 


0463 R 




18BF 


83 


C2 


06 




18C2 










18C2 


F6 


06 


0487 R 


04 


18C7 


74 


OB 






18C9 










18C9 


EC 








18CA 


A8 


01 






18CC 


75 


FB 






18CE 


FA 








18CF 










18CF 


EC 








18D0 


A8 


01 






1802 


74 


FB 






18D4 










18D4 


86 


C3 






18D6 


AB 








1807 


FB 








18D8 


E2 


E8 






18DA 


E9 


219E R 





8E4 


80 


FC 


04 


fiV.f 


7? 


08 




8F9 


80 


FC 


07 


8 EC 


74 


03 




BEE 


FB 


30 


90 


8F1 








an 


E8 


16EB R 



4411 
4412 
4413 
4414 
4415 
4416 
4417 
4418 
4419 
4420 
4421 
4422 
4423 
4424 
4425 
4(426 
4427 
4428 
4429 
4430 
4431 
4432 
4433 
4434 
4435 
4436 
4437 
4438 
4439 
4440 
4441 
4442 
4443 
4444 
4445 
4446 
4447 
4448 
4449 
4450 
4451 
4452 
4453 
4i»54 
4455 
4456 
4457 
4458 
4459 
4460 
4461 
4462 
4463 
4464 
4465 
4466 
4467 
4468 
4469 
4470 
4471 
4472 
4473 
4474 
4475 
4476 
4477 
4478 
4479 
4480 
4481 
4482 
4483 
4484 
4485 
4486 
4487 
4488 
4489 
4490 
4491 
4492 
4493 
4494 
4U95 
4496 
4497 
4498 
4499 
4500 
4501 
4502 
4503 
4504 
4505 
4506 
4507 
4508 
4509 
4510 
4511 
4512 
4513 
4514 
4515 
4516 
4517 
4518 
4519 
4520 
4521 
4522 
4523 
4524 
4525 
4526 
4527 
4528 
4529 
4530 
4531 
4532 
4533 
4534 
4535 
4536 



POP 

MOV 

GRX_RD2 ENDP 



C GRX_RECG: 



SAVE AREA HAS CHARACTER I 

CALL OUT_DX 

LES DI.GRX_SET 

SUB BP,BX 

MOV SI.BP 

CLD 

MOV AL,0 

PUSH SS 

POP DS 

MOV DX,256D 

PUSH SI 

PUSH Dl 

MOV CX,BX 

REPE CMPSB 

POP Dl 

POP SI 

JZ S18_5 



ADD 
DEC 
JNZ 



SET READ MODE BACK 
GET FONT DEFINITIONS 
ADJUST POINTER TO 
BEGINNING OF SAVE AREA 

ENSURE DIRECTION 

CODE POINT BEING MATCHED 

ADDRESSING TO STACK 

FOR THE STRING COMPARE 
NUMBER TO TEST AGAINST 

SAVE SAVE AREA POINTER 
SAVE CODE POINTER 
NUMBER OF BYTES TO MATCH 
COMPARE THE 8 BYTES 
RECOVER THE POINTERS 

IF ZFL SET, THEN MATCH 
OCCURRED 
NO MATCH, ON TO NEXT 
NEXT CODE POINT 
LOOP CONTROL 
DO ALL OF THEM 
AL=CHAR, I F NOT FOUND 
READJUST THE STACK 



■ WRITE CHARACTER/ATTRIBUTE AT CURRENT CURSOR POSITION 



WRITE_AC_CURRENT 

THIS ROUTINE WRITES THE ATTRIBUTE 

AND CHARACTER AT THE CURRENT CURSOR 

POSITION 
INPUT' 

(AH) = CURRENT CRT MODE 

(BH) = DISPLAY PAGE 

(CX) = COUNT OF CHARACTERS TO WRITE 

(AL) = CHAR TO WRITE 

(BL) = ATTRIBUTE OF CHAR TO WRITE 

(DS) = DATA SEGMENT 

(ES) = REGEN SEGMENT 
OUTPUT 

NONE 



ASSUME DS:ABSO 

CALL DOS 

MOV AH,CRT_MODE 

CMP AH, 4 

JC P6 

CMP AH. 7 

JE P6 

JMP GRAPHICS_WRITE 

CALL MK_ES 

MOV AH,BL 

PUSH AX 

PUSH CX 

CALL FIND_POSITION 

MOV D I , BX 

POP CX 

POP BX 

MOV DX,ADDR_6845 

ADD DX,6 

■WAIT FOR HORIZONTAL RETRACE 



IS THIS GRAPHICS 
IS THIS BW CARD 

: WRITE_AC_CONTINUE 

GET ATTRIBUTE TO AH 
SAVE ON STACK 
SAVE WRITE COUNT 

ADDRESS TO Dl REGISTEI 

: WRITE COUNT 

; CHARACTER IN BX REG 
GET BASE ADDRESS 
POINT AT STATUS PORT 



GET STATUS 

IS IT LOW 

WAIT UNTIL IT IS 

NO MORE INTERRUPTS 

GET STATUS 
IS IT HIGH 
WAIT UNTIL IT IS 

RECOVER THE CHAR/ATTR 
PUT THE CHAR/ATTR 
INTERRUPTS BACK ON 
AS MANY TIMES 



• WRITE CHARACTER ONLY AT CURRENT CURSOR POSITION 



WRITE_C_CURRENT 

THIS ROUTINE WRITES THE CHARACTER AT 

THE CURRENT CURSOR POSITION, ATTRIBUTE 

UNCHANGED 
INPUT 

(AH) = CURRENT CRT MODE 

(BH) = DISPLAY PAGE 

(CX) = COUNT OF CHARACTERS TO WRITE 

(AL) = CHAR TO WRITE 

(DS) = DATA SEGMENT 

(ES) = REGEN SEGMENT 



ASSUME 

CALL 

MOV 

CMP 
JC 
CMP 
JE 

JMP 

CALL 



DS:ABSO 

DOS 

AH,CRT_MODE 

AH, 4 
P10 
AH, 7 
P10 

GRAPHICS_WRITE 

MK_ES 



IS THIS GRAPHICS 
IS THIS BW CARD 



August 2, 1984 



IBM Enhanced Graphics Adapter 139 



18FII 


50 




18F5 


51 




18F6 


E8 


1651 R 


18F9 


88 


FB 


18FB 


59 




18FC 


5B 




18FD 


8B 


16 0463 R 


1901 


83 


C2 06 


1904 






1904 


F6 


06 0487 R 04 


1909 


74 


OB 


190B 






190B 


EC 




190C 


A8 


01 


190E 


75 


FB 


1910 


FA 




1911 






1911 


EC 




1912 


A8 


01 


1914 


74 


FB 


1916 






1916 


8A 


C3 


1918 


AA 




1919 


FB 




191A 


47 




191B 


E2 


E7 


191D 


E9 


219E R 



1920 






1920 


80 


FC 07 


1923 


72 


03 


1925 


E9 


19D7 R 


1928 






1928 


E8 


16EB R 


192B 


B4 


00 


192D 


50 




192E 


E8 


16A4 R 


1931 


8B 


F8 


1933 


58 




1934 


3C 


80 


1936 


73 


06 


1938 


C5 


36 010C R 


193C 


EB 


06 


193E 






193E 


2C 


80 


1940 


C5 


36 007C R 


1944 






1944 


D1 


EO 


1946 


D1 


EO 


1948 


D1 


EO 


194A 


03 


FO 


194C 


IE 




194D 


E8 


OCFE R 


1950 


80 


3E 0449 R 06 


1955 


IF 




1956 


72 


2C 


1958 






1958 


57 




1959 


56 




195A 


B6 


04 


195C 






195C 


AC 




195D 


F6 


C3 80 


1960 


75 


16 


1962 


AA 




1963 


AC 




1964 






1964 


26 


88 85 1FFF 


1969 


83 


C7 4F 


196C 


FE 


CE 


196E 


75 


EC 


1970 


5E 





4537 
4538 
4539 
4540 
4541 
4542 
4543 
4544 
4545 
4546 
4547 
4548 
4549 
4550 
4551 
4552 
4553 
4554 
4555 
4556 
4557 
4558 
4559 
4560 
4561 
4562 
4563 
4564 
4565 
4566 
4567 
4568 
4569 
4570 
4571 
4572 
4573 
4574 
4575 
4576 
4577 
4578 
4579 
4580 
4581 
4582 
4583 
4584 
4585 
4586 
4587 
4588 
4589 
4590 
4591 
4592 
4593 
4594 
4595 
4596 
4597 
4598 
4599 
4600 
4601 
4602 
4603 
4604 
4605 
4606 
4607 
4608 
4609 
4610 
4611 
4612 
4613 
4614 
4615 
4616 
4617 
4618 
4619 
4620 
4621 
4622 
4623 
4624 
4625 
4626 
4627 
4628 
4629 
4630 
4631 
4632 
4633 
4634 
4635 
4636 
4637 
4638 
4639 
4640 
4641 
4642 
4643 
4644 
4645 
4646 
4647 
4648 
4649 
4650 
4651 
4652 
4653 
4654 
4655 
4656 
4657 
4658 
4659 
4660 
4661 
4662 



PUSH AX 

PUSH CX 

CALL FIND_POSITION 

MOV D I , BX 

POP CX 

POP BX 

-WAIT FOR HORIZONTAL RETRACE 



ADDRESS TO 01 

WRITE COUNT 

BL HAS CHAR TO WRITE 



GET STATUS 
IS IT LOW 
WAIT UNTIL IT IS 
NO MORE INTERRUPTS 

GET STATUS 
IS IT HIGH 
WAIT UNTIL IT IS 

RECOVER CHAR 
PUT THE CHAR/ATTR 
INTERRUPTS BACK ON 
BUMP POINTER PAST ATTR 
AS REQUESTED 



GRAPHICS WRITE 

THIS ROUTINE WRITES THE ASCII CHARACTER TO THE 

CURRENT POSITION ON THE SCREEN. 
ENTRY 

AL = CHARACTER TO WRITE 

BL = COLOR ATTRIBUTE TO BE USED FOR FOREGROUND COLOR 
IF BIT 7 IS SET, THE CHAR IS XOR'D INTO THE REGEN 
BUFFER (0 IS USED FOR THE BACKGROUND COLOR) 

CX = NUMBER OF CHARS TO WRITE 

DS = DATA SEGMENT 

ES = REGEN SEGMENT 
EXIT 

NOTHING IS RETURNED 

GRAPHICS READ 

THIS ROUTINE READS THE ASCII CHARACTER AT THE CURRENT 
CURSOR POSITION ON THE SCREEN BY MATCHING THE DOTS ON 
THE SCREEN TO THE CHARACTER GENERATOR CODE POINTS 

ENTRY 

NONE (0 18 ASSUMED AS THE BACKGROUND COLOR) 



FOR COMPATIBILITY ROUTINES, THE IMAGES USED TO FORM CHARS ARE 
CONTAINED IN ROM FOR THE 1ST 128 CHARS. TO ACCESS CHARS 
IN THE SECOND HALF, THE USER MUST INITIALIZE THE VECTOR AT 
INTERRUPT 1FH (LOCATION 0007CH) TO POINT TO THE USER 
SUPPLIED TABLE OF GRAPHIC IMAGES (8X8 BOXES). 
FAILURE TO DO SO WILL CAUSE IN STRANGE RESULTS 



ASSUME 
GRAPHICS_WRITE 
CMP 



CALL 
MOV 
PUSH 



DETERMINE POSITION IN REGEN BUFFER TO PUT CODE POINTS 



DETERMINE REGION TO GET CODE POINTS FROM 

POP AX 
CMP AL,80H 
JAE SI 

IMAGE IS IN FIRST HALF, CONTAINED IN ROM 



IMAGE IS IN SECOND HALF, IN USER RAM 



DETERMINE GRAPHICS MODE IN OPERATION 



SAL 


AX, 1 


SAL 


AX, 1 


SAL 


AX,1 


ADD 


SI, AX 


PUSH 


DS 


CALL 


DOS 


CMP 


CRT MODE, 6 


POP 


DS 



■HIGH RESOLUTION MODE 



PUSH 
PUSH 
MOV 

LODSB 

TEST 

JNZ 

STOSB 

LODSB 



MOV 
ADD 
DEC 
JNZ 
POP 



ES:[DI+2000H-1],AL 



RECOVER CODE POINT 
IS IT IN SECOND HALF 
YES 



DETERMINE_MODE 



DETERMINE_MODE 
MULTIPLY CODE POINT 
VALUE BY 8 



TEST FOR MEDIUM RES MODE 



H I GH_CHAR 
SAVE REGEN POINTER 
SAVE CODE POINTER 
NUMBER OF TIMES THROUGH 

LOOP 
GET BYTE FROM CODE POINT 
SHOULD WE USE THE 

FUNCTION TO PUT CHAR IN 
STORE IN REGEN BUFFER 



STORE IN SECOND HALF 
MOVE TO NEXT ROW IN REGEN 
DONE WITH LOOP 



140 IBM Enhanced Graphics Adapter 



August 2, 1984 



1971 


5F 




1972 


47 




1973 


E2 E3 




1975 


E9 219E R 




1978 






1978 


26: 32 05 




197B 


AA 




197C 


AC 




197D 


26: 32 85 


1FFF 


1982 


EB EG 




1984 






198U 


8A D3 




1986 


D1 E7 




1988 


E8 166D R 




198B 






198B 


57 




198C 


56 




198D 


B6 Ok 




198F 






198F 


AC 




1990 


E8 1682 R 




1993 


23 03 




1995 


F6 C2 80 




1998 


7U 07 




199A 


26: 32 25 




199D 


26: 32 45 


01 


19A1 






19A1 


26: 88 25 




19AU 


26: 88 45 


01 


19A8 


AC 




19A9 


E8 1682 R 




19AC 


23 03 




19AE 


F6 02 80 




19B1 


74 OA 




19B3 


26: 32 A5 


2000 


19B8 


26: 32 85 


2001 


19BD 






19BD 


26: 88 A5 


2000 


19C2 


26: 88 85 


2001 


19C7 


83 07 50 




19CA 


FE CE 




19CC 


75 01 




19CE 


5E 




19CF 


5F 




19D0 


47 




19D1 


47 




19D2 


E2 87 




19DU 


E9 219E R 




19D7 







19D7 


80 


FC OF 


19DA 


72 


OE 


19DC 


E8 


14F7 R 


19DF 


72 


09 


19E1 


80 


E3 85 


19E4 


8A 


E3 


19E6 


DO 


E4 


19E8 


OA 


DC 


19EA 






19EA 


2A 


E4 


19E0 


F7 


26 0485 R 


19F0 


50 




19F1 


E8 


16BA R 


19F4 


8B 


F8 


19F6 


8B 


2E 0485 R 


19FA 


BA 


AOOO 


19FD 


8E 


02 


19FF 


05 


36 0100 R 


1A03 


58 




1A04 


03 


FO 


1A06 


B6 


03 


1A08 






1A08 


F6 


03 80 


1A0B 


74 


OB 


1A0D 


B2 


OE 


1A0F 


B8 


0318 


1A12 


E8 


0D15 R 


1A15 


EB 


IE 90 


1A18 






1A18 


57 




1A19 


B2 


04 


1A1B 


B8 


020F 


1A1E 


E8 


0D15 R 


1A21 


2B 


00 


1A23 


51 




1A24 


8B 


OD 


1A26 


IE 




1A27 


E8 


OCFE R 


1A2A 






1A2A 


AA 




1A2B 


03 


3E 044A R 


1A2F 


4F 




1A30 


E2 


F8 


1A32 


IF 




1A33 


59 




1A34 


5F 




1A35 






1A35 


B2 


04 


1A37 


B4 


02 


1A39 


8A 


03 


1A3B 


E8 


0D15 R 


1A3E 


57 




1A3F 


53 




1A40 


51 




1A41 


8B 


DD 


1A43 


IE 




1A44 


E8 


OCFE R 


1A47 


8B 


OE 044A R 


1A4B 


IF 





4663 
4664 
4665 
4666 
4667 
4668 
4669 
4670 
4671 
4672 
4673 
4674 
4675 
4676 
4677 
4678 
4679 
4680 
4681 
4682 
4683 
4684 
4685 
4686 
4687 
4688 
4689 
4690 
4691 
4692 
4693 
4694 
4695 
4696 
4697 
4698 
4699 
4700 
4701 
4702 
4703 
4704 
4705 
4706 
4707 
4708 
4709 
4710 
4711 
4712 
4713 
4714 
4715 
4716 
4717 
4718 
4719 
4720 
4721 
4722 
4723 
4724 
4725 
4726 
4727 
4728 
4729 
4730 
4731 
4732 
4733 
4734 
4735 
4736 
4737 
4738 
4739 
4740 
4741 
4742 
4743 
4744 
4745 
4746 
4747 
4748 
4749 
4750 
4751 
4752 
4753 
4754 
4755 
4756 
4757 
4758 
4759 
4760 
4761 
4762 
4763 
4764 
4765 
4766 
4767 
4768 
4769 
4770 
4771 
4772 
4773 
4774 
4775 
4776 
4777 
4778 
4779 
4780 
4781 
4782 
4783 
4784 
4785 
4786 
4787 
4788 



LOOP 


S3 


JMP 


V_RET 


XOR 


AL, ES:{DI ] 


STOSB 




LODSB 




XOR 


AL,ES:[DI+2000H-11 


JMP 


35 


MEDIUM 


RESOLUTION WRITE 


.7: 

MOV 


DL, BL 


SAL 


Dl,1 


CALL 


319 


PUSH 


Dl 


PUSH 


SI 


MOV 


DH,4 


LODSB 




CALL 


S21 


AND 


AX,BX 


TEST 


DL,80H 


JZ 


S10 


XOR 


AH,ES:[DI] 


XOR 


AL,ES:[DI+1] 


>10: 




MOV 


ES:IDI],AH 


MOV 


ES:[DI+1 1,AL 


LODSB 




CALL 


321 


AND 


AX.BX 


TEST 


DL,80H 


JZ 


S11 


XOR 


AH,ES:[DI+2000H] 


XOR 


AL,ES:IDI+2001H] 


511: 




MOV 


E3:[DI+2000H],AH 


MOV 


E3:[DI+2000H+1],AL 


ADD 


Dl,80 


DEC 


DH 


JNZ 


S9 


POP 


SI 


POP 


Dl 


INC 


Dl 


INC 


Dl 


LOOP 


38 


JMP 


V RET 


3RAPHICS WRITE 


ENDP 



: CHAR TO WRITE 

: DISPLAY PAGE 

: ATTRIBUTE/COLOR 

: COUNT OF CHARS TO WRITE 



C GRX_WRT PROC 
C ASSUME 

C CMP 



AND 
MOV 
SHL 



OR 
I : 
SUB 
MUL 
PUSH 
CALL 
MOV 
MOV 

SRLOAD 
MOV 
MOV 
LDS 
POP 
ADD 
MOV 

TEST 

JZ 

MOV 

MOV 

CALL 

JMP 

PUSH 
MOV 
MOV 
CALL 
SUB 
PUSH 
MOV 
PUSH 
CALL 

STOSB 

ADD 

DEC 

LOOP 

POP 

POP 

POP 

MOV 

MOV 

MOV 

CALL 

PUSH 

PUSH 

PUSH 

MOV 

PUSH 

CALL 

ASSUME 

MOV 

POP 

ASSUME 



NEAR 

DS:ABSO, ES: NOTHING 

AH,OFH 

NO_ADJ 1 

MEM_DET 

NO_ADJ 1 

BL, 10000101B 

AH,BL 

AH,1 

BL,AH 



GR_CUR 
DI,AX 
BP, POINTS 
ES,0A000H 
DX, OAOOOH 
ES.DX 

SI,GRX_SET 
AX 



BL,080H 

NO_XOR 

DL,GRAPH_ADDR 

AX,0318H 

OUT_DX 

F_2 



DL, SEQ_ADDR 
AX,020FH 
0UT_DX 
AX, AX 



D I , CRT_00LS 



DL, SEQ_ADDR 
AH,02H 
AL,BL 
0UT_DX 



DOS 

DS:ABSO 

CX,CRT_COLS 



RECOVER REGEN POINTER 
POINT TO NEXT CHAR PCS 
MORE CHARS TO WRITE 



XOR WITH CURRENT 
STORE THE CODE POINT 
AGAIN FOR ODD FIELD 

BACK TO MAINSTREAM 



MED_RES_WRITE 
SAVE HIGH COLOR BIT 
0FFSET»2, 2 BYTES/CHAR 
EXPAND BL TO FULL WORD 

OF COLOR 
SAVE REGEN POINTER 
SAVE THE CODE POINTER 
NUMBER OF LOOPS 

GET CODE POINT 
DOUBLE UP ALL THE BITS 
CONVERT THEM TO FORE- 
GROUND COLOR (0 BACK) 
IS THIS XOR FUNCTION 
NO, STORE IT IN A3 IT IS 
DO FUNCTION WITH HALF 
AND WITH OTHER HALF 

STORE FIRST BYTE 
STORE SECOND BYTE 
GET CODE POINT 

CONVERT TO COLOR 

IS THIS XOR FUNCTION 

NO, JUST STORE THE VALUE 

FUNCTION WITH FIRST HALF 

AND WITH SECOND HALF 



KEEP GOING 
RECOVER CODE PONTER 
RECOVER REGEN POINTER 
POINT TO NEXT CHAR 

MORE TO WRITE 



640X350 GRAPHICS 

BASE CARD 

85H, XOR C2 CO MASK 



ZERO 

OFFSET FONT TABLE BASE 
FONT TABLE DISPLACEMENT 
GET OFFSET INTO REGEN 

INTO DESTINATION 
BYTES PER CHAR 
REGEN SEGEMNT 



ADDRESSING TO FONTS 
RECOVER OFFSET 
CHARACTER IN TABLE 



GRAPHICS CHIP XOR 
SET REGISTER 
SKIP BLANK 
BLANK BOX FOR CHAR 
SAVE REGEN POINTER 

ENABLE ALL MAPS 

STORE ZERO 

SAVE CHARACTER COUNT 

GET BYTE COUNT 



ZERO REGEN BYTE 
NEXT BYTE OF BOX 
ADJUST 
NEXT BYTE 



SET MAP MASK 

FOR COLOR 
SET THE CHIP 
SAVE OFFSET IN REGEN 
SAVE COLOR VALUE 
SAVE CHACTER COUNT 
LOOP CONTROL, BYTES/CHAR 
SAVE FONT SEGMENT 
SET LOW RAM SEGMENT 



WRITE OUT THE CHARACTER 



August 2, 1984 



IBM Enhanced Graphics Adapter 141 



TMC 


8A 


04 


1AUE 


26 


8A 25 


1A51 


26 


88 05 


1A54 


46 




1A55 


03 


F9 


1A57 


UB 




1A58 


75 


F2 


1A5A 


59 




1A5B 


58 




1A5C 


28 


F5 


lASE 


5F 




1A5F 


47 




1A60 


E2 


A6 


1A62 


82 


CE 


1A6U 


88 


0300 


1A67 


E8 


0D15 R 


1A6A 


82 


C4 


1A6C 


88 


020 F 


1A6F 


E8 


0015 R 


1A72 


E9 


219E R 


1A75 







1A75 


80 3E 0463 R 84 


1A7A 


74 09 


1A7C 


F6 06 0487 R 02 


1A81 


74 05 


1A83 


CD 42 


1A85 




1A85 


E9 219E R 


1A88 




1A88 


28 CO 


1A8A 


88 E8 


1A8C 


C4 3E 04A8 R 


1A90 


83 C7 04 


1A93 


26: C4 3D 


1A96 


80 CO 


1A98 


08 C7 


1A9A 


74 01 


1A9C 


45 


1A9D 




1A9D 


E8 1DC0 R 


1AA0 


OA FF 


1AA2 


75 65 



1AA4 


8A FB 




1AA6 


AO 0466 R 




1AA9 


24 EO 




1AAB 


80 E3 IF 




1AAE 


OA C3 




1AB0 


A2 0466 R 




1A83 
1AB5 
1A88 


8A DF 
80 E7 08 
DO E7 




1ABA 


8A E8 




1ABC 
1ABF 


80 E5 EF 
OA ED 




1AC1 


80 E3 OF 




1AC4 


8A FB 




1AC6 


DO E3 




1AC8 


80 E3 10 




1ACB 


80 E7 07 




1ACE 


OA DF 




1AD0 


AO 0449 R 




1AD3 


3C 03 




1AD5 


76 OE 




1AD7 


84 00 




1AD9 


8A C3 




1ADB 


E8 1D9F R 




1ADE 


OB ED 




1AE0 


74 03 




1AE2 


26: 88 ID 




1AE5 






1AE5 


80 3E 0449 R 


03 


IAEA 


77 05 




1AEC 


E8 0E9A R 




1AEF 


72 07 




1AF1 






1AF1 


84 11 




1AF3 


8A C3 




1AF5 


E8 1D9F R 




1AF8 






1AF8 


OB ED 




1AFA 


74 04 




1AFC 


26: 88 5D 10 




1800 






1800 


8A DO 




1802 


80 E3 20 




1805 


81 05 




1807 


D2 EB 





4789 
4790 
4791 
4792 
4793 
4794 
4795 
4796 
4797 
4798 
4799 
4800 
4801 
4802 
4803 
4804 
4805 
4806 
4807 



4812 
4813 
4814 
4815 
4816 
4817 
4818 
4819 
4820 
4821 
4822 
4823 
4824 
4825 
4826 
4827 
4828 
4829 
4830 
4831 
4832 
4833 
4834 
4835 
4836 
4837 
4838 
4839 
4840 
4841 
4842 
4843 
4844 
4845 
4846 
4847 
4848 
4849 
4850 
4851 
4852 
4853 
4854 
4855 
4856 
4857 
4858 
4859 
4860 
4861 
4862 
4863 
4864 
4865 
4866 
4867 
4868 
4869 
4870 
4871 
4872 
4873 
4874 
4875 
4876 
4877 
4878 
4879 
4880 
4881 
4882 
4883 
4884 
4885 
4886 
4887 
4888 
4889 
4890 
4891 
4892 
4893 
4894 
4895 
4896 
4897 
4898 
4899 
4900 
4901 
4902 
4903 
4904 
4905 
4906 
4907 
4908 
4909 
4910 
4911 
4912 
4913 
4914 



MOV 


AL,DS: SI] 


MOV 


AH,ES: Dl] 


MOV 


ES:[DI ,AL 


INC 


SI 


ADD 


DI,CX 


DEC 


BX 


JNZ 


S1K 


POP 


CX 


POP 


BX 


SUB 


SI.BP 


POP 


Dl 


INC 


Dl 


LOOP 


S20A 


MOV 


DL, GRAPH ADDR 


MOV 


AX,0300H 


CALL 


OUT DX 


MOV 


DL.SEQ ADDR 


MOV 


AX,020FH 


CALL 


OUT DX 


JMP 


V RET 


GRX_WRT ENDP 




SUBTTL 




; SET COLOR PALETTE 


AHB: 




ASSUME 


DSrABSO 


CMP 


BYTE PTR ADDR 6845, 0B4H 


JE 


M21 B 


TEST 


INFO, 2 



CODE POINT 

LATCH DATA 

WRITE ONE BYTE OF FONT 

NEXT FONT POINT 

ONE ROW BELOW LAST POINT 

BYTES PER CHAR COUNTER 

DO NEXT ROW OF CHARACTER 

CHARACTER COUNT 

COLOR VALUE 

ADJUST PTR TO FONT TABLE 

REGEN POINTER 

NEXT CHAR POSN IN REGEN 

WRITE ANOTHER CHARACTER 



NO ROTATE 



CALL VALID ONLY FOR COLOR 
SEE IF ITS THE OLD COLOR CARD 
IF NOT, HANDLE IT HERE 
OLD CODE CALL 

BACK TO CALLER 



SUB 


AX, AX 


MOV 


8P,AX 


LES 


DI,SAVE PTR 


ADD 


Dl,4 


LES 


Dl, DWORD PTR ES:[D 


MOV 


AX, ES 


OR 


AX,DI 


JZ 


N0T4AHB 


INC 


BP 


CALL 


PAL IN IT 


OR 


8H,8H 


JNZ 


M20 



■ HANDLE 8H = HERE 

ALPHA MODES => BL = OVERSCAN COLOR 

GRAPHICS => BL = OVERSCAN AND BACKGROUND COLOR 

■ MOVE INTENSITY BIT FROM D3 TO D4 FOR COMPATIBILITY 



MOV 


BH.BL 


MOV 


AL,CRT PALETTE 


AND 


AL,OEOH 


AND 


BL,01FH 


OR 


AL,8L 


MOV 


CRT PALETTE, AL 


MOV 


BL,BH 


AND 


BH,08H 


SHL 


BH,1 


MOV 


CH,AL 


AND 


CH,OEFH 


OR 


CH,CH 


AND 


8L.0FH 


MOV 


BH,BL 


SHL 


BL, 1 


AND 


BL,010H 


AND 


BH,07H 


OR 


BL.BH 


MOV 


AL,CRT MODE 


CMP 


AL,3 


JBE 


M21 



■ GRAPHICS MODE DONE HERE (SET PALETTE AND OVERSCAN) 

MOV AH,0 
MOV AL, BL 
CALL PAL_SET 



• ALPHA MODE DONE HERE (SET OVERSCAN REGISTER) 



CMP 


CRT MODE, 3 


JA 


SET OVRSC 


CALL 


BRST DET 


JC 


SKIP_OVRSC 


SET OVRSC: 




MOV 


AH,011H 


MOV 


AL,BL 


CALL 


PAL SET 


SKIP OVRSC: 





CHECK FOR AN ENHANCED MODE 
NO CHANCE 

SEE IF WE ARE ENHANCED 
THERE IS NO BORDER 

OVERSCAN REGISTER 

SET THE BORDER 



ES:[DI ][16D1,BL 



MOV 


BL,CH 


AND 


BL,020H 


MOV 


CL.5 


SHR 


BL,CL 


. HANDLE 


BH = 1 HERE 


; ALPHA 


MODES => NO EFFECT 


; GRAPH 


CS => LOW BIT OF BL = 




PALETTE = BACKGROUND 




PALETTE 1 = GREEN 




PALETTE 2 = RED 




PALETTE 3 = BROWN 




=> LOW BIT OF BL = 1 




PALETTE = BACKGROUND 




PALETTE 1 = CYAN 




PALETTE 2 = MAGENTA 


; 


PALETTE 3 = WHITE 



142 IBM Enhanced Graphics Adapter 



August 2, 1984 



1B09 




1B09 


80 3E 04U9 R 03 


1B0E 


76 4A 


1B10 


AO 0U66 R 


1B13 


2U DP 


1B15 


80 E3 01 


1B18 


7U 02 


1B1A 


OC 20 


1B1C 




1B1C 


A2 0U66 R 


1B1F 


24 10 


1B21 


OC 02 


1B23 


OA D8 


1B25 


BU 01 


1B27 


8A C3 


1B29 


E8 1D9F R 


1B2C 


OB ED 


1B2E 


74 04 


1B30 


26: 88 5D 01 


1B34 




1B3U 


FE C3 


1B36 


FE 03 


1B38 


B4 02 


1B3A 


8A 03 


1B3C 


E8 1D9F R 


1B3F 


OB ED 


1BU1 


74 04 


1B43 


26: 88 5D 02 


1BU7 




1BU7 


FE C3 


1B49 


FE 03 


1B4B 


B4 03 


1BUD 


8A 03 


1BUF 


E8 1D9F R 


1B52 


OB ED 


1B5U 


74 04 


1B56 


26: 88 5D 03 


1B5A 




1B5A 


E8 1DB7 R 


1B5D 


E9 219E R 



1B60 


F7 


?6 


044A R 


1B64 


■)1 






1B65 


D1 


L9 




1B67 


U1 


t9 




1B69 


D1 


E9 




1B6B 


03 


01 




1B60 


8A 


DP 




1B6F 


?A 


FP 




1B71 


«B 


OB 




1B73 


8B 


U 


044C R 


1B77 


K3 


04 




1B79 








1B79 


03 


03 




1B7B 


E2 


PC 




1B7D 








1B7D 


•><) 






1B7E 


«B 


1)8 




1B80 


80 


F1 


07 


1B83 


BO 


fiO 




1B85 


D? 


PR 




1B87 


C3 






1B88 









1B8A BO 28 

1B8C 52 

1B8D 80 E2 FE 

1B90 F6 E2 



1B93 P6 02 01 
1B96 74 03 
1B98 05 2000 



1B9E 8B 01 



4915 
4916 
4917 
4918 
4919 
4920 
4921 
4922 
4923 
4924 
4925 
4926 
4927 
4928 
4929 
4930 
4931 
4932 
4933 
4934 
4935 
4936 
4937 
4938 
4939 
4940 
4941 
4942 
4943 
4944 
4945 
4946 
4947 
4948 
4949 
4950 
4951 
4952 
4953 
4954 
4955 
4956 
4957 
4958 
4959 
4960 
4961 
4962 
4963 
4964 
4965 
4966 
4967 
4968 
4969 
4970 
4971 
4972 
4973 
4974 
4975 
4976 
4977 
4978 
4979 
4980 
4981 
4982 
4983 
4984 
4985 
4986 
4987 
4988 
4989 
4990 
4991 
4992 
4993 
4994 
4995 
4996 
4997 
4998 
4999 
5000 
5001 
5002 
5003 
5004 
5005 
5006 
5007 
5008 
5009 
5010 
5011 
5012 
5013 
5014 
5015 
5016 
5017 
5018 
5019 
5020 
5021 
5022 
5023 
5024 
5025 
5026 
5027 
5028 
5029 
5030 
5031 
5032 
5033 
5034 
5035 
5036 
5037 
5038 
5039 
5040 



CMP 


CRT MODE, 3 


JBE 


M80 


MOV 


AL,CRT PALETTE 


AND 


AL,0DFH 


AND 


BL.1 


JZ 


M22 


OR 


AL,020H 


MOV 


CRT PALETTE, AL 


AND 


AL,010H 


OR 


AL,2 


OR 


BL,AL 


MOV 


AH,1 


MOV 


AL,BL 


CALL 


PAL_SET 


OR 


BP,BP 


JZ 


M22Y 


MOV 


ES:[DI][1],BL 



MOV 
MOV 
CALL 



MOV AH, 3 
MOV AL, BL 
CALL PAL_SET 



ES:[DI ][3],BL 



INCLUDE 
SUBTTL VDOT. 
PAGE 

DX = ROW 
CX = COLUMN 
BH = PAGE 



D0T_SUP 


_1 


PROC NEA 




OFFSET 


= PAGE OFFSET 




MUL 


WORD PTR CR 




PUSH 


CX 




SHR 


CX, 1 




SHR 


CX, 1 




SHR 


CX, 1 




ADD 


AX,CX 




MOV 


BL, BH 




SUB 


BH,BH 




MOV 


CX, BX 




MOV 


BX,CRT LEN 




JCXZ 


DS 2 


DS 3: 








ADD 


AX, BX 




LOOP 


DS 3 


DS 2: 








POP 


CX 




MOV 


BX,AX 




AND 


CL,07H 




MOV 


AL,080H 




SHR 


AL,CL 




RET 




DOT SUP 




ENDP 



• ROW • BYTES/ROW + COLUMN/8 



ROW » BYTES/ROW 
SAVE COLUMN VALUE 
DIVIDE BY EIGHT TO 

DETERMINE THE BYTE THAT 

THIS DOT IS IN 

(8 BITS/BYTE) 
BYTE OFFSET INTO PAGE 
GET PAGE INTO BL 
ZERO 

COUNT VALUE 
LENGTH OF ONE PAGE 
PAGE ZERO 



RECOVER COLUMN VALUE 

REGEN OFFSET 

SHIFT COUNT FOR BIT MASK 

MASK BIT 

POSITION MASK BIT 



THIS SUBROUTINE DETERMINES THE REGEN BYTE LOCATION 

OF THE INDICATED ROW COLUMN VALUE IN GRAPHICS MODE. 

ENTRY — 
DX = ROW VALUE (0-199) 
CX = COLUMN VALUE (0-639) 

EXIT — 
SI = OFFSET INTO REGEN BUFFER FOR BYTE OF INTEREST 
AH = MASK TO STRIP OFF THE BITS OF INTEREST 
CL = BITS TO SHIFT TO RIGHT JUSTIFY THE MASK IN AH 
DM = # BITS IN RESULT 



PROC 
PUSH 
PUSH 



MOV 
PUSH 
AND 
MUL 



MOV 
POP 
MOV 



NEAR 



SAVE ROW VALUE 

STRIP OFF ODD/EVEN BIT 

AX HAS ADDRESS OF 1ST BYTE 

OF INDICATED ROW 
RECOVER IT 
TEST FOR EVEN/ODD 
JUMP IF EVEN ROW 
OFFSET TO LOCATION OF ODD ROWS 
EVEN_ROW 

MOVE POINTER TO SI 
RECOVER AL VALUE 
COLUMN VALUE TO DX 



■ DETERMINE GRAPHICS MODE CURRENTLY IN EFFECT 



August 2, 1984 



IBM Enhanced Graphics Adapter 143 



1BA0 


BB 02C0 


1BA3 


B9 0302 


1BA6 


80 3E 0^^9 R 06 


1BAB 


72 06 


1BAD 


BB 0180 


1BB0 


B9 0703 



1BB5 


D3 EA 


1BB7 


03 F2 


1BB9 


8A F7 



1BBB 2A C9 

1BBD 

1BBD DO C8 



1BBF 


OP 


cn 


1BC1 


KF- 


CF 


1BC3 


fi> 


F8 


1BC5 


BA 


E3 


1BC7 


1)2 


FO 


1BC9 


5B 




1BCA 


C3 




1BCB 







1BCB 
IBDO 


80 3E 0449 R 07 
77 2A 


1BD2 




1BD2 


52 


1BD3 
1BD6 


BA B800 
8E C2 



1BDB E8 1B88 R 



1BDE 


D2 E8 




1BE0 


22 CU 




1BE2 


26: 8A OC 




1BE5 


5B 




1BE6 


F6 C3 80 




1BE9 


75 OD 




1BEB 


F6 04 




1BED 


22 CC 




1BEF 


OA CI 




1BF1 






1BF1 


26: 88 04 




1BF«4 


58 




1BF5 


E9 219E R 




1BF8 






1BF8 


32 CI 




1BFA 


EB F5 




1BFC 






1BFC 






1BFC 


80 3E 0449 


R OF 


1C01 


72 OD 




1C03 


E8 14F7 R 




1C06 


72 08 




1C08 


24 85 




1C0A 


8A EO 




1C0C 


DO E4 




1C0E 


OA 04 




1C10 






1C10 


50 




1C11 


8B C2 




1C13 


E8 1B60 R 




1C16 


B6 03 




1C18 


B2 CE 




1C1A 


B4 08 




1C1C 


E8 0D15 R 




1C1F 


52 




1C20 


BA AOOO 




1C23 


8E 02 




1C25 


5A 




1C26 


58 




1C27 


8A E8 




1C29 


F6 05 80 




1C2C 


74 OA 




1C2E 


B4 03 




1C30 


BO 18 




1C32 


E8 0D15 R 




1C35 


EB 12 90 




1C38 






1C38 


B2 04 




1C3A 


B4 02 




1C3C 


BO FF 




1C3E 


E8 0D15 R 





5041 
5042 
5043 
5044 
5045 
5046 
5047 
5048 
5049 
5050 
5051 
5052 
5053 
5054 
5055 
5056 
5057 
5058 
5059 
5060 
5061 
5062 
5063 
5064 
5065 
5066 
5067 
5068 
5069 
5070 
5071 
5072 
5073 
5074 
5075 
5076 
5077 
5078 
5079 
5080 
5081 
5082 
5083 
5084 
5085 
5086 
5087 
5088 
5089 
5090 
5091 
5092 
5093 
5094 
5095 
5096 
5097 
5098 
5099 
5100 
5101 
5102 
5103 
5104 
5105 
5106 
5107 
5108 
5109 
5110 
5111 
5112 
5113 
5114 
5115 
5116 
5117 
5118 
5119 
5120 
5121 
5122 
5123 
5124 
5125 
5126 
5127 
5128 
5129 
5130 
5131 
5132 
5133 
5134 
5135 
5136 
5137 
5138 
5139 
5140 
5141 
5142 
5143 
5144 
5145 
5146 
5147 
5148 
5149 
5150 
5151 
5152 
5153 
5154 
5155 
5156 
5157 
5158 
5159 
5160 
5161 
5162 
5163 
5164 
5165 
5166 



OL = # OF ADDRESS BITS IN COLUMN VALUE ( 3/2 FOR H/M) 

BL = MASK TO SELECT BITS FROM POINTED BYTE (80H/C0H FOR H/M) 

BH = NUMBER OF VALID BITS IN POINTED BYTE ( 1/2 FOR H/M) 



SET PARMS FOR MED RES 



MOV 


BX,2C0H 


MOV 


CX, 302H 


CMP 


CRT MODE, 6 


JC 


R5 


MOV 


BX, 180H 


MOV 


CX,703H 



HANDLE IF MED ARES 
SET PARMS FOR HIGH RES 



■ DETERMINE BIT OFFSET IN BYTE FROM COLUMN MASK 



ADDRESS OF PEL WITHIN BYTE TO CH 



■ DETERMINE BYTE OFFSET FOR THIS LOCATION IN COLUMN 



SHR DX,CL 
ADD S1,DX 
MOV DH.BH 



SHIFT BY CORRECT AMOUNT 

INCREMENT THE POINTER 

GET THE # OF BITS IN RESULT TO DH 



• MULTIPLY BH (VALID BITS IN BYTE) BY CH (BIT OFFSET) 



ADD 


CL,CH 


DEC 


BH 


JNZ 


R6 


MOV 


AH,BL 


SHR 


AH.CL 


POP 


BX 


RET 




ENDP 





ZERO INTO STORAGE LOCATION 

LEFT JUSTIFY THE VALUE 

IN AL (FOR WRITE) 
ADD IN THE BIT OFFSET VALUE 
LOOP CONTROL 
ON EXIT, CL HAS SHIFT COUNT 

TO RESTORE BITS 
GET MASK TO AH 

MOVE THE MASK TO CORRECT LOCATION 
RECOVER REG 
RETURN WITH EVERYTHING SET UP 



READ DOT -- WRITE DOT 

THESE ROUTINES WILL WRITE A DOT, OR READ THE DOT AT 

THE INDICATED LOCATION 
ENTRY — 

DX = ROW (0-199) (THE ACTUAL VALUE DEPENDS ON THE MODE) 
CX = COLUMN ( 0-639) ( THE VALUES ARE NOT RANGE CHECKED ) 
AL = DOT VALUE TO WRITE (1,2 OR 4 BITS DEPENDING ON MODE, 

REQ'D FOR WRITE DOT ONLY, RIGHT JUSTIFIED) 

BIT 7 OF AL=1 INDICATES XOR THE VALUE INTO THE LOCATION 
DS = DATA SEGMENT 
ES = REGEN SEGMENT 

EXIT 

AL = DOT VALUE READ, RIGHT JUSTIFIED, READ ONLY 



; WRITE DOT 


AHO: 




ASSUME 


DS:ABSO 


CMP 


CRT_M0DE,7 


JA 


WRITE_D0T_2 


WRITE DOT 


PROC NEAR 


ASSUME 


DS:ABSO,ES: NOTHING 


PUSH 


DX 


SRLOAD 


ES,0B800H 


MOV 


DX,0B800H 


MOV 


ES.DX 


POP 


DX 


PUSH 


AX 


PUSH 


AX 


CALL 


R3 


SHR 


AL,CL 


AND 


AL,AH 


MOV 


CL,ES:[SI ] 


POP 


BX 


TEST 


BL,80H 


JNZ 


R2 


NOT 


AH 


AND 


CL,AH 


OR 


AL,CL 


R1: 




MOV 


ES:[SI ],AL 


POP 


AX 


JMP 


V_RET 


R2: 




XOR 


AL,OL 


JMP 


R1 


WRITE_DOT 


ENDP 


WRITE DOT 2 


PROC NEAR 


OMP 


CRT MODE,OFH 


JB 


NO ADJ2 


CALL 


MEM DET 


JC 


NO ADJ2 


AND 


AL, 10000101B 


MOV 


AH,AL 


SHL 


AH,1 


OR 


AL,AH 


NO ADJ2: 




PUSH 


AX 


MOV 


AX,DX 


CALL 


DOT SUP 1 


MOV 


DH,3 


MOV 


DL, GRAPH ADDR 


MOV 


AH,G BIT MASK 


CALL 


OUT DX 


PUSH 


DX 


SRLOAD 


ES,OAOOOH 


MOV 


DX, OAOOOH 


MOV 


ES,DX 


POP 


DX 


POP 


AX 


MOV 


OH,AL 


TEST 


0H,080H 


JZ 


WD A 


MOV 


AH,G DATA ROT 


MOV 


AL,018H 


CALL 


OUT DX 


JMP 


WD_B 


WD_A: 




MOV 


DL,SEQ ADDR 


MOV 


AH,S MAP 


MOV 


AL,OFFH 


CALL 


OUT DX 



SAVE DOT VALUE 

TWICE 
DETERMINE BYTE POSITION OF THE DOT 
SHIFT TO SET UP THE BITS FOR OUTPUT 
STRIP OFF THE OTHER BITS 
GET THE CURRENT BYTE 
RECOVER XOR FLAG 
IS IT ON 

YES, XOR THE DOT 
SET THE MASK TO REMOVE THE 

INDICATED BITS 
OR IN THE NEW VALUE OF THOSE BITS 
F I N I SH_DOT 
RESTORE THE BYTE IN MEMORY 



XOR_DOT 

EXCLUSIVE OR THE DOTS 

FINISH UP THE WRITING 



85H, XOR 02 CO MASK 



; GRAPHICS CHIP 

; BIT MASK REGISTER 

; SET BIT MASK 

; REGEN SEGMENT 



RECOVER COLOR 

SAVE COLOR 

SEE I F XOR 

NO XOR 

DO XOR 

XOR FUNCTION 

SET THE REGISTER 

SKIP THE BLANK 

BLANK THE DOT 

SEQUENCER 

MAP MASK 

ENABLE ALL MAPS 

SET THE REGISTER 



144 IBM Enhanced Graphics Adapter 



Ai^vst 2, 1984 



ICJtl 


26: 8A 07 


^c^^ 


2A CO 




1CU6 


26: 88 07 


1C49 






1CU9 


82 CU 




1CUB 


84 02 




1C«4D 


8A C5 




1CUF 


2H OF 




1C51 


E8 0D15 


R 


1C5U 


26: 8A 07 


1C57 


BO FF 




1C59 


26: 88 07 


1C5C 


E8 GDI 5 


R 


1C5F 


82 CE 




1C61 


84 03 




1C63 


2A CO 




1C65 


E8 0D15 


R 


1C68 


84 08 




1C6A 


80 FF 




1C6C 


E8 0D15 


R 


1C6F 


E9 219E 


R 


1C72 






1C72 






1C72 


50 




1C73 


52 




1C7U 


BA AOOO 




1C77 


8E C2 




1C79 


5A 




1C7A 


58 




1C7B 


8B C2 




1C7D 


E8 1B60 


R 


1C80 


B5 07 




1C82 


2A E9 




1C8U 


2B D2 




1C86 


80 00 




1C88 


C3 




1C89 






1C89 






1C89 


8A CD 




1C8B 


B4 04 




1C8D 


52 




1C8E 


86 03 




1C90 


82 CE 




1C92 


E8 0015 


R 


1C95 


5A 




1C96 


26: 8A 27 


1C99 


D2 EC 




1C9B 


80 E4 01 


1C9E 


C3 




1C9F 







1CA7 


BA 


B800 






1CAA 


8E 


C2 






1CAC 


5A 








1CAD 


E8 


1B88 


R 




1CB0 


26 


8A 04 




1CB3 


22 


C4 






1CB5 


D2 


EO 






1CB7 


8A 


CE 






1CB9 


D2 


CO 






1CBB 


E9 


219E 


R 




1CBE 










1CBE 










1CBE 


80 


3E 0449 


R OF 


1CC3 


72 


25 






1CC5 


E8 


14F7 


R 




1CC8 


72 


20 






1CCA 










1CCA 


E8 


1C72 


R 




1CCD 


E8 


1C89 


R 




1CD0 


OA 


D4 






1CD2 


DO 


E4 






1CD4 


OA 


D4 






1CD6 


80 


02 






1CD8 


E8 


1C89 


R 




1CDB 


DO 


E4 






1CDD 


DO 


E4 






1CDF 


OA 


D4 






1CE1 


DO 


E4 






1CE3 


OA 


D4 






1CE5 


8A 


C2 






1CE7 


E9 


219E 


R 




1CEA 










1CEA 










1CEA 


E8 


1C72 


R 




ICED 










ICED 


E8 


1C89 


R 




1CF0 


8A 


C8 






1CF2 


D2 


E4 






1CF4 


OA 


D4 






1CF6 


FE 


CO 






1CF8 


3C 


03 






1CFA 


76 


F1 






1CFC 


8A 


C2 






1CFE 


E9 


219E 


R 




1D01 











5167 
5168 
5169 
5170 
5171 
5172 
5173 
5174 
5175 
5176 
5177 
5178 
5179 
5180 
5181 
5182 
5183 
5184 
5185 
5186 
5187 
5188 
5189 
5190 
5191 
5192 
5193 
5194 
5195 
5196 
5197 
5198 
5199 
5200 
5201 
5202 
5203 
5204 
5205 
5206 
5207 
5208 
5209 
5210 
5211 
5212 
5213 
5214 
5215 
5216 
5217 
5218 
5219 
5220 
5221 
5222 
5223 
5224 
5225 
5226 
5227 
5228 
5229 
5230 
5231 
5232 
5233 
5234 
5235 
5236 
5237 
5238 
5239 
5240 
5241 
5242 
5243 
5244 
5245 
5246 
5247 
5248 
5249 
5250 
5251 
5252 
5253 
5254 
5255 
5256 
5257 
5258 
5259 
5260 
5261 
5262 
5263 
5264 
5265 
5266 
5267 
5268 
5269 
5270 
5271 
5272 
5273 
5274 
5275 
5276 
5277 
5278 
5279 
5280 
5281 
5282 
5283 
5284 
5285 
5286 
5287 
5288 
5289 
5290 
5291 
5292 





MOV 


AL,ES:(BX] 




SUB 


AL.AL 




MOV 


ES:[BX],AL 


WD_B: 








MOV 


DL,SEQ ADDR 




MOV 


AH,S MAP 




MOV 


AL,CH 




AND 


AL,OFH 




CALL 


OUT DX 




MOV 


AL,ES:[BX] 




MOV 


AL,OFFH 




MOV 


ES:[BX].AL 




- NORMALIZE THE ENVIRONMENT 




CALL 


OUT DX 




MOV 


DL, GRAPH ADDR 




MOV 


AH.G DATA ROT 




SUB 


AL.AL 




CALL 


OUT DX 




MOV 


AH,G BIT MASK 




MOV 


AL.OFFH 




CALL 


OUT_DX 




JMP 


V RET 


WRITE 


_D0T_2 


ENDP 


RD_S 


PROC 


NEAR 




ASSUME 


DS:ABSO 




PUSH 


AX 




PUSH 


DX 




SRLOAD 


ES,OAOOOH 




MOV 


DX,OAO0OH 




MOV 


ES,DX 




POP 


DX 




POP 


AX 




MOV 


AX,DX 




CALL 


DOT SUP 1 




MOV 


CH,7 




SUB 


CH,CL 




SUB 


DX, DX 




MOV 


AL,0 




RET 




RD_S 


ENDP 




RD_1S 


PROC 


NEAR 




MOV 


CL,CH 




MOV 


AH, 4 




PUSH 


DX 




MOV 


DH,3 




MOV 


DL, GRAPH ADDR 




CALL 


OUT DX 




POP 


DX 




MOV 


AH,ES:[BX] 




SHR 


AH,CL 




AND 


AH,1 




RET 




RD_1S 


ENDP 
- READ DOT 




AHD: 








ASSUME 


DS:ABS0 




CMP 


CRT MODE, 7 




JA 


R_i 


READ_ 


DOT 


PROC NEAR 




ASSUME 


DS:ABSO,ES: NOTHING 




PUSH 


DX 




SRLOAD 


ES,0B800H 




MOV 


DX,08800H 




MOV 


ES,DX 




POP 


DX 




CALL 


R3 




MOV 


AL, ES:[SI ] 




AND 


AL,AH 




SHL 


AL,CL 




MOV 


CL,DH 




ROL 


AL,CL 




JMP 


V RET 


READ_ 


DOT 


ENDP 


R_1: 


CMP 


CRT MODE,0FH 




JB 


READ DOT 2 




CALL 


MEM DET 




JC 


READ_D0T_2 


READ_ 


D0T_1 


PROC NEAR 




ASSUME 


DS:ABSO, ES: NOTHING 




CALL 


RD S 




CALL 


RD IS 




OR 


DL,AH 




SHL 


AH,1 




OR 


DL,AH 




MOV 


AL,2 




CALL 


RD IS 




SHL 


AH,1 




SHL 


AH,1 




OR 


DL,AH 




SHL 


AH,1 




OR 


DL,AH 




MOV 


AL.DL 




JMP 


V RET 


READ_ 


D0T_1 


ENDP 


READ_ 


DOT 2 


PROC NEAR 




ASSUME 


DS:ABSO, ES: NOTHING 




CALL 


RD_S 


RD_2A 








CALL 


RD IS 




MOV 


CL,AL 




SHL 


AH,CL 




OR 


DL,AH 




INC 


AL 




CMP 


AL,3 




JBE 


RD 2A 




MOV 


AL,DL 




JMP 


V RET 


READ_ 


DOT 2 


ENDP 



LATCH DATA 

ZERO 

BLANK THE DOT 

SET THE COLOR MAP MASK 

SEQUENCER 

MAP MASK REGISTER 

COLOR VALUE 

VALUES 0-15 

SET IT 

LATCH DATA 

WRITE VALUE 

SET THE DOT 



ALL MAPS ON 
GRAPHICS CHIPS 
XOR REGISTER 
NORMAL WRITES 



WRITE DOT DONE 



DETERMINE BYTE POSITION OF DOT 

GET THE BYTE 

MASK OFF THE OTHER BITS IN THE BYTE 

LEFT JUSTIFY THE VALUE 

GET NUMBER OF BITS IN RESULT 

RIGHT JUSTIFY THE RESULT 



WRITE_TTY WRITE TELETYPE TO ACTIVE PAGE 

THIS INTERFACE PROVIDES A TELETYPE LIKE INTERFACE TO THE VIDEO 
CARD. THE INPUT CHARACTER IS WRITTEN TO THE CURRENT CURSOR 
POSITION, AND THE CURSOR IS MOVED TO THE NEXT POSITION. IF THE 
CURSOR LEAVES THE LAST COLUMN OF THE FIELD. THE COLUMN IS SET 



August 2, 1984 



IBM Enhanced Graphics Adapter 145 



1D02 


8A 


3E 0462 R 


1D06 


53 




1D07 


8A 


OF 


1D09 


32 


FF 


1D0B 


D1 


E3 


1D0D 


8B 


97 0450 R 


1D11 


5B 




1D12 


3C 


OD 


1D1U 


7U 


5C 


1D16 


3C 


OA 


1D18 


7U 


5C 


1D1A 


3C 


08 


1D1C 


74 


4C 


1D1E 


3C 


07 


1D20 


7U 


5C 


1D22 


BH 


OA 


1D24 


B9 


0001 


1D27 


CD 


10 


1D29 


FE 


C2 


1D2B 


3A 


16 044A R 


1D2F 


75 


35 


1D31 


2A 


02 


1D33 


3A 


36 0484 R 


1D37 


75 


2B 


1D39 






1D39 


E8 


115D R 


1D3C 


AO 


0449 R 


1D3F 


3C 


04 


1DU1 


72 


06 


1DU3 


2A 


FF 


1045 


3C 


07 


1D47 


75 


06 


1DI49 






1D49 


BU 


08 


1DI4B 


CD 


10 


1D4D 


8A 


FC 


IDUF 






1DUF 


B8 


0601 


1D52 


2B 


C9 


1D54 


8A 


36 0484 R 


1D58 


8A 


16 044A R 


1D5C 


FE 


CA 


1D5E 






1D5E 


CD 


10 


1D60 






1D60 


58 




1D61 


E9 


219E R 


1D6U 






1D6U 


FE 


C6 


1D66 






1D66 


B4 


02 


1D68 


EB 


F4 


1D6A 






1D6A 


OA 


02 


1D6C 


in 


F8 


1D6E 


FE 


CA 


1D70 


EB 


F4 


1D72 






1D72 


2A 


02 


1D74 


EB 


FO 


1D76 






1D76 


3A 


36 0484 R 


1D7A 


75 


E8 


1D7C 


EB 


BB 


1D7E 






1D7E 


B3 


02 


1D80 


E8 


0020 R 


1D83 


EB 


DB 



1085 


8A 26 044A R 


1089 


8A 3E 0462 R 


1080 


AO 0487 R 


1090 


24 80 


1092 


OA 06 0449 R 



5293 
5294 
5295 
5296 
5297 
5298 
5299 
5300 
5301 
5302 
5303 
5304 
5305 
5306 
5307 
5308 
5309 
5310 
5311 
5312 
5313 
5314 
5315 
5316 
5317 
5318 
5319 
5320 
5321 
5322 
5323 
5324 
5325 
5326 
5327 
5328 
5329 
5330 
5331 
5332 
5333 
5334 
5335 
5336 
5337 
5338 
5339 
5340 
5341 
5342 
5343 
5344 
5345 
5346 
5347 
5348 
5349 
5350 
5351 
5352 
5353 
5354 
5355 
5356 
5357 
5358 
5359 
5360 
5361 
5362 
5363 
5364 
5365 
5366 
5367 
5368 
5369 
5370 
5371 
5372 
5373 
5374 
5375 
5376 
5377 
5378 
5379 
5380 
5381 
5382 
5383 
5384 
5385 
5386 
5387 
5388 
5389 
5390 
5391 
5392 
5393 
5394 
5395 
5396 
5397 
5398 
5399 
5400 
5401 
5402 
5403 
5404 
5405 
5406 
5407 
5408 
5409 
5410 
5411 
5412 
5413 
5414 
5415 
5416 
5417 
5418 



TO ZERO, AND THE ROW VALUE IS INCREMENTED. IF THE ROW VALUE 
LEAVES THE FIELD, THE CURSOR IS PLACED ON THE LAST ROW, FIRST 
COLUMN, AND THE ENTIRE SCREEN IS SCROLLED UP ONE LINE. WHEN 
THE SCREEN IS SCROLLED UP, THE ATTRIBUTE FOR FILLING THE NEWLY 
BLANKED LINE IS READ FROM THE CURSOR POSITION ON THE PREVIOUS 
LINE BEFORE THE SCROLL, IN CHARACTER MODE. IN GRAPHICS MODE, 
THE COLOR IS USED. 

(AH) = CURRENT CRT MODE 

(AL) = CHARACTER TO BE WRITTEN 
NOTE THAT BACK SPACE, CAR RET, BELL AND LINE FEED ARE HANDLED 
AS COMMANDS RATHER THAN AS DISPLAYABLE GRAPHICS 

(BL) = FOREGROUND COLOR FOR CHAR WRITE IF CURRENTLY IN A 
GRAPHICS MODE 

ALL REGISTERS SAVED 



SAVE REGISTERS 

GET THE ACTIVE PAGE 

SAVE 

GET PAGE TO BL 

CLEAR HIGH BYTE 

*2 FOR WORD OFFSET 

CURSOR, ACTIVE PAGE 

RECOVER 



IS IT CARRIAGE RETURN 

CAR_RET 

IS IT A LINE FEED 

LINE_FEED 

IS IT A BACKSPACE 

BAG K_S PACE 

IS IT A BELL 

BELL 



ASSUME CS:CODE.DS:ABS0 


PUSH 


AX 


MOV 


BH, ACTIVE PAGE 


PUSH 


BX 


MOV 


BL.BH 


XOR 


BH.BH 


SAL 


BX,1 


MOV 


OX, [BX + OFFSET CURSOR POSN 


POP 


BX 


; ox NOW HAS THE CURRENT CURSOR POSITI 


CMP 


AL,ODH 


JE 


U9 


CMP 


AL,OAH 


JE 


U10 


CMP 


AL,08H 


JE 


U8 


CMP 


AL,07H 


JE 


U11 


. WRITE 


THE CHAR TO THE SCREEN 


MOV 


AH, 10 


MOV 


CX, 1 


INT 


10H 


. POSIT 


ON THE CURSOR FOR NEXT CHAR 


INC 


DL 


CMP 


OL,BYTE PTR CRT COLS 


JNZ 


U7 


SUB 


OL,DL 


CMP 


OH, ROWS 


JNZ 


U6 



: WRITE CHAR ONLY 
ONLY ONE CHAR 
WRITE THE CHAR 



; TEST FOR COLUMN OVERFLOW 
; SET_CURSOR 
COLUMN FOR CURSOR 



• SCROLL REQUIRED 



CALL 


SET_CPOS 


)ETERM 


INE VALUE TO F 


MOV 


AL,CRT MODE 


CMP 


AL,4 


JB 


U2 


SUB 


BH, BH 


CMP 


AL.7 


JNE 


U3 



SET_CURSOR_INC 



SET THE CURSOR 



MOV 
SUB 
MOV 
MOV 
DEC 


AX, 601 H 

CX,CX 

OH, ROWS 

DL,BYTE PTR CRT COLS 

DL 


INT 


10H 


POP 
JMP 


AX 
V_RET 


INC 


OH 


MOV 
JMP 


AH, 2 
U4 


BACK 


SPACE FOUND 



CARRIAGE RETURN FOUND 

SUB DL,DL 
JMP U7 

• LINE FEED FOUND 



• CMP OH, 
JNE U6 
JMP U1 

• BELL FOUND 



MOV BL,2 
CALL BEEP 
JMP U5 



• CURRENT VIDEO STATE 



ASSUME 

MOV 

MOV 

MOV 

AND 

OR 



DS:ABSO 

AH, BYTE PTR CRT_COLS 

BH,ACTIVE_PAGE 

AL, INFO 

AL,080H 

AL,CRT_MODE 



; GET THE CURRENT MODE 



READ CHAR/ATTR 
STORE IN BH 
SCROLL-UP 
SCROLL ONE LINE 
UPPER LEFT CORNER 
LOWER RIGHT ROW 
LOWER RIGHT COLUMN 

VIDEO-CALL-RETURN 
SCROLL UP THE SCREEN 
TTY-RETURN 

RESTORE THE CHARACTER 
RETURN TO CALLER 
SET-CURSOR- INC 
NEXT ROW 
SET-CURSOR 

ESTABLISH THE NEW CURSOR 



ALREADY AT END OF LINE 

SET CURSOR 

NO -- JUST MOVE IT BACK 

SET_CURSOR 



BOTTOM OF SCREEN 

YES, SCROLL THE SCREEN 

NO, JUST SET THE CURSOR 



SET UP COUNT FOR BEEP 
SOUND THE POD BELL 
TTY_RETURN 



GET NUMBER OF COLUMNS 



146 IBM Enhanced Graphics Adapter 



August 2, 1984 



1D96 5F 

1D97 5E 

1D98 59 

1099 59 

1D9A 5A 

1D9B IF 

1D9C 07 

1D9D 5D 

1D9E CF 



1D9F 






1D9F 


50 




1DA0 


E8 


0D05 R 


1DA3 


FA 




1DA4 






1DA4 


EC 




1DA5 


A8 


08 


IDA? 


74 


FB 


1DA9 


58 




1DAA 


82 


CO 


1DAC 


86 


CU 


1DAE 


EE 




1DAF 


86 


CU 


1DB1 


EE 




1DB2 


BO 


20 



1DB7 




1DB7 


E8 1DC0 R 


1DBA 


B2 CO 


1DBC 


BO 20 


1DBE 


EE 


1DBF 


C3 


1DC0 




1DG0 




1DC0 


E8 0D05 R 


1DC3 


EC 


1DC4 


C3 


1DC5 





1DC5 


F6 06 0487 R 


02 


1DCA 


75 07 




1DCC 


80 3E 0463 R 


B4 


1DD1 


74 33 




1DD3 






1DD3 


8A EO 




1DD5 


OA E4 




1DD7 


75 30 




1DD9 


2B ED 




1DDB 


C4 3E 04A8 R 




1DDF 


83 C7 04 




1DE2 


26: C4 3D 




1DE5 


8C CO 




1DE7 


OB C7 




1DE9 


74 01 




1DEB 


45 




1DEC 






1DEC 


E8 1DC0 R 




1DEF 


8A E3 




1DF1 


8A C7 




1DF3 


E8 1D9F R 




1DF6 


E8 1DB7 R 




1DF9 


OB ED 




1DFB 


74 09 




IDFD 


8A C7 




1DFF 


2A FF 




1E01 


03 FB 




1E03 


26: 88 05 




1E06 






1E06 


E9 219E R 




1E09 






1E09 


FE CC 




1E0B 


75 2D 




1E0D 


2B ED 




1E0F 


C4 3E 04A8 R 




1E13 


83 C7 04 




1E16 


26: C4 3D 




1E19 


8C CO 




1E1B 


OB C7 




1E1D 


74 01 




1E1F 


45 




1E20 






1E20 


E8 1DC0 R 




1E23 


B4 11 




1E25 


8A C7 




1E27 


E8 1D9F R 




1E2A 


E8 1DB7 R 




1E2D 


OB ED 




1E2F 


74 D5 




1E31 


83 C7 11 




1E34 


26: 88 3D 




1E37 


E9 219E R 




1E3A 






1E3A 


FE CC 




1E3C 


75 40 




1E3E 


IE 




1E3F 


06 





5419 
5420 
5421 
5422 
5423 
5424 
5425 
5426 
5427 
5428 
5429 
5430 
5431 
5432 
5433 
5434 
5435 
5436 
5437 
5438 
5439 
5440 
5441 
5442 
5443 
5444 
5445 
5446 
5447 
5448 
5449 
5450 
5451 
5452 
5453 
5454 
5455 
5456 
5457 
5458 
5459 
5460 
5461 
5462 
5463 
5464 
5465 
5466 
5467 
5468 
5469 
5470 
5471 
5472 
5473 
5474 
5475 
5476 
5477 
5478 
5479 
5480 
5481 
5482 
5483 
5484 
5485 
5486 
5487 
5488 
5489 
5490 
5491 
5492 
5493 
5494 
5495 
5496 
5497 
5498 
5499 
5500 
5501 
5502 
5503 
5504 
5505 
5506 
5507 
5508 
5509 
5510 
5511 
5512 
5513 
5514 
5515 
5516 
5517 
5518 
5519 
5520 
5521 
5522 
5523 
5524 
5525 
5526 
5527 
5528 
5529 
5530 
5531 
5532 
5533 
5534 
5535 
5536 
5537 
5538 
5539 
5540 
5541 
5542 
5543 
5544 





POP 


Dl 




POP 


SI 




POP 


CX 




POP 


CX 




POP 


DX 




POP 


DS 




POP 


ES 




POP 


BP 




IRET 






SUBTTL 




PAL_SET 


PROC 


NEAR 




PUSH 


AX 




CALL 


WHAT_BASE 




CLI 




■ 


IN 


AL.DX 




TEST 


AL,08H 




JZ 


VR 




POP 


AX 




MOV 


DL,ATTR WRITE 




XCHG 


AL,AH 




OUT 


DX.AL 




XCHG 


AL,AH 




OUT 


DX.AL 




MOV 


AL,020H 




OUT 


DX.AL 




STI 






RET 




PAL_SET 


ENDP 




PAL_0N 


PROC 


NEAR 




CALL 


PAL IN IT 




MOV 


DL.ATTR WRITE 




MOV 


AL,020H 




OUT 


DX,AL 




RET 




PAL_0N 


ENDP 




PAL_INI 


T 


PROC NEAR 




CALL 


WHAT BASE 




IN 


AL, DX 




RET 




PAL_ 1 N 1 T 

. SET PALE 


ENDP 
:TTE REGISTERS 



; DISCARD BX 



; VERTICAL RETRACE 



ASSUME DS:ABS0 

TEST INFO, 2 

JNZ BM_0K 

■ HERE THE EGA IS IN A COLOR MODE 



IN MONOCHROME MODE 



MOV 


AH,AL 


OR 


AH, AH 


JNZ 


BM 1 


SET INDIVIDUAL REGISTER 


SUB 


BP,BP 


LES 


DI,SAVE PTR 


ADD 


Dl,4 ~ 


LES 


Dl, DWORD PTR ES:[DI ] 


MOV 


AX,ES 


OR 


AX,DI 


JZ 


TLO 1 


INC 


BP 


CALL 


PAL INIT 


MOV 


AH,BL 


MOV 


AL, BH 


CALL 


PAL SET 


CALL 


PAL ON 


OR 


BP,BP 


JZ 


BM OUT 


MOV 


AL,BH 


SUB 


BH,BH 


ADD 


DI,BX 


MOV 


ES:[DI ],AL 



DEC 


AH 


JNZ 


BM_2 


SUB 


BP,BP 


LES 


DI,SAVE PTR 


ADD 


Dl,4 


LES 


Dl, DWORD PTR ES:[DI 


MOV 


AX,ES 


OR 


AX,DI 


JZ 


TLO 2 



• SET OVERSCAN REGISTER 



CALL 


PAL INII 


MOV 


AH,011H 


MOV 


AL,BH 


CALL 


PAL SET 


CALL 


PAL_ON 


OR 


BP,BP 


JZ 


BM OUT 


ADD 


DI,011H 


MOV 


ES:[DI], 



JNZ BM_3 
■ SET 16 PALETTE REGISTERS AND OVERSCAN REGISTER 



Ai^vst 2, 1984 



IBM Enhanced Graphics Adapter 147 



lEUO 


CU 3E 04A8 R 


1E4«t 


83 C7 04 


1E47 


26: C4 3D 


1EUA 


8C CO 


1EUC 


OB C7 


1EUE 


74 09 


1E50 


IF 


1E51 


IE 


1E52 


8B F2 


1E5U 


B9 0011 


1E57 


F3/ A4 


1E59 




1E59 


07 


1E5A 


IF 


1E5B 


8B DA 


1E5D 


E8 IDCO R 


1E60 


2A E4 


1E62 




1E62 


26: 8A 07 


1E65 


E8 1D9F R 


1E68 


FE Ck 


1E6A 


43 


1E6B 


80 FC 10 


1E6E 


72 F2 


1E70 


FE C4 


1E72 


26: 8A 07 


1E75 


E8 1D9F R 


1E78 


E8 1DB7 R 


1E7B 


E9 219E R 


1E7E 




1E7E 


FE CC 


1E80 


75 29 



1E83 
1E86 
1E89 
1E8C 


E8 0D5A R 
83 C3 33 
26: 8A 07 
5B 


1E8D 
1E8F 


OA DB 
75 OA 


1E91 
1E96 
1E98 
1E9B 
1E9B 
1E9D 


80 26 0465 R DF 
24 F7 
EB OC 90 

FE CB 
75 07 


1E9F 
1EA4 
1EA6 


80 OE 0465 R 20 
OC 08 


1EA6 
1EA8 
1EAB 
1EAB 


B4 10 

E8 1D9F R 

E9 219E R 



1EAF 


55 






1EB0 


53 






1EB1 


51 






1EB2 


52 






1EB3 


06 






1EB4 


E8 


OCFE 


R 


1EB7 


AO 


0449 


R 


1EBA 


50 






1EBB 


3C 


07 




1EBD 


74 


07 




1EBF 


C6 


06 0449 R OB 


1EC4 


EB 


05 




1EC6 








1EC6 


C6 


06 0449 R OC 


1ECB 








1ECB 


E8 


ODAB 


R 


1ECE 


E8 


OCFE 


R 


1ED1 


58 






1ED2 


A2 


0449 


R 


1ED5 


07 






1ED6 


5A 






1ED7 


59 






1ED8 


5B 






1ED9 


5D 






1EDA 


58 






1EDB 


OA 


CO 




1EDD 


74 


17 




1EDF 


OE 






1EE0 


07 






1EE1 


2B 


D2 




1EE3 


B9 


0100 




1EE6 


FE 


C8 




1EE8 


75 


07 




1EEA 


B7 


OE 




1EEC 


BD 


0000 


E 


1EEF 


EB 


05 




1EF1 








1EF1 


B7 


08 




1EF3 


BD 


0000 


E 



5545 
5546 
5547 
5548 
5549 
5550 
5551 
5552 
5553 
5554 
5555 
5556 
5557 
5558 
5559 
5560 
5561 
5562 
5563 
5564 
5565 
5566 
5567 
5568 
5569 
5570 
5571 
5572 
5573 
5574 
5575 
5576 
5577 
5578 
5579 
5580 
5581 
5582 
5583 
5584 
5585 
5586 
5587 
5588 
5589 
5590 
5591 
5592 
5593 
5594 
5595 
5596 
5597 
5598 
5599 
5600 
5601 
5602 
5603 
5604 
5605 
5606 
5607 
5608 
5609 
5610 
5611 
5612 
5613 
5614 
5615 
5616 
5617 
5618 
5619 
5620 
5621 
5622 
5623 
5624 
5625 
5626 
5627 
5628 
5629 
5630 
5631 
5632 
5633 
5634 
5635 
5636 
5637 
5638 
5639 
5640 
5641 
5642 
5643 
5644 
5645 
5646 
5647 
5648 
5649 
5650 
5651 
5652 
5653 
5654 
5655 
5656 
5657 
5658 
5659 
5660 
5661 
5662 
5663 
5664 
5665 
5666 
5667 
5668 
5669 
5670 





LES 


DI,SAVE PTR 




ADD 


Dl,4 " 




LES 


Dl, DWORD PTR ES:[DI] 




MOV 


AX, ES 




OR 


AX,DI 




JZ 


TL0_3 




POP 


DS 




PUSH 


DS 




MOV 


SI.DX 




MOV 


CX, 17D 


REP 


MOVSB 




TL0_3: 








POP 


ES 




POP 


DS 




MOV 


BX,DX 




CALL 


PAL IN IT 




SUB 


AH, AH 


BM_2A: 








MOV 


AL,ES:[BX] 




CALL 


PAL SET 




INC 


AH 




INC 


BX 




CMP 


AH,010H 




JB 


BM 2A 




INC 


AH~ 




MOV 


AL,ES:[BX1 




CALL 


PAL_SET 




CALL 


PAL ON 




JMP 


V_RET 


BM_3: 








DEC 


AH 




JNZ 


BM_4 




TOGGLE 


INTENSIFY/BLINKING BIT 




PUSH 


BX 




CALL 


MAKE BASE 




ADD 


BX,010H + LN 4 




MOV 


AL.ES:[BX1 




POP 


BX 




OR 


BL,BL 




JNZ 


BM_6 




ENABLE 


INTENSIFY 




AND 


CRT MODE SET, 1101 1111 




AND 


AL,0F7H 




JMP 


BM_7 


BM_6: 








DEC 


BL 




JNZ 


BM_7 




ENABLE 


BLINK 




OR 


CRT MODE SET,020H 




OR 


AL,08H 



ES:DI PTR TO PAL SAVE AREA 



PARAMETER ES 
PARAMETER OFFSET 



INCLUDE 
SUBTTL 
PAGE 



AL = USER SPECIFIED FONT 

1 8 X 14 FONT 

2 8X8 DOUBLE DOT 
BL = BLOCK TO LOAD 



CH_GEN 








PUSH 


AX 




PUSH 


BP 




PUSH 


BX 




PUSH 


CX 




PUSH 


DX 




PUSH 


ES 




ASSUME 


DS:ABSO 




CALL 


DDS 




MOV 


AL,CRT MODE 




PUSH 


AX 




CMP 


AL,7 




JE 


H14 




MOV 


CRT MODE,0BH 




JMP 


SHORT H15 


H14: 








MOV 


CRT_MODE,0CH 


H15: 








CALL 


SET REGS 




CALL 


DDS 




POP 


AX 




MOV 


CRT_MODE,AL 




POP 


ES 




POP 


DX 




POP 


CX 




POP 


BX 




POP 


BP 




POP 


AX 




OR 


AL.AL 




JZ 


DO MAP2 




PUSH 


CS 




POP 


ES 




SUB 


DX,DX 




MOV 


CX,0256D 




DEC 


AL 




JNZ 


H7 




MOV 


BH.014D 




MOV 


BP, OFFSET CGMN 




JMP 


SHORT D0_MAP2 


H7: 








MOV 


BH,8 




MOV 


BP, OFFSET CGDDOT 



SAVE THE INVOLVED REGS 



SET DATA SEGMENT 

GET THE CURRENT MODE 

SAVE IT 

IS THIS MONOCHROME 

MONOCHROME VALUES 

COLOR VALUES 

SKIP 

MONOCHROME VALUES 



RESET THE DATA SEGMENT 
RECOVER OLD MODE VALUE 
RETURN TO LOW MEMORY 

RESTORE REGS THAT WERE 
USED BY THE MODE SET 
ROUTINES 



SET FLAGS 

USER SPECIFIED FONT 

SET SEGMENT TO 
THIS MODULE 

ZERO OUT START OFFSET 

CHAR COUNT (FULL SET) 
; WHICH PARAMETER 
: MUST BE ONE 

BYTES PER CHARACTER 

8 X 14 TABLE OFFSET 

STORE IT 



ALPHA CHARACTER GENERATOR LOAD 



148 IBM Enhanced Graphics Adapter 



August 2, 1984 



1EF6 








1EF6 


06 






1EF7 


IF 






1EF8 


52 






1EF9 


BA 


AOOO 




1EFC 


8E 


02 




lEFE 


5A 






1EFF 


51 






1F00 


B1 


05 




1F02 


D3 


E2 




1F04 


59 






1F05 


OA 


DB 




1F07 


74 


08 




1F09 








1F09 


81 


02 UOOO 


1F0D 


FE 


OB 




1F0F 


75 


F8 




1F11 








1F11 


8A 


07 




1F13 


2A 


E4 




1F15 


8B 


FA 




1F17 


8B 


F5 




1F19 


E3 


OD 




1F1B 








1F1B 


51 






1F1C 


8B 


08 




1F1E 


F3/ A4 




1F20 


2B 


F8 




1F22 


83 


07 20 


1F25 


59 






1F26 


E2 


F3 




1F28 








1F28 


C3 






1F29 








1F29 


E8 


OOFE 


R 


1F2C 


A3 


0U85 


R 


1F2F 


8B 


16 0U63 R 


1F33 


80 


3E 0UU9 R 07 


1F38 


75 


05 




1F3A 


BU 


14 




1F3C 


E8 


0D15 


R 


1F3F 








1F3F 


FE 


08 




IFUI 


B4 


09 




1FU3 


E8 


0D15 


R 


1F46 


FE 


08 




1F/|8 


8A 


E8 




1FUA 


8A 


08 




1FUC 


FE 


01 




1FUE 


B4 


01 




1F50 


CD 


10 




1F52 


8A 


IE 0449 R 


1F56 


B8 


015E 




1F59 


80 


FB 03 


1F5C 


77 


08 




1F5E 


E8 


0E9A 


R 


1F61 


72 


03 




1F63 


B8 


00C8 




1F66 








1F66 


99 






1F67 


F7 


36 0485 R 


1F6B 


U8 






1F6C 


A2 


0484 


R 


1F6F 


FE 


CO 




1F71 


2A 


E4 




1F73 


F7 


26 0485 R 


1F77 


U8 






1F78 


8B 


16 0463 R 


1F7C 


B4 


12 




1F7E 


E8 


0D15 


R 


1F81 


AO 


0484 


R 


1F8«t 


FE 


CO 




1F86 


F6 


26 044A R 


1F8A 


D1 


EO 




1F8C 


05 


0100 




1F8F 


A3 


0440 


R 


1F92 


E8 


0E96 


R 


1F95 


E9 


219E 


R 


1F98 








1F98 


3C 


10 




1F9A 


73 


37 




1F9C 


3C 


03 




1F9E 


73 


17 




1FA0 


E8 


1EAE 


R 


1FA3 


E8 


ODAB 


R 


1FA6 


E8 


0E96 


R 


1FA9 


E8 


OOFE 


R 


1FAC 


8B 


OE 0460 R 


1FB0 


BU 


01 




1FB2 


CD 


10 




1FBJ* 


E9 


219E 


R 


1FB7 








1FB7 


75 


17 




1FB9 


B6 


03 




1FBB 


B2 


04 




1FBD 


B8 


0001 




1FC0 


E8 


0D15 


R 


1FC3 


BU 


03 




1FC5 


8A 


03 




1FC7 


E8 


0D15 


R 



5671 
5672 
5673 
5674 
5675 
5676 
5677 
5678 
5679 
5680 
5681 
5682 
5683 
5684 
5685 
5686 
5687 
5688 
5689 
5690 
5691 
5692 
5693 
5694 
5695 
5696 
5697 
5698 
5699 
5700 
5701 
5702 
5703 
5704 
5705 
5706 
5707 
5708 
5709 
5710 
5711 
5712 
5713 
5714 
5715 
5716 
5717 
5718 
5719 
5720 
5721 
5722 
5723 
5724 
5725 
5726 
5727 
5728 
5729 
5730 
5731 
5732 
5733 
5734 
5735 
5736 
5737 
5738 
5739 
5740 
5741 
5742 
5743 
5744 
5745 
5746 
5747 
5748 
5749 
5750 
5751 
5752 
5753 
5754 
5755 
5756 
5757 
5758 
5759 
5760 
5761 
5762 
5763 
5764 
5765 
5766 
5767 
5768 
5769 
5770 
5771 
5772 
5773 
5774 
5775 
5776 
5777 
5778 
5779 
5780 
5781 
5782 
5783 
5784 
5785 
5786 
5787 
5788 
5789 
5790 
5791 
5792 
5793 
5794 
5795 
5796 



• POINTER TO TABLE 

• COUNT OF CHARS 

• CHAR COUNT OFFSET INTO MAP 2 
■ BYTES PER CHARACTER 

• MAP 2 BLOCK TO LOAD 



D0_MAP2 








PUSH 


ES 




POP 


DS 




PUSH 


DX 




SRLOAD 


ES,OAOOOH 




MOV 


DX,OAOOOH 




MOV 


ES,DX 




POP 


DX 




PUSH 


CX 




MOV 


CL,5 




SHL 


DX,CL 




POP 


CX 




OR 


BL,BL 




JZ 


H3 


H4: 








ADD 


DX,04000H 




DEC 


BL 




JNZ 


H4 


H3: 








MOV 


AL,BH 




SUB 


AH, AH 




MOV 


DI.DX 




MOV 


SI,BP 




JCXZ 


LD_0VER 


LD: 








PUSH 


OX 




MOV 


OX, AX 




REP 


MOVSB 




SUB 


DI.AX 




ADD 


DI,020H 




POP 


OX 




LOOP 


LD 


LD_0VER 








RET 




BRK_1 : 








ASSUME 


DS:ABSO 




CALL 


DOS 




MOV 


POINTS, AX 




MOV 


DX, ADDR_6845 




CMP 


CRT MODE, 7 




JNE 


H11A 




MOV 


AH,C UNDERLN LOG 




CALL 


OUT_DX 


H11A: 








DEO 


AL 




MOV 


AH,C MAX SCAN LN 




CALL 


OUT DX 




DEC 


AL 




MOV 


OH,AL 




MOV 


OL,AL 




INC 


OL 




MOV 


AH,1 




INT 


10H 




MOV 


BL,CRT_MODE 




MOV 


AX,350D 




CMP 


BL,3 




JA 


H11 




CALL 


BRST DET 




JO 


H11 




MOV 


AX,200D 


H11: 


CWD 






DIV 


POINTS 




DEC 


AX 




MOV 


ROWS,AL 




INC 


AL 




SUB 


AH, AH 




MUL 


POINTS 




DEO 


AX 




MOV 


DX,ADDR 6845 




MOV 


AH,C VRT DSP END 




CALL 


OUT DX 




MOV 


AL, ROWS 




INC 


AL 




MUL 


BYTE PTR CRT COLS 




SHL 


AX,1 




ADD 


AX,256D 




MOV 


CRT LEN,AX 




CALL 


PH_5 




JMP 
LOADABLE 


V_RET 

CHARACTER GENERATC 



AL,03H 
HI 



■ ALPHA MODE ACTIVITY HERE 



CMP 

JAE 

CALL 

CALL 

CALL 

ASSUME 

CALL 

MOV 

MOV 

INT 



CH_GEN 

SET_REGS 

PH_5 

DS:ABSO 

DOS 

OX,CURSOR_MODE 

AH,1 

10H 

V_RET 



JMP 
• SET THE CHARACTER GENERATOR BLOCK SELECT REGISTER 



FONT TABLE SEGMENT 
ADDRESSING TO TABLE 
SAVE REGISTER 
ADDRESSING TO MAP 2 



RECOVER REGISTER 

MULTIPLY BY 020H SINCE 
MAXIMUM BYTES PER 
CHARACTER IS 32D=020H 

RECOVER 

WHICH 16K BLOCK TO LOAD 

BLOCK ZERO 

INCREMENT TO NEXT BLOCK 
ANY MORE 
DO ANOTHER 

BYTES PER CHARACTER 

ZERO 

OFFSET INTO MAP 

OFFSET INTO TABLE 

CHARACTER COUNT 

SAVE CHARACTER COUNT 
ONE ENTIRE CHARACTER 

AT A TIME 
ADJUST OFFSET 
NEXT CHARACTER POSITION 
RECOVER CHARACTER COUNT 
DO THE REST 



SET LOW MEMORY SEGMENT 
GET BYTES/CHARACTER 
ORTO REGISTER 



POINTS - 1 

R09H 

SET THE CHARACTER HEIGHT 

POINTS - 2 

CURSOR START 

CURSOR END 

ADJUST END 

SET C_TYPE BIOS CALL 

SET THE CURSOR 

GET THE CURRENT MODE 
MAX SCANS ON SCREEN 
640X200 ALPHA MODES 
MUST BE 350 



; SET FOR 200 

PREPARE TO DIVIDE 

MAX ROWS ON SCREEN 

ADJUST 

SAVE ROWS 

READJUST 

CLEAR 

ROWS*BYTES/OHAR 

ADJUST 

ORTO ADDRESS 

SCANS DISPLAYED 

SET IT 

GET CHARACTER ROWS 

ADJUST 

ROWS»COLUMNS 

«2 FOR ALPHA MODE 

SPACE BETWEEN PAGES 

BYTES PER PAGE 

VIDEO ON 

RETURN TO CALLER 



RANGE CHECK 
NEXT STAGE 
SET THE CHAR GEN 

VIDEO ON 

SET THE DATA SEGMENT 

GET THE MODE 

SET C_TYPE 

EMULATE CORRECT CURSOR 

RETURN TO CALLER 



JNE 
MOV 
MOV 



MOV 
MOV 
CALL 



AH,S_CGEN 

AL,BL 

OUT_DX 



NOT IN RANGE 
SEQUENCER 
AH=S_RESET, AL=1 



CHAR BLOCK REGISTER 
GET THE VALUE 
SET IT 



August 2, 1984 



IBM Enhanced Graphics Adapter 149 



1FCA 


B8 


0003 




1FCD 


E8 


001 5 


R 


1FD0 








1FD0 


E9 


219E 


R 


1FD3 








1FD3 


3C 


20 




1FD5 


73 


26 




1FD7 


2C 


10 




1FD9 


3C 


02 




1FDB 


77 


F3 




1FDD 


50 






1FDE 


53 






1FDF 


E8 


1EAE 


R 


1FE2 


E8 


OOAB 


R 


1FE5 


58 






1FE6 


58 






1FE7 


8A 


EO 




1FE9 


OA 


E^ 




1FEB 


8A 


C7 




1FED 


74 


09 




1FEF 


80 


08 




1FF1 


80 


FC 01 




1FF4 


75 


02 




1FF6 


80 


OE 




1FF8 








1FF8 


2A 


E4 




1FFA 


E9 


1F29 


R 



1FFD 


3C 30 


1FFF 


73 6A 


2001 


2C 20 


2003 


75 11 



2005 


2B 


02 


2007 


8E 


DA 


2009 


FA 




200A 


89 


2E 007C R 


200E 


8C 


06 007E R 


2012 


FB 




2013 






2013 


E9 


219E R 


2016 






2016 


52 




2017 


2B 


D2 


2019 


8E 


DA 


201B 


5A 




201C 


3C 


03 


201 E 


77 


F3 


2020 


FE 


C8 


2022 


74 


14 


202U 


OE 




2025 


07 




2026 


FE 


C8 


2028 


75 


08 


202A 


B9 


OOOE 


202D 


BD 


0000 E 


2030 


EB 


06 


2032 






2032 


B9 


0008 


2035 


BD 


0000 E 


2038 






2038 


FA 




2039 


89 


2E 010C R 


203D 


8C 


06 OlOE R 


2041 


FB 




20U2 


E8 


OCFE R 


2045 


89 


OE 0485 R 


2049 


8A 


C3 


2048 


BB 


2067 R 


204E 


OA 


CO 


2050 


75 


05 


2052 


8A 


C2 


2054 


EB 


09 90 


2057 






2057 


3C 


03 


2059 


76 


02 


205B 


BO 


02 


205D 






205D 


2E 


D7 


205F 






205F 


FE 


C8 


2061 


A2 


0484 R 


2064 


E9 


219E R 


2067 






2067 


00 


OE 19 2B 



206B 


3C 


30 


206D 


74 


03 


206 F 






206F 


E9 


219E R 


2072 






2072 


8B 


OE 0485 R 


2076 


8A 


16 0484 R 


207A 


80 


FF 07 


207D 


77 


FO 


207F 


80 


FF 01 


2082 


77 


18 


2084 


52 




2085 


2B 


D2 


2087 


8E 


DA 


2089 


5A 





5797 
5798 
5799 
5800 
5801 
5802 
5803 
5804 
5805 
5806 
5807 
5808 
5809 
5810 
5811 
5812 
5813 
5814 
5815 
5816 
5817 
5818 
5819 
5820 
5821 
5822 
5823 
5824 
5825 
5626 
5827 
5828 
5829 
5830 
5831 
5832 
5833 
5834 
5835 
5836 
5837 
5838 
5839 
5840 
5841 
5842 
5843 
5844 
5845 
5846 
5847 
5848 
5849 
5850 
5851 
5852 
5853 
5854 
5855 
5856 
5857 
5858 
5859 
5860 
5861 
5862 
5863 
5864 
5865 
5866 
5867 
5868 
5869 
5870 
5871 
5872 
5873 
5874 
5875 
5876 
5877 
5878 
5879 
5880 
5881 
5882 
5883 
5884 
5885 
5886 
5887 
5888 
5889 
5890 
5891 
5892 
5893 
5894 
5895 
5896 
5897 
5898 
5899 
5900 
5901 
5902 
5903 
5904 
5905 
5906 
5907 
5908 
5909 
5910 
5911 
5912 
5913 
5914 
5915 
5916 
5917 
5918 
5919 
5920 
5921 
5922 



l_ALPHA1 : 

ASSUME DS:ABSO 

CMP AL,020H 

JAE AH11_GRAPHICS 

— ALPHA MODE ACTIVITY HERE 



JA 

PUSH 

PUSH 

CALL 

CALL 

POP 

POP 

MOV 

OR 

MOV 

JZ 

MOV 

CMP 

JNE 

MOV 



AH,1 
H13 
AL, 14D 



AH=S_RESET, AL=3 
RETURN TO CALLER 



ADJUST TO - N 
RANGE CHECK 
INVALID CALL 
SAVE 

LOAD THE CHAR GEN 



RESTORE 

CALLING PARAMETER 

USER MODE 

DO NOT SET BYTES/CHAR 
8X8 FONT 

IS THE CALL FOR MONOC 
NO, LEAVE IT AT 8 
MONOC SET 



■ GRAPHICS MODE ACTIVITY HERE 



l_GRAPHICS: 
ASSUME 
CMP 
JAE 
SUB 
JNZ 



DS:ABSO 
AL,030H 
AH11_ INFORM 
AL,020H 



COMPATIBILITY, UPPER HALF GRAPHICS CHARACTER SET 



ASSUME 
SRLOAD 
SUB 
MOV 



DS:ABSO 
DS,0 
DX,DX 
DS,DX 



ASSUME 


DS:ABSO 


PUSH 


DX 


SRLOAD 


DS,0 


SUB 


DX,DX 


MOV 


DS,DX 


POP 


DX 


CMP 


AL,03H 


JA 


F11 


DEC 


AL 


JZ 


F19 


PUSH 


CS 


POP 


ES 


DEC 


AL 


JNZ 


F13 


MOV 


CX,14D 


MOV 


BP, OFFSET CGMN 


JMP 


SHORT F19 


MOV 


CX,8 


MOV 


BP, OFFSET CGDDOT 


CLI 




MOV 


WORD PTR GRX SET 


MOV 


WORD PTR GRX_SET 


STI 




ASSUME 


DS:ABSO 


CALL 


DOS 


MOV 


POINTS,CX 


MOV 


AL,BL 


MOV 


BX, OFFSET RT 


OR 


AL,AL 


JNZ 


DR 3 


MOV 


AL,DL 


JMP 


DR_1 


CMP 


AL.3 


JBE 


DR 2 


MOV 


al72 


XLAT 


CS:RT 


DEC 


AL 


MOV 


ROWS,AL 


JMP 


V_RET 


LABEL 


BYTE 


DB 


OOD, 14D,25D,43D 



RANGE CHECK 



ROM 8 X 14 CHARACTER SET 



ROM 8X8 DOUBLE DOT 



- INFORMATION RETURN DONE HERE 

INFORM: 

ASSUME DS:ABSO 
CMP AL,030H 



MOV 
MOV 
CMP 



CX, POINTS 
DL, ROWS 
BH,7 



ASSUME 


DS:ABSO 


PUSH 


DX 


SRLOAD 


DS,0 


SUB 


DX,DX 


MOV 


DS,DX 


POP 


DX 



150 IBM Enhanced Graphics Adapter 



August 2, 1984 



208A 


OA 


FF 




5923 


208C 


75 


07 




5924 


208E 


CU 


2E 


007C R 


5925 


2092 


EB 


1A 


90 


5926 


2095 








5927 


2095 


Cl» 


2E 


0100 R 


5928 


2099 


EB 


13 


90 


5929 
5930 
5931 
5932 


209C 








5933 
5934 


209C 


80 


EF 


02 


5935 


209F 


8A 


DF 




5936 


20A1 


2A 


FF 




5937 


20A3 


D1 


E3 




5938 


20A5 


81 


03 


2087 R 


5939 


20A9 


2E 


8B 


2F 


5940 


20AC 


OE 






5941 


20AD 


07 






5942 
5943 


20AE 








5944 


20AE 


5F 






5945 


20AF 


5E 






5946 


20B0 


5B 






5947 


20B1 


58 






5948 


20B2 


58 






5949 


2083 


IF 






5950 


20BU 


58 






5951 


2085 


58 






5952 


2086 


CF 






5953 
5954 
5955 
5956 


2087 








5957 


2087 


0000 E 




5958 


2089 


0000 E 




5959 


20BB 


0000 E 




5960 


2080 


0000 E 




5961 










5962 










5963 










5964 










5965 










5966 


20BF 








5967 
5968 


208F 


80 


FB 


10 


5969 


20C2 


72 


51 




5970 


20CU 


7U 


IB 




5971 


20C6 


80 


FB 


20 


5972 


20C9 


7U 


03 




5973 


20CB 


E9 


219E R 


5974 


20CE 








5975 
5976 


20CE 


28 


D2 




5977 


20D0 


8E 


DA 




5978 


20D2 


FA 






5979 


20D3 


C7 


06 


0014 R 21A7 R 


5980 


2009 


8C 


OE 


0016 R 


5981 


20DD 


FB 






5982 


20DE 


E9 


219E R 


5983 


20E1 








5984 


20E1 


8A 


3E 


0487 R 


5985 


20E5 


80 


E7 


02 


5986 


20E8 


DO 


EF 




5987 
5988 


20EA 


AO 


0U87 R 


5989 


20ED 


24 


60 




5990 


20EF 


B1 


05 




5991 


20F1 


D2 


E8 




5992 


20F3 


8A 


D8 




5993 
5994 


20 F5 


8A 


OE 


0488 R 


5995 


20 F9 


8A 


E9 




5996 


20FB 


80 


El 


OF 


5997 


20FE 


DO 


ED 




5998 


2100 


DO 


ED 




5999 


2102 


DO 


ED 




6000 


210U 


DO 


ED 




6001 


2106 


80 


E5 


OF 


6002 
6003 


2109 


5F 






6004 


210A 


5E 






6005 


210B 


5A 






6006 


21 OC 


5A 






6007 


2100 


5A 






6008 


210E 


IF 






6009 


210F 


07 






6010 


2110 


5D 






6011 


2111 


CF 






6012 


2112 








6013 


2112 


E9 


219E R 


6014 


2115 








6015 


2115 








6016 


2115 


E9 


219E R 


6017 










6018 










6019 










6020 


2118 








6021 


2118 


3C 


Ok 




6022 


211A 


73 


F9 




6023 


211C 


E3 


F7 




6024 


211E 


53 






6025 


211F 


8A 


DF 




6026 


2121 


2A 


FF 




6027 


2123 


D1 


E3 




6028 


2125 


8B 


87 


0450 R 


6029 


2129 


58 






6030 


21 2A 


56 






6031 
6032 


212B 


50 






6033 


212C 


88 


0200 


6034 


212F 


CD 


10 




6035 


2131 


58 






6036 


2132 








6037 


2132 


51 






6038 


2133 


53 






6039 


213'J 


50 






6040 


2135 


86 


EO 




6041 


2137 


26: 


8A 


46 00 


6042 


213B 


1*5 






6043 


213C 


3C 


OD 




6044 


213E 


7k 


3D 




6045 


21U0 


3C 


OA 




6046 


2Ht2 


74 


39 




6047 


21U4 


3C 


08 




6048 





HANDLE 


BH = 2 THRU BH = 


5 HERE 


7: 


ASSUME 


DS:ABSO 






SUB 


BH,2 






MOV 


BL.BH 






SUB 


BH,BH 






SAL 


BX,1 






ADD 


BX. OFFSET TBL 5 






MOV 


BP,CS:[BX) 






PUSH 


OS 






POP 


ES 




NFORM. 


_OUT: 







RETURN ROM TABLE POINTERS 



TABLE OF CHARACTER GENERATOR OFFSETS 



TBL_5 


LABEL 


WORD 




DW 


OFFSET CGMN 




DW 


OFFSET CGDDOT 




DW 


OFFSET INT IF 1 




DW 


OFFSET CGMN FDG 




SUBTTL 






ALiERNATE SELECT 


AH12: 








ASSUME 


DS:ABSO 




CMP 


BL,010H 




JB 


ACT 1 




JE 


ACT 3 




CMP 


BL,020H 




JE 


ACT 2 




JMP 


V_RET 


ACT_2: 








SRLOAD 


DS,0 




SUB 


DX.DX 




MOV 


DS,DX 




CLI 






MOV 


WORD PTR INT5 PTf 




MOV 


WORD PTR INT5_PT 




STI 






JMP 


V_RET 


AC 1 _3 : 








MOV 


BH, INFO 




AND 


BH,2 




SHR 


BH,1 




MOV 


AL, INFO 




AND 


AL,01100000B 




MOV 


CL,5 




SHR 


AL,CL 




MOV 


BL.AL 




MOV 


CL, INFO 3 




MOV 


CH,CL 




AND 


CL,OFH 




SHR 


CH,1 




SHR 


CH,1 




SHR 


CH.1 




SHR 


CH,1 




AND 


CH,OFH 




POP 


Dl 




POP 


SI 




POP 


DX 




POP 


DX 




POP 


DX 




POP 


DS 




POP 


ES 




POP 


BP 




IRET 




AH12_X 








JMP 


V_RET 


ACT 1: 






STR_OUTZ: 






JMP 


V_RET 




WRITE STRING 


AH13: 








CMP 


AL,04 




JAE 


STR OUTZ 




JCXZ 


STR OUTZ 




PUSH 


BX 




MOV 


BL.BH 




SUB 


BH,BH 




SAL 


BX, 1 




MOV 


SI,[BX + OFFSET ( 




POP 


BX 




PUSH 


SI 




PUSH 


AX 




MOV 


AX, 0200H 




INT 


10H 




POP 


AX 


STR_1 : 








PUSH 


CX 




PUSH 


BX 




PUSH 


AX 




XCHG 


AH,AL 




MOV 


AL,ES:[BP] 




INC 


BP 




CMP 


AL,ODH 




JE 


STR_CR_LF 




CMP 


AL,OAH 




JE 


STR_CR_LF 



RETURN ACTIVE CALL 



ALTERNATE PRINT SCREEN 



NT5_PTR, OFFSET PRINT_SCREEN 



LOOKING FOR MONOC BIT 
ISOLATE 
ADJUST 

LOOKING FOR MEMORY 
MEMORY BITS 
SHIFT COUNT 
ADJUST MEM VALUE 
RETURN REGISTER 

FEATURE/SWITCH 
DUPLICATE IN CH 
MASK OFF SWITCH VALUE 
MOVE FEATURE VALUE 



RETURN TO CALLER 
RETURN TO CALLER 



*2 FOR WORD OFFSET 

GET CURSOR POSITION 

RESTORE 

CURRENT VALUE ON STACK 



SET THE CURSOR POSITION 



GET THE CHAR TO WRITE 
CARRIAGE RETURN 
LINE FEED 
BACKSPACE 



August 2, 1984 



IBM Enhanced Graphics Adapter 151 



21U6 


7U 35 


2148 


3C 07 


21UA 


7U 31 


2140 


89 0001 


21JtF 


80 PC 02 


2152 


72 05 


215U 


26: 8A 5E 00 


2158 


1*5 


2159 




2159 


Bk 09 


215B 


CD 10 


215D 


FE C2 


215F 


3A 16 OtjUA R 


2163 


72 11 


2165 


3A 36 0U84 R 


2169 


75 07 


216B 


B8 OEOA 


216E 


CD 10 


2170 


FE CE 


2172 




2172 


FE C6 


2174 


2A D2 


2176 




2176 


B8 0200 


2179 


CD 10 


217B 


EB OE 


217D 




217D 


BH OE 


217F 


CD 10 


2181 


8A OF 


2183 


2A FF 


2185 


D1 E3 


2187 


88 97 0*450 R 


2188 





21 8E E2 A2 



2191 


3C 


01 


2193 


/U 


09 


2195 


3C 


03 


2197 


/H 


05 


2199 


B» 


0200 


219C 


CI) 


10 


219E 






219E 






219E 


51- 




219F 


5E 




21A0 


5B 




21A1 


59 




21A2 


5A 




21A3 


IF 




21AU 


07 




21A5 


50 




21A6 


CF 




21A7 







21A7 

21A7 FB 

21A8 IE 

21A9 50 

21AA 53 

21AB 51 

21AC 52 

21AD E8 OCFE R 

2180 80 3E 0500 R 01 

2185 74 63 

2187 C6 06 0500 R 01 

218C BU OF 

218E CD 10 



21C0 


8A CC 


21C2 


8A 2E 0U84 R 


21C6 


FE C5 


21C8 


E8 2220 R 


21CB 


51 


21CC 


BU 03 


21CE 


CD 10 


21 DO 


59 


21D1 


52 


21D2 


33 02 



21DA CD 10 
21DC OA CO 



6049 
6050 
6051 
6052 
6053 
605U 
6055 
6056 
6057 
6058 
6059 
6060 
6061 
6062 
6063 
6064 
6065 
6066 
6067 
6068 
6069 
6070 
6071 
6072 
6073 
6074 
6075 
6076 
6077 
6078 
6079 
6080 
6081 
6082 
6083 
6084 
6085 
6086 
6087 
6088 
6089 
6090 
6091 
6092 
6093 
6094 
6095 
6096 
6097 
6098 
6099 
6100 
6101 
6102 
6103 
6104 
6105 
6106 
6107 
6108 
6109 
6110 
6111 
6112 
6113 
6114 
6115 
6116 
6117 
6118 
6119 
6120 
6121 
6122 
6123 
6124 
6125 
6126 
6127 
6128 
6129 
6130 
6131 
6132 
6133 
6134 
6135 
6136 
6137 
6138 
6139 
6140 
6141 
6142 
6143 
6144 
6145 
6146 
6147 
6148 
6149 
6150 
6151 
6152 
6153 
6154 
6155 
6156 
6157 
6158 
6159 
6160 
6161 
6162 
6163 
6164 
6165 
6166 
6167 
6168 
6169 
6170 
6171 
6172 
6173 
6174 



JE 


SIR CR LF 


CMP 


AL,07H 


JE 


STR CR LF 


MOV 


CX,1 


CMP 


AH, 2 


JB 


DO STR 


MOV 


8L,ES:[BP] 


INC 


BP 


DO STR: 





CMP 


DL,BYTE PTR CRT COLS 


JB 


STR 2 


CMP 


DH,R0WS 


JNE 


STR 3 


MOV 


AX,0E0AH 


INT 


10H 



MOV 


AX,0200H 


INT 


10H 


JMP 


SHORT STR 


STR CR LF: 




MOV 


AH,OEH 


INT 


10H 


MOV 


BL,BH 


SUB 


BH,BH 


SAL 


BX,1 


MOV 


DX, [BX + OF 


STR 4: 




POP 


AX 


POP 


BX 



BELL 

COUNT OF CHARACTERS 
CHECK WHERE ATTR IS 
NOT IN THE STRING 
GET THE ATTRIBUTE 
NEXT ITEM IN STRING 

WRITE THE CHAR/ATTR 

NEXT CURSOR POSITION 
COLUMN OVERFLOW 
NOT YET 



SET THE CURSOR 



GET PAGE TO LOW BYTE 



OFFSET CURSOR_POSN] 



DX 

AL, 1 

STR_OUT 

AL,3 

STR_OUT 

AX,0200H 

10H 



; SET CURSOR POSITION 
; ALLOW FALL THROUGH 
; VIDEO BIOS RETURN 





POP 


SI 








POP 


BX 








POP 


CX 








POP 


DX 








POP 


DS 








POP 


ES 








POP 


BP 








IRET 








V_RET 


ENDP 








COMBO_V 


IDEO 


ENDP 








INCLUDE 




VPRSC. 


INC 




SU8TTL 


VPRSC. 


INC 






PAGE 









INTERRUPT 5 

THIS LOGIC WILL BE INVOKED BY INTERRUPT 05H TO PRINT THE 
SCREEN. THE CURSOR POSITION AT THE TIME THIS ROUTINE IS INVOKED 
WILL BE SAVED AND RESTORED UPON COMPLETION. THE ROUTINE IS 
INTENDED TO RUN WITH INTERRUPTS ENABLED. IF A SUBSEQUENT 
'PRINT SCREEN' KEY IS DEPRESSED DURING THE TIME THIS ROUTINE 
IS PRINTING IT WILL BE IGNORED. 
ADDRESS 50:0 CONTAINS THE STATUS OF THE PRINT SCREEN: 

50:0 =0 EITHER PRINT SCREEN HAS NOT BEEN CALLED 

OR UPON RETURN FROM A CALL THIS INDICATES 
A SUCCESSFUL OPERATION. 
=1 PRINT SCREEN IS IN PROGRESS 
=255 ERROR ENCOUNTERED DURING PRINTING 



ASSUME CS:CODE,DS:ABSO 



NT SCREEN 


PROC FAR 


STI 




PUSH 


DS 


PUSH 


AX 


PUSH 


BX 


PUSH 


CX 


PUSH 


DX 


CALL 


DOS 


CMP 


STATUS 8YTE,1 


JZ 


EXIT 


MOV 


STATUS BYTE,1 


MOV 


AH, 15 



MUST RUN WITH I NTS ENABLED 
MUST USE 50:0 FOR DATA 
AREA STORAGE 



SEE IF PRINT ALREADY IN PROGRESS 
JUMP IF PRINT IN PROGRESS 
INDICATE PRINT NOW IN PROGRESS 
WILL REQUEST THE CURRENT MODE 
[AL]=MODE (NOT USED) 
[AH]=NUMBER COLUMNS/LINE 
[BH]=VISUAL PAGE 



AT THIS POINT WE KNOW THE COLUMNS/LINE ARE IN 

[AX] AND THE PAGE IF APPLICABLE IS IN [BH]. THE STACK 

HAS DS,AX, BX,CX,DX PUSHED. [AL] HAS VIDEO MODE 



WILL MAKE USE OF [CX] REG TO 

CONTROL ROW & COLUMNS 

ADJUST 

CAR RETURN LINE FEED ROUTINE 

SAVE SCREEN BOUNDS 

WILL NOW READ THE CURSOR. 

AND PRESERVE THE POSITION 

RECALL SCREEN BOUNDS 

RECALL [BH]=VISUAL PAGE 

SET CURSOR POSITION TO [0,0] 

THE LOOP FROM PR 1 10 TO THE INSTRUCTION PRIOR TO PR 1 20 : 
IS THE LOOP TO READ EACH CURSOR POSITION FROM THE : 
SCREEN AND PRINT. : 



MOV 


CL.AH 


MOV 


CH,ROWS 


INC 


CH 


CALL 


CRLF 


PUSH 


CX 


MOV 


AH, 3 


INT 


10H 


POP 


CX 


PUSH 


DX 


XOR 


DX.DX 



AH, 2 
10H 
AH, 8 
10H 
AL,AL 



TO INDICATE CURSOR SET REQUEST 
NEW CURSOR POS ESTABLISHED 
TO INDICATE READ CHARACTER 
CHARACTER NOW IN [AL] 
SEE I F VALID CHAR 



152 IBM Enhanced Graphics Adapter 



August 2, 1984 



21DE 


75 


02 




21 EO 


BO 


20 




21 E2 








21 E2 


52 






21E3 


33 


D2 




21 E5 


32 


Elt 




21 E7 


CD 


17 




21 E9 


5A 






21 EA 


F6 


Cl» 29 




21ED 


75 


21 




21EF 


FE 


C2 




21 n 


3A 


CA 




21F3 


75 


DF 




21 F5 


32 


02 




21 F7 


8A 


E2 




21 F9 


52 






21 FA 


E8 


2220 R 




21 FD 


5A 






21FE 


FE 


C6 




2200 


3A 


EE 




2202 


75 


DO 




220U 


5A 






2205 


B4 


02 




2207 


CD 


10 




2209 


C6 


06 0500 R 00 


220E 


EB 


OA 




2210 








2210 


5A 






2211 


BH 


02 




2213 


CD 


10 




2215 


C6 


06 0500 R FF 


221A 








221A 


5A 






221B 


59 






221C 


5B 






221D 


58 






221 E 


IF 






221 F 


CF 






2220 








2220 








2220 


33 


D2 




2222 


32 


EU 




222U 


BO 


OD 




2226 


CD 


17 




2228 


32 


EU 




222A 


BO 


OA 




222C 


CD 


17 




222E 


C3 







6175 
6176 
6177 
6178 
6179 
6180 
6181 
6182 
6183 
6184 
6185 
6186 
6187 
6188 
6189 
6190 
6191 
6192 
6193 
6194 
6195 
6196 
6197 
6198 
6199 
6200 
6201 
6202 
6203 
6204 
6205 
6206 
6207 
6208 
6209 
6210 
6211 



6214 
6215 
6216 
6217 
6218 
6219 
6220 
6221 
6222 
6223 
6224 
6225 
6226 
6227 
6228 
6229 
6230 
6231 
6232 
6233 



PUSH 
XOR 
XOR 
INT 
POP 
TEST 
JNZ 
INC 
CMP 
JNZ 
XOR 
MOV 
PUSH 
CALL 
POP 
INC 



MOV 

POP 
POP 
POP 
POP 
POP 
I RET 
_SCREEN 



CL,DL 
PRI10 
DL,DL 
AH,DL 



STATUS_BYTE,OFFH 



SAVE CURSOR POSITION 

INDICATE PRINTER 1 

TO INDICATE PRINT CHAR IN [AL] 

PRINT THE CHARACTER 

RECALL CURSOR POSITION 

TEST FOR PRINTER ERROR 

JUMP IF ERROR DETECTED 

ADVANCE TO NEXT COLUMN 

SEE IF AT END OF LINE 

I F NOT PROCEED 

BACK TO COLUMN 

[AH]=0 

SAVE NEW CURSOR POSITION 

LINE FEED CARRIAGE RETURN 

RECALL CURSOR POSITION 

ADVANCE TO NEXT LINE 

FINISHED? 

IF NOT CONTINUE 

RECALL CURSOR POSITION 

TO INDICATE CURSOR SET REQUEST 

CURSOR POSITION RESTORED 

INDICATE FINISHED 

EXIT THE ROUTINE 

GET CURSOR POSITION 
TO REQUEST CURSOR SET 
CURSOR POSITION RESTORED 
INDICATE ERROR 

RESTORE ALL THE REGISTERS USED 



• CARRIAGE RETURN, LINE FEED SUBROUTINE 



PROC 
XOR 
XOR 



NEAR 
DX,DX 
AH, AH 



PRINTER 
WILL NOW SEND I 
TO PRINTER 



SEND THE CARRIAGE RETURN 



0000 


00 
00 


00 
00 


00 


00 


00 00 


0008 


00 


00 


00 


00 


00 00 


000 E 


00 
81 


00 
BD 


7E 


81 


A5 81 


0016 


99 


81 


7E 


00 


00 00 


001C 


00 
FF 


00 
C3 


7E 


FF 


DB FF 


0024 


E7 


FF 


7E 


00 


00 00 


002A 


00 
FE 


00 
FE 


00 


6C 


FE FE 


0032 


7C 


38 


10 


00 


00 00 


0038 


00 
FE 


00 
7C 


00 


10 


38 7C 


0040 


38 


10 


00 


00 


00 00 


0046 


00 
E7 


00 
E7 


18 


3C 


3C E7 


004E 


18 


18 


3C 


00 


00 00 


0054 


00 
FF 


00 
7E 


18 


3C 


7E FF 


005C 


18 


18 


3C 


00 


00 00 


0062 


00 
3C 


00 
3C 


00 


00 


00 18 


006A 


18 


00 


00 


00 


00 00 


0070 


FF 
C3 


FF 
C3 


FF 


FF 


FF E7 


0078 


E7 


FF 


FF 


FF 


FF FF 


007 E 


00 
42 


00 
42 


00 


00 


3C 66 


0086 


66 


3C 


00 


00 


00 00 


008C 


FF 
BD 


FF 
BD 


FF 


FF 


C3 99 


0094 


99 


C3 


FF 


FF 


FF FF 


009A 


00 
78 


00 
CC 


IE 


OE 


lA 32 


00A2 


CC 


CC 


78 


00 


00 00 


00A8 


00 
3C 


00 
18 


3C 


66 


66 66 


OOBO 


7E 


18 


18 


00 


00 00 


00B6 


00 
30 


00 
30 


3F 


33 


3F 30 


OOBE 


70 


FO 


EO 


00 


00 00 


00C4 


00 
63 


00 
63 


7F 


63 


7F 63 


OOCC 


67 


E7 


E6 


CO 


00 00 


00D2 


00 
E7 


00 
3C 


18 


18 


DB 3C 


OODA 


DB 


18 


18 


00 


00 00 


00 EO 


00 
FE 


00 
F8 


80 


CO 


EO F8 


00E8 


EO 


CO 


80 


00 


00 00 


OOEE 


00 
FE 


00 
3E 


02 


06 


OE 3E 


00 F6 


OE 


06 


02 


00 


00 00 


00 FC 


00 
18 


00 
18 


18 


3C 


7E 18 


0104 


7E 


3C 


18 


00 


00 00 


01 OA 


00 


00 


66 


66 


66 66 



PAGE, 120 

SUBTTL MONOCHROME CHARACTER GENERATOR 
CODE SEGMENT PUBLIC 

PUBLIC CGMN 
CGMN LABEL BYTE 

DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH 

l,OBDH 
l,0C3H 
l,OFEH 
l,07CH 
l,0E7H 
l,07EH 
l,03CH 
H,0C3H 
1,042H 
l,OBDH 
l,OCCH 
H,018H 
H,030H 
H,063H 
H,03CH 



ODBH, 01 8H, 01 8H, OOOH, OOOH, OOOH 
OOOH, OOOH, 080H, OCOH, OEOH, 0F8H, OFEH, 



,0F8H 
,03EH 
,018H 
,066H 



BOTTOM_HALF 00 



BT_0F 
TH_10 



August 2, 1984 



IBM Enhanced Graphics Adapter 153 





66 


66 










66 


0112 


00 


66 


66 


00 


00 


00 


67 


0118 


00 
7B 


00 
IB 


7F 


DB 


DB 


DB 


68 
69 


0120 


IB 


IB 


IB 


00 


00 


00 


70 


0126 


00 
C6 


7C 
C6 


C6 


60 


38 


6C 


71 
72 


012E 


6C 


38 


OC 


C6 


70 


00 


73 


013U 


00 
00 


00 
00 


00 


00 


CO 


00 


74 
75 


013C 


FE 


FE 


FE 


00 


00 


00 


76 


01U2 


00 
18 


00 
18 


18 


3C 


7E 


18 


77 
78 


01UA 


7E 


3C 


18 


7E 


00 


00 


79 


0150 


00 
18 


00 
18 


18 


3C 


7E 


18 


80 
81 


0158 


18 


18 


18 


00 


00 


00 


82 


015E 


00 
18 


00 
18 


18 


18 


18 


18 


83 
84 


0166 


7E 


3C 


18 


00 


00 


00 


85 


016C 


00 
FE 


00 
OC 


00 


00 


18 


OC 


86 

87 


017U 


18 


00 


00 


00 


OC 


00 


88 


017A 


00 
FE 


00 
60 


00 


00 


30 


60 


89 
90 


0182 


30 


00 


00 


00 


00 


00 


91 


0188 


00 
CO 


00 
CO 


00 


00 


00 


CO 


92 
93 


0190 


FE 


00 


00 


00 


00 


00 


94 


0196 


00 
FE 


00 
6C 


00 


00 


28 


6C 


95 
96 


019E 


28 


00 


00 


00 


00 


00 


97 


01AU 


00 
7C 


00 
7C 


00 


10 


38 


38 


98 
99 


01AC 


FE 


FE 


00 


00 


00 


00 


100 


01 B2 


00 
7C 


00 
38 


00 


FE 


FE 


7C 


101 
102 


01 BA 


38 


10 


00 


00 


00 


00 


103 
104 


01C0 


00 
00 


00 
00 


00 


00 


00 


00 


105 
106 


01C8 


00 


00 


00 


00 


00 


00 


107 


01CE 


00 
18 


00 
18 


18 


3C 


30 


3C 


108 
109 


01 D6 


00 


18 


18 


00 


00 


00 


110 


01 DC 


00 
00 


66 
00 


66 


66 


24 


00 


111 
112 


01 EU 


00 


00 


00 


00 


00 


00 


113 


01 EA 


00 
6C 


00 
6C 


6C 


6C 


FE 


6C 


114 
115 


01 F2 


FE 


6C 


6C 


00 


00 


00 


116 


01 F8 


18 
7C 


18 

06 


7C 


C6 


02 


CO 


117 
118 


0200 


86 


C6 


7C 


18 


18 


00 


119 


0206 


00 
OC 


00 
18 


00 


00 


02 


06 


120 
121 


020E 


30 


66 


C6 


00 


00 


00 


122 


021U 


00 
76 


00 
DC 


38 


6C 


60 


38 


123 
124 


021C 


CC 


CC 


76 


00 


00 


00 


125 


0222 


00 
00 


30 
00 


30 


30 


60 


00 


126 
127 


022A 


00 


00 


00 


00 


00 


00 


128 


0230 


00 
30 


00 
30 


OC 


18 


30 


30 


129 
130 


0238 


30 


18 


OC 


00 


00 


00 


131 


023E 


00 
OC 


00 
OC 


30 


18 


OC 


OC 


132 
133 


02U6 


OC 


18 


30 


00 


00 


00 


134 


02UC 


00 
FF 


00 
3C 


00 


00 


66 


3C 


135 
136 


0254 


66 


00 


00 


00 


DO 


00 


137 


025A 


00 
7E 


00 
18 


00 


00 


18 


18 


138 
139 


0262 


18 


00 


00 


00 


00 


00 


140 


0268 


00 
00 


00 
00 


00 


00 


00 


00 


141 
142 


0270 


18 


18 


18 


30 


00 


00 


143 


0276 


00 
FE 


00 
00 


00 


00 


00 


00 


144 
145 


027E 


00 


00 


00 


00 


00 


00 


146 


0284 


00 
00 


00 
00 


00 


00 


00 


00 


147 
148 


028C 


00 


18 


18 


00 


00 


00 


149 


0292 


00 
30 


00 
60 


02 


06 


00 


18 


150 
151 


029A 


CO 


80 


00 


00 


00 


00 


152 
153 


02A0 


00 
F6 


00 
E6 


7C 


C6 


CE 


DE 


154 
155 


02A8 


C6 


C6 


7C 


00 


00 


00 


156 


02AE 


00 
18 


00 
18 


18 


38 


78 


18 


157 
158 


0286 


18 


18 


7E 


00 


00 


00 


159 


02BC 


00 
18 


00 
30 


7C 


C6 


06 


00 


160 
161 


02CU 


60 


C6 


FE 


00 


00 


00 


162 


02CA 


00 
30 


00 
06 


7C 


C6 


06 


06 


163 
164 


02D2 


06 


C6 


7C 


00 


00 


00 


165 


02D8 


00 
CC 


00 
FE 


OC 


1C 


30 


60 


166 
167 


02E0 


OC 


OC 


IE 


00 


00 


00 


168 


02E6 


00 
FC 


00 
06 


FE 


CO 


CO 


CO 


169 
170 


02EE 


06 


C6 


7C 


00 


00 


00 


171 


02 FU 


00 
FC 


00 
C6 


38 


60 


CO 


CO 


172 
173 


02 FC 


C6 


C6 


7C 


00 


00 


00 


174 


0302 


00 
18 


00 
30 


FE 


C6 


06 


00 


175 
176 


030A 


30 


30 


30 


00 


00 


00 


177 


0310 


00 
7C 


00 
C6 


7C 


C6 


C6 


06 


178 
179 


0318 


C6 


C6 


7C 


00 


00 


00 


180 


031E 


00 
7E 


00 
06 


7C 


C6 


06 


C6 


181 
182 


0326 


06 


OC 


78 


00 


00 


00 


183 


032C 


00 
00 


00 
00 


00 


18 


18 


00 


184 
185 


033U 


18 


18 


00 


00 


00 


00 


186 


033A 


00 
00 


00 
00 


00 


18 


18 


00 


187 
188 


0342 


18 


18 


30 


00 


DO 


00 


189 


0348 


00 
60 


00 
30 


06 


OC 


18 


30 


190 
191 



038H,010H, 
OOOH.OOOH, 



OOOH, 
OOOH, 



0OOH,OO0H, 
000H,000H, 



OOOH 
OOOH,OOOH,OOOH 



), OOOH, 
),070H, 



OOOH, OOOH, 
006H,OOEH, 



OOOH 
ODEH,0F6H,OE6H 



TH_1A 
BT_1A 



BT_1F 
TH_20 ! 



BT_2F / 
TH_30 



154 IBM Enhanced Graphics Adapter 



August 2, 1984 



0350 


18 


OC 


06 


00 


00 


00 


192 


0356 


00 
00 


00 
00 


00 


00 


00 


7E 


193 
194 


035E 


7E 


00 


00 


00 


00 


00 


195 


0364 


00 
06 


00 
OC 


60 


30 


18 


00 


196 
197 


036C 


18 


30 


60 


00 


00 


00 


198 


0372 


00 
18 


00 
18 


7C 


06 


C6 


00 


199 
200 


037A 


00 


18 


18 


00 


00 


00 


201 
202 


0380 


00 
DE 


00 
DE 


7C 


06 


06 


DE 


203 
204 


0388 


DC 


CO 


7C 


00 


00 


00 


205 


038E 


00 
06 


00 
FE 


10 


38 


60 


06 


206 
207 


0396 


C6 


C6 


C6 


00 


00 


00 


208 


039C 


00 
7C 


00 
66 


FC 


66 


66 


66 


209 
210 


03Alt 


66 


66 


FC 


00 


00 


00 


211 


03AA 


00 
CO 


00 
CO 


3C 


66 


C2 


CO 


212 

213 


03B2 


C2 


66 


3C 


00 


00 


00 


214 


03B8 


00 
66 


00 
66 


F8 


60 


66 


66 


215 
216 


03C0 


66 


6C 


F8 


00 


00 


00 


217 


03C6 


00 
78 


00 
68 


FE 


66 


62 


68 


218 
219 


03CE 


62 


66 


FE 


00 


00 


00 


220 


03 DU 


00 
78 


00 
68 


FE 


66 


62 


68 


221 
222 


03DC 


60 


60 


FO 


00 


00 


00 


223 


03E2 


00 
CO 


00 
DE 


3C 


66 


C2 


00 


224 
225 


03 EA 


C6 


66 


3A 


00 


00 


00 


226 


03 FO 


00 
FE 


00 
C6 


C6 


06 


06 


06 


227 
228 


03 F8 


C6 


C6 


C6 


00 


00 


00 


229 


03FE 


00 
18 


00 
18 


3C 


18 


18 


18 


230 
231 


0U06 


18 


18 


3C 


00 


00 


00 


232 


OUOC 


00 
OC 


00 
OC 


IE 


00 


00 


00 


233 
234 


0414 


CC 


CC 


78 


00 


00 


00 


235 


QUIA 


00 
78 


00 
6C 


E6 


66 


60 


60 


236 
237 


0422 


6C 


66 


E6 


00 


00 


00 


238 


0U28 


00 
60 


00 
60 


FO 


60 


60 


60 


239 
240 


0430 


62 


66 


FE 


00 


00 


00 


241 


0436 


00 
06 


00 
C6 


C6 


EE 


FE 


FE 


242 
243 


043E 


C6 


06 


C6 


00 


00 


00 


244 


0444 


00 
DE 


00 
CE 


C6 


E6 


F6 


FE 


245 
246 


044C 


C6 


C6 


C6 


00 


00 


00 


247 


0452 


00 
C6 


00 
C6 


38 


60 


06 


06 


248 
249 


045A 


C6 


6C 


38 


00 


00 


00 


250 
251 


0460 


00 
7C 


00 
60 


FC 


66 


66 


66 


252 
253 


0468 


60 


60 


FO 


00 


00 


00 


254 


046E 


00 
C6 


00 
D6 


7C 


06 


06 


06 


255 
256 


0476 


DE 


7C 


OC 


OE 


00 


00 


257 


047C 


00 
7C 


CO 
6C 


FC 


66 


66 


66 


258 
259 


0484 


66 


66 


E6 


00 


00 


00 


260 


048A 


00 
38 


CO 
OC 


7C 


06 


06 


60 


261 
262 


0492 


C6 


C6 


7C 


00 


00 


00 


263 


0498 


00 
18 


00 
18 


7E 


7E 


5A 


18 


264 
265 


04A0 


18 


18 


3C 


00 


00 


00 


266 


04A6 


00 
C6 


00 
06 


C6 


06 


06 


06 


267 
268 


04AE 


C6 


06 


7C 


00 


00 


00 


269 


0484 


00 
C6 


00 
06 


C6 


06 


C6 


06 


270 
271 


04BC 


6C 


38 


10 


00 


00 


00 


272 


04C2 


00 
06 


00 
D6 


C6 


06 


06 


06 


273 
274 


04CA 


FE 


7C 


6C 


00 


00 


00 


275 


04D0 


00 
38 


00 
38 


06 


06 


60 


38 


276 
277 


04D8 


6C 


06 


C6 


00 


00 


00 


278 


04DE 


00 
3C 


00 
18 


66 


66 


66 


66 


279 
280 


04E6 


18 


18 


3C 


00 


00 


00 


281 


04 EC 


00 
30 


00 
60 


FE 


C6 


80 


18 


282 
283 


04F4 


C2 


06 


FE 


00 


00 


00 


284 


04 FA 


00 
30 


00 
30 


30 


30 


30 


30 


285 
286 


0502 


30 


30 


30 


00 


00 


00 


287 


0508 


00 
38 


00 

1C 


80 


CO 


EO 


70 


288 
289 


0510 


OE 


06 


02 


00 


00 


00 


290 


0516 


00 
OC 


00 
OC 


30 


00 


00 


00 


291 
292 


051E 


OC 


OC 


30 


00 


00 


00 


293 


0524 


10 
00 


38 
00 


60 


06 


00 


00 


294 
295 


052C 


00 


00 


00 


00 


00 


00 


296 


0532 


00 
00 


00 
00 


00 


00 


00 


00 


297 
298 


053A 


00 


00 


00 


00 


FF 


00 


299 
300 


0540 


30 
00 


30 
00 


18 


00 


00 


00 


301 
302 


0548 


00 


00 


00 


00 


00 


00 


303 


054E 


00 
OC 


00 
7C 


00 


00 


00 


78 


304 
305 


0556 


CC 


CC 


76 


00 


00 


00 


306 


055C 


00 
6C 


00 
66 


EO 


60 


60 


78 


307 
308 


0564 


66 


66 


70 


00 


00 


00 


309 


056A 


00 
C6 


00 
CO 


00 


00 


00 


7C 


310 
311 


0572 


CO 


C6 


70 


00 


00 


00 


312 


0578 


00 
6C 


00 
CC 


10 


00 


00 


30 


313 
314 


0580 


CC 


CC 


76 


00 


00 


00 


315 


0586 


00 
C6 


00 
FE 


00 


00 


00 


70 


316 
317 



OOOH, 
OOOH, 



018H, 
OOOH, 



018H, 
070H, 



OOOH, 
006 H, 



OOOH, 
0C6H, 



OOOH 
ODEH,ODEH,ODEH 



006H^ 
OOOH. 



,06CH, 
,000H, 



038H, 
OFOH, 



OOOH, 
066H, 



OOOH, 
066H, 



OOOH 
066H,07CH,060H 



OOOH, 
030H, 



OOOH, 
030H, 



,>000H, 
OOOH, 



,00OH 

, OOOH, OOOH, OOOH 



BT_3F ? 
TH_40 @ 



BT_4F 
TH_50 P 



BT_5F . 
TH_60 ' 



August!, 1984 



IBM Enhanced Graphics Adapter 155 



058E 


CO 


C6 


7C 


00 


00 


00 


318 


059U 


00 
FO 


00 
60 


38 


6C 


64 


60 


319 
320 


059C 


60 


60 


FO 


00 


00 


00 


321 


05A2 


00 
CC 


00 
CC 


00 


00 


00 


76 


322 
323 


05AA 


CC 


7C 


OC 


CC 


78 


00 


324 


05B0 


00 
76 


00 
66 


EO 


60 


60 


6C 


325 
326 


05B8 


66 


66 


E6 


00 


00 


00 


327 


05BE 


00 
18 


00 
18 


18 


18 


00 


38 


328 
329 


05C6 


18 


18 


3C 


00 


00 


00 


330 


05CC 


00 
06 


00 
06 


06 


06 


00 


OE 


331 
332 


05Dit 


06 


06 


66 


66 


30 


00 


333 


05DA 


00 
6C 


00 
78 


EO 


60 


60 


66 


334 
335 


05 E2 


6C 


66 


E6 


00 


00 


00 


336 


05E8 


00 
18 


00 
18 


38 


18 


18 


18 


337 
338 


05 FO 


18 


18 


3C 


00 


00 


00 


339 


05 F6 


00 
FE 


00 
D6 


00 


00 


00 


EC 


340 
341 


05FE 


D6 


D6 


C6 


00 


00 


00 


342 


0604 


00 
66 


00 
66 


00 


00 


00 


DC 


343 
344 


060C 


66 


66 


66 


00 


00 


00 


345 


0612 


00 
C6 


00 
06 


00 


00 


00 


7C 


346 
347 


061A 


C6 


C6 


7C 


00 


00 


00 


348 
349 


0620 


00 
66 


00 
66 


00 


00 


00 


DC 


350 
351 


0628 


66 


7C 


60 


60 


FO 


00 


352 


062E 


00 
CC 


00 
CC 


00 


00 


00 


76 


353 
354 


0636 


CC 


7C 


OC 


OC 


IE 


00 


355 


063C 


00 
76 


00 
66 


00 


00 


00 


DC 


356 
357 


0644 


60 


60 


FO 


00 


00 


00 


358 


06UA 


00 
C6 


00 
70 


00 


00 


00 


7C 


359 
360 


0652 


10 


06 


70 


00 


00 


00 


361 


0658 


00 
30 


00 
30 


10 


30 


30 


FC 


362 
363 


0660 


30 


36 


1C 


00 


00 


00 


364 


0666 


00 
CC 


00 
CC 


00 


00 


00 


CC 


365 
366 


066E 


CC 


CC 


76 


00 


00 


00 


367 


0674 


00 
66 


00 
66 


00 


00 


00 


66 


368 
369 


067C 


66 


3C 


18 


00 


00 


00 


370 


0682 


00 
C6 


00 
D6 


00 


00 


00 


C6 


371 
372 


068A 


D6 


FE 


6C 


00 


00 


00 


373 


0690 


00 
6C 


00 
38 


00 


00 


00 


C6 


374 
375 


0698 


38 


6C 


C6 


00 


00 


00 


376 


069E 


00 
C6 


00 
C6 


00 


00 


00 


C6 


377 
378 


06A6 


C6 


7E 


06 


OC 


F8 


00 


379 


06AC 


00 
CC 


00 
18 


00 


00 


00 


FE 


380 
381 


06B4 


30 


66 


FE 


00 


00 


00 


382 


06 BA 


00 
70 


00 
18 


OE 


18 


18 


18 


383 
384 


06C2 


18 


18 


OE 


00 


00 


00 


385 


06C8 


00 
00 


00 
18 


18 


18 


18 


18 


386 
387 


06D0 


18 


18 


18 


00 


00 


00 


388 


06 D6 


00 
OE 


00 
18 


70 


18 


18 


18 


389 
390 


06DE 


18 


18 


70 


00 


00 


00 


391 


06E4 


00 
00 


00 
00 


76 


DC 


00 


00 


392 
393 


06EC 


00 


00 


00 


00 


00 


00 


394 


06 F2 


00 
6C 


00 
C6 


00 


00 


10 


38 


395 
396 


06 FA 


C6 


FE 


00 


00 


00 


00 


397 
398 


0700 


00 
CO 


00 
C2 


3C 


66 


C2 


CO 


399 
400 


0708 


66 


3C 


OC 


06 


7C 


00 


401 


070E 


00 
CC 


00 
CC 


CC 


CC 


00 


CC 


402 
403 


0716 


CC 


CC 


76 


00 


00 


00 


404 


071C 


00 
C6 


OC 
FE 


18 


30 


00 


7C 


405 
406 


0724 


CO 


C6 


7C 


00 


00 


00 


407 


072A 


00 
OC 


10 
7C 


38 


6C 


00 


78 


408 
409 


0732 


CC 


CC 


76 


00 


00 


00 


410 


0738 


00 
OC 


00 
7C 


CC 


CC 


00 


78 


411 
412 


0740 


CC 


CC 


76 


00 


00 


00 


413 


0746 


00 
OC 


60 
7C 


30 


18 


00 


78 


414 
415 


074E 


CC 


CC 


76 


00 


00 


00 


416 


0754 


00 
OC 


38 
7C 


6C 


38 


00 


78 


417 
418 


075C 


CC 


CC 


76 


00 


00 


00 


419 


0762 


00 
60 


00 
66 


00 


00 


3C 


66 


420 
421 


076A 


3C 


OC 


06 


3C 


00 


00 


422 


0770 


00 
C6 


10 
FE 


38 


6C 


00 


7C 


423 
424 


0778 


CO 


C6 


7C 


00 


00 


00 


425 


077E 


00 
C6 


00 
FE 


CC 


CC 


00 


7C 


426 
427 


0786 


CO 


C6 


7C 


00 


00 


00 


428 


078C 


00 
C6 


60 
FE 


30 


18 


00 


7C 


429 
430 


0794 


CO 


C6 


7C 


00 


00 


00 


431 


079A 


00 
18 


00 
18 


66 


66 


00 


38 


432 
433 


07A2 


18 


18 


3C 


00 


00 


00 


434 


07A8 


00 
18 


18 
18 


3C 


66 


00 


38 


435 
436 


07B0 


18 


18 


3C 


00 


00 


00 


437 


07B6 


00 
18 


60 
18 


30 


18 


00 


38 


438 
439 


07BE 


18 


18 


3C 


00 


00 


00 


440 


07C4 


00 
C6 


C6 
C6 


C6 


10 


38 


6C 


441 
442 


07CC 


FE 


C6 


C6 


00 


00 


00 


443 



l,0C6H,07CH, 
),OOOH,OOOH, 



OOOH, 
OOOH, 



OOOH.OOOH 
OOOH,ODCH, 



0C6H, 
OOOH, 



OFEH.OOOH, 
000H,03CH, 



OOOH, 
066H, 



OOOH, OOOH 
0C2H,0C0H, 



l,0F0H,060H 

I 
l,OCCH,OCCH 

I 
l,076H,066H 

I 
l,018H,018H 

I 
l,006H,006H 

I 
l,06CH,078H 

I 
l,018H,018H 

I 
l,0FEH,0D6H 

I 
l,066H,066H 

I 
l,0C6H,0C6H 

066H,066H 
0CCH,0CCH 
076H,066H 
0C6H,070H 
030H,030H 
OCCH,OCCH 
066H,066H 
0C6H,0D6H 
06CH,038H 
0C6H,0C6H 
0CCH,018H 
070H,018H 
0O0H,O18H 
00EH,018H 
OOOH, OOOH 
06CH,0C6H 

0C0H,0C2H 
0CCH,0CCH 
0C6H,0FEH 
00CH,07CH 
00CH,07CH 
00CH,07CH 
00CH,07CH 
060H,066H 
0C6H,0FEH 
0C6H,0FEH 
0C6H,0FEH 
018H,018H 
018H,018H 
018H,018H 
0C6H,0C6H 



OFEH, 0C6H, 0C6H, OOOH, OOOH, OOOH 



BT_6F L.C. 
TH_70 L.C. 



BT_7F DELTA 
TH_80 



156 IBM Enhanced Graphics Adapter 



August 2, 1984 



07D2 


38 
C6 


6C 
C6 


38 


00 


38 


6C 


444 
445 


07DA 


FE 


C6 


C6 


00 


00 


00 


446 
447 


07E0 


18 
60 


30 
7C 


60 


00 


FE 


66 


448 
449 


07 E8 


60 


66 


FE 


00 


00 


00 


450 


07EE 


00 
36 


00 
7E 


00 


00 


CC 


76 


451 
452 


07 F6 


D8 


D8 


6E 


00 


00 


00 


453 


07 FC 


00 
FE 


00 
CC 


3E 


6C 


CC 


CC 


454 
455 


080U 


CC 


CC 


CE 


00 


00 


00 


456 


080A 


00 
C6 


10 
C6 


38 


6C 


00 


7C 


457 
458 


0812 


C6 


C6 


7C 


00 


00 


00 


459 


0818 


00 
C6 


00 
C6 


C6 


C6 


00 


7C 


460 
461 


0820 


C6 


C6 


7C 


00 


00 


00 


462 


0826 


00 
C6 


60 
C6 


30 


18 


00 


7C 


463 
464 


082E 


C6 


C6 


7C 


00 


00 


00 


465 


0834 


00 
CC 


30 
CC 


78 


CC 


00 


CC 


466 
467 


083C 


CC 


CC 


76 


00 


00 


00 


468 


0842 


00 
CC 


60 
CC 


30 


18 


00 


CC 


469 
470 


084A 


CC 


CC 


76 


00 


00 


00 


471 


0850 


00 
C6 


00 
C6 


C6 


C6 


00 


C6 


472 
473 


0858 


C6 


7E 


06 


OC 


78 


00 


474 


085E 


00 
C6 


C6 
C6 


C6 


38 


6C 


C6 


475 
476 


0866 


C6 


6C 


38 


00 


00 


00 


477 


086C 


00 
C6 


C6 
C6 


C6 


00 


C6 


C6 


478 
479 


0874 


C6 


C6 


7C 


00 


00 


00 


480 


087A 


00 
60 


18 
66 


18 


3C 


66 


60 


481 
482 


0882 


3C 


18 


18 


00 


00 


00 


483 


0888 


00 
60 


38 
60 


6C 


64 


60 


FO 


484 
485 


0890 


60 


E6 


FC 


00 


00 


00 


486 


0896 


00 
7E 


00 
18 


66 


66 


3C 


18 


487 
488 


089E 


7E 


18 


18 


00 


00 


00 


489 


08A4 


00 
CC 


F8 
DE 


CC 


CC 


F8 


C4 


490 
491 


08AC 


CC 


CC 


C6 


00 


00 


00 


492 


08B2 


00 
7E 


OE 
18 


IB 


18 


18 


18 


493 
494 


08BA 


18 


18 


18 


D8 


70 


00 


495 
496 


08C0 


00 
OC 


18 
7C 


30 


60 


00 


78 


497 
498 


08C8 


CC 


CC 


76 


00 


00 


00 


499 


08CE 


00 
18 


00 
18 


18 


30 


00 


38 


500 
501 


08D6 


18 


18 


3C 


00 


00 


00 


502 


08DC 


00 
C6 


18 
C5 


30 


60 


00 


7C 


503 
504 


08E4 


C6 


C6 


7C 


00 


00 


00 


505 


08 EA 


00 
CC 


18 

CC 


30 


60 


00 


CC 


506 
507 


08 F2 


CC 


CC 


76 


00 


00 


00 


508 


08 F8 


00 
66 


00 
66 


76 


DC 


00 


DC 


509 
510 


0900 


66 


66 


66 


00 


00 


00 


511 


0906 


76 
FE 


DC 
DE 


00 


C6 


E6 


F6 


512 
513 


090E 


CE 


C6 


C6 


00 


00 


00 


514 


091U 


00 
7E 


3C 
00 


6C 


6C 


3E 


00 


515 
516 


091C 


00 


00 


00 


00 


00 


00 


517 


0922 


00 
7C 


38 
00 


6C 


6C 


38 


00 


518 
519 


092A 


00 


00 


00 


00 


00 


00 


520 


0930 


00 
30 


00 
60 


30 


30 


00 


30 


521 
522 


0938 


C6 


C6 


7C 


00 


00 


00 


523 


093E 


00 
FE 


00 
CO 


00 


00 


00 


00 


524 
525 


0946 


CO 


CO 


00 


00 


00 


00 


526 


094C 


00 
FE 


00 
06 


00 


00 


00 


00 


527 
528 


0954 


06 


06 


00 


00 


00 


00 


529 


095A 


00 
30 


CO 
60 


CO 


C6 


CC 


08 


530 
531 


0962 


DC 


86 


OC 


18 


3E 


00 


532 


0968 


00 
30 


CO 
66 


CO 


C6 


CC 


D8 


533 
534 


0970 


CE 


9E 


3E 


06 


06 


00 


535 


0976 


00 
18 


00 
3C 


18 


18 


00 


18 


536 
537 


097E 


3C 


3C 


18 


00 


00 


00 


538 


0984 


00 
D8 


00 
6C 


00 


00 


36 


6C 


539 
540 


098C 


36 


00 


00 


00 


00 


00 


541 


0992 


00 
36 


00 
6C 


00 


00 


08 


6C 


542 
543 


099A 


D8 


00 


00 


00 


00 


00 


544 
545 


09A0 


11 
11 


44 
44 


11 


44 


11 


44 


546 
547 


09A8 


11 


44 


11 


44 


11 


44 


548 


09AE 


55 
55 


AA 
AA 


55 


AA 


55 


AA 


549 
550 


0986 


55 


AA 


55 


AA 


55 


AA 


551 


09BC 


DO 
DO 


77 
77 


DD 


77 


DD 


77 


552 
553 


09C4 


DO 


77 


DD 


77 


DD 


77 


554 


09CA 


18 
18 


18 
18 


18 


18 


18 


18 


555 
556 


0902 


18 


18 


18 


18 


18 


18 


557 


09D8 


18 
18 


18 
F8 


18 


18 


18 


18 


558 
559 


09 EO 


18 


18 


18 


18 


18 


18 


560 


09E6 


18 
18 


18 
F8 


18 


18 


18 


F8 


561 
562 


09EE 


18 


18 


18 


18 


18 


18 


563 


09 Fit 


36 
36 


36 
F6 


36 


36 


36 


36 


564 
565 


09 FC 


36 


36 


36 


36 


36 


36 


566 


0A02 


00 
00 


00 
FE 


00 


00 


00 


00 


567 
568 


OAOA 


36 


36 


36 


36 


36 


36 


569 



038H, 
OFEH, 
018H, 



06CH, 
0C6H, 
030H, 



038H, 
0C6H, 
060H, 



000H,038H, 
OOOH,OO0H, 
OOOH.OFEH, 



06CH,0C6H,0C6H 

OOOH 

066H,060H,07CH 



018H, 
OOOH, 



018H, 
018H, 



018H, 
030H; 



0D8H,070H, 
O6OH,OO0H, 



OOOH 
078H,00CH,07CH 



0D8H, 
011H, 



OOOH, 
044H, 



OOOH, 
011H, 



OOOH, OOOH, 
044H,011H, 



OOOH 
044H,011H,044H 



036H,036H,036H,036H,036H,036H 



TH_8F 
BT_8F 
TH_90 



BT_9F 
TH_AO 



BT_AF 
TH_BO 



August 2, 1984 



IBM Enhanced Graphics Adapter 157 



0A10 


00 
18 


00 
F8 


00 


00 


00 


F8 


570 
571 


0A18 


18 


18 


18 


18 


18 


18 


572 


0A1E 


36 
06 


36 
F6 


36 


36 


36 


F6 


573 
574 


0A26 


36 


36 


36 


36 


36 


36 


575 


0A2C 


36 
36 


36 
36 


36 


36 


36 


36 


576 
577 


0A3U 


36 


36 


36 


36 


36 


36 


578 


0A3A 


00 
06 


00 
F6 


00 


00 


00 


FE 


579 
580 


0AU2 


36 


36 


36 


36 


36 


36 


581 


0AU8 


36 
06 


36 
FE 


36 


36 


36 


F6 


582 
583 


0A50 


00 


00 


00 


00 


00 


00 


584 


OA56 


36 
36 


36 

FE 


36 


36 


36 


36 


585 
586 


0A5E 


00 


00 


00 


00 


00 


00 


587 


0A6U 


18 
18 


18 
F8 


18 


18 


18 


F8 


588 
589 


0A6C 


00 


00 


00 


00 


00 


00 


590 


0A72 


00 
00 


00 
F8 


00 


00 


00 


00 


591 
592 


0A7A 


18 


18 


18 


18 


18 


18 


593 
594 


OA80 


18 
18 


18 
IF 


18 


18 


18 


18 


595 
596 


0A88 


00 


00 


00 


00 


00 


00 


597 


0A8E 


18 
18 


18 
FF 


18 


18 


18 


18 


598 
599 


0A96 


00 


00 


00 


00 


00 


00 


600 


0A9C 


00 
00 


00 
FF 


00 


00 


00 


00 


601 
602 


0AA4 


18 


18 


18 


18 


18 


18 


603 


OAAA 


18 
18 


18 
IF 


18 


18 


18 


18 


604 
605 


0AB2 


18 


18 


18 


18 


18 


18 


606 


0AB8 


00 
00 


00 
FF 


00 


00 


00 


00 


607 
608 


OACO 


00 


00 


00 


00 


00 


00 


609 


0AC6 


18 
18 


18 
FF 


18 


18 


18 


18 


610 
611 


OACE 


18 


18 


18 


18 


18 


18 


612 


OADU 


18 
18 


18 

IF 


18 


18 


18 


IF 


613 
614 


OADC 


18 


18 


18 


18 


18 


18 


615 


0AE2 


36 
36 


36 
37 


36 


36 


36 


36 


616 
617 


OAEA 


36 


36 


36 


36 


36 


36 


618 


OAFO 


36 
30 


36 

3F 


36 


36 


36 


37 


619 
620 


0AF8 


00 


00 


00 


00 


00 


00 


621 


OAFE 


00 
30 


00 
37 


00 


00 


00 


3F 


622 
623 


0B06 


36 


36 


36 


36 


36 


36 


624 


OBOC 


36 
00 


36 
FF 


36 


36 


36 


F7 


625 
626 


OBIlt 


00 


00 


00 


00 


00 


00 


627 


0B1A 


00 
00 


00 
F7 


00 


00 


00 


FF 


628 
629 


0822 


36 


36 


36 


36 


36 


36 


630 


0B28 


36 
30 


36 
37 


36 


36 


36 


37 


631 
632 


0B30 


36 


36 


36 


36 


36 


36 


633 


0836 


00 
00 


00 
FF 


00 


00 


00 


FF 


634 
635 


0B3E 


00 


00 


00 


00 


00 


00 


636 


0B44 


36 
00 


36 

F7 


36 


36 


36 


F7 


637 
638 


08UC 


36 


36 


36 


36 


36 


36 


639 


0B52 


18 
00 


18 
FF 


18 


18 


18 


FF 


640 
641 


085A 


00 


00 


00 


00 


00 


00 


642 
643 


0B60 


36 
36 


36 

FF 


36 


36 


36 


36 


644 
645 


0B68 


00 


00 


00 


00 


00 


00 


646 


0B6E 


00 
00 


00 
FF 


00 


00 


00 


FF 


647 
648 


0876 


18 


18 


18 


18 


18 


18 


649 


0B7C 


00 
00 


00 
FF 


00 


00 


00 


00 


650 
651 


0884 


36 


36 


36 


36 


36 


36 


652 


0B8A 


36 
36 


36 
3F 


36 


36 


36 


36 


653 
654 


0892 


00 


00 


00 


00 


00 


00 


655 


0B98 


18 
18 


18 
IF 


18 


18 


18 


IF 


656 
657 


OBAO 


00 


00 


00 


00 


00 


00 


658 


08A6 


00 
18 


00 
IF 


00 


00 


00 


IF 


659 
660 


08AE 


18 


18 


18 


18 


18 


18 


661 


0884 


00 
00 


00 
3F 


00 


00 


00 


00 


662 
663 


0B8C 


36 


36 


36 


36 


36 


36 


664 


0BC2 


36 
36 


36 

FF 


36 


36 


36 


36 


665 
666 


08CA 


36 


36 


36 


36 


36 


36 


667 


OBDO 


18 
18 


18 
FF 


18 


18 


18 


FF 


668 
669 


0BD8 


18 


18 


18 


18 


18 


18 


670 


OBOE 


18 
18 


18 
F8 


18 


18 


18 


18 


671 
672 


08E6 


00 


00 


00 


00 


00 


00 


673 


08EC 


00 
00 


00 
IF 


00 


00 


00 


00 


674 
675 


08F4 


18 


18 


18 


18 


18 


18 


676 


08FA 


FF 
FF 


FF 
FF 


FF 


FF 


FF 


FF 


677 
678 


0C02 


FF 


FF 


FF 


FF 


FF 


FF 


679 


0C08 


00 
00 


00 
FF 


00 


00 


00 


00 


680 
681 


0C10 


FF 


FF 


FF 


FF 


FF 


FF 


682 


0C16 


FO 
FO 


FO 
FO 


FO 


FO 


FO 


FO 


683 
684 


0C1E 


FO 


FO 


FO 


FO 


FO 


FO 


685 


0C24 


OF 
OF 


OF 
OF 


OF 


OF 


OF 


OF 


686 
687 


0C2C 


OF 


OF 


OF 


OF 


OF 


OF 


688 


0C32 


FF 
FF 


FF 
00 


FF 


FF 


FF 


FF 


689 
690 


0C3A 


00 


00 


00 


00 


00 


00 


691 
692 


0C40 


00 
DC 


00 
08 


00 


00 


00 


76 


693 
694 


0C48 


D8 


DC 


76 


00 


00 


00 


695 



OOOH, OOOH, OOOH, OOOH, OOOH, 0F8H, 018H, 0F8H 



018H, 
018H, 



018H, 
018H, 



018H, 
018H, 



018H, 
018H, 



018H, 
018H, 



018H 
018H,018H,01FH 



OOOH, 
036H, 



OOOH, 
036H, 



OOOH, 
036H, 



OOOH, 
036H, 



OOOH, 
036H, 



OOOH 
,036H,036H,0FFH 



OOOH, 
OOOH, 
0D8H, 



OOOH, 
OOOH, 
ODCH, 



OOOH, 
OOOH, 
076H, 



OOOH, 
OOOH, 
OOOH, 



OOOH, 
OOOH, 
OOOH, 



OOOH 

076H,0DCH,0D8H 

OOOH 



BT_BF 
TH_CO 



BT_CF 
TH_DO 



BT_DF 
TH_EO 
BT_EO 



158 IBM Enhanced Graphics Adapter 



August 2, 1984 



OCUE 


00 
FC 


00 
C6 


00 


00 


70 


C6 


696 
697 


0C56 


C6 


FC 


CO 


CO 


HO 


00 


698 


0C5C 


00 
CO 


00 
CO 


FE 


06 


06 


CO 


699 
700 


0C6U 


CO 


CO 


CO 


00 


00 


00 


701 


0C6A 


00 
60 


00 
6C 


00 


00 


FE 


60 


702 
703 


0C72 


60 


6C 


60 


00 


00 


00 


704 


0C78 


00 
18 


00 
30 


FE 


06 


60 


30 


705 
706 


0C80 


60 


06 


FE 


00 


00 


00 


707 


0C86 


00 
D8 


00 
D8 


00 


00 


00 


7E 


708 
709 


0C8E 


D8 


D8 


70 


00 


00 


00 


710 


0C9U 


00 
66 


00 
66 


00 


00 


66 


66 


711 
712 


0C9C 


70 


60 


60 


CO 


00 


00 


713 


0CA2 


00 
18 


00 
18 


00 


00 


76 


DC 


71U 
715 


OCAA 


18 


18 


18 


00 


00 


00 


716 


OCBO 


00 
66 


00 
66 


7E 


18 


3C 


66 


717 
718 


0CB8 


30 


18 


7E 


00 


00 


00 


719 


OCBE 


00 
FE 


00 
06 


38 


6C 


C6 


06 


720 
721 


0CC6 


C6 


6C 


38 


00 


00 


00 


722 


OCCC 


00 
06 


00 
6C 


38 


6C 


06 


06 


723 
72U 


0CD4 


60 


6C 


EE 


00 


00 


00 


725 


OCDA 


00 
3E 


00 
66 


IE 


30 


18 


OC 


726 
727 


0CE2 


66 


66 


3C 


00 


00 


00 


728 


0CE8 


00 
DB 


00 
DB 


00 


00 


00 


7E 


729 
730 


OCFO 


7E 


00 


00 


00 


00 


00 


731 


0CF6 


00 
DB 


00 
F3 


03 


06 


7E 


DB 


732 
733 


OCFE 


7E 


60 


CO 


00 


00 


00 


73U 


ODOU 


00 
70 


00 
60 


10 


30 


60 


60 


735 
736 


ODOC 


60 


30 


10 


00 


00 


00 


737 


0D12 


00 
C6 


00 
C6 


00 


7C 


C6 


C6 


738 
739 


0D1A 


C6 


C6 


C6 


00 


00 


00 


740 
741 


0D20 


00 
FE 


00 
00 


00 


FE 


00 


00 


742 
743 


0D28 


00 


FE 


00 


00 


00 


00 


744 


0D2E 


00 
18 


00 
18 


00 


18 


18 


7E 


745 
746 


0D36 


00 


00 


FF 


00 


00 


00 


747 


0D3C 


00 
00 


00 
18 


30 


18 


OC 


06 


748 
749 


ODUU 


30 


00 


7E 


00 


00 


00 


750 


ODUA 


00 
30 


00 
18 


00 


18 


30 


60 


751 
752 


0D52 


OC 


00 


7E 


00 


00 


00 


753 


0D58 


00 
18 


00 
18 


OE 


IB 


IB 


18 


754 
755 


0D60 


18 


18 


18 


18 


18 


18 


756 


0D66 


18 
18 


18 
18 


18 


18 


18 


18 


757 
758 


0D6E 


D8 


D8 


70 


00 


00 


00 


759 


0D74 


00 
7E 


00 
00 


00 


18 


18 


00 


760 
761 


0D7C 


18 


18 


00 


00 


00 


00 


762 


0D82 


00 
00 


00 
76 


00 


00 


76 


DC 


763 
764 


0D8A 


DC 


00 


00 


00 


00 


00 


765 


0D90 


00 
00 


38 
00 


6C 


6C 


38 


00 


766 
767 


0D98 


00 


00 


00 


00 


00 


00 


768 


0D9E 


00 
18 


00 
18 


00 


00 


00 


00 


769 
770 


0DA6 


00 


00 


00 


00 


00 


00 


771 


ODAC 


00 
00 


00 
18 


00 


00 


00 


00 


772 
773 


0DB4 


00 


00 


00 


00 


00 


00 


774 


ODBA 


00 
OC 


OF 
EC 


OC 


OC 


00 


00 


775 
776 


0DC2 


60 


3C 


10 


00 


00 


00 


777 


0DC8 


00 
6C 


08 
00 


60 


60 


6C 


60 


778 
779 


ODDO 


00 


00 


00 


00 


00 


00 


780 


0D06 


00 
F8 


70 
00 


D8 


30 


60 


C8 


781 
782 


ODDE 


00 


00 


00 


00 


00 


00 


783 


0DE4 


00 
70 


00 
70 


00 


00 


7C 


70 


784 
785 


ODEC 


70 


70 


00 


00 


00 


00 


786 


0DF2 


00 
00 


00 
00 


00 


00 


00 


00 


787 
788 


ODFA 


00 


00 


00 


00 


00 


00 


789 


OEOO 














790 



OOOH, OOOH, OOOH, OOOH, 07CH, 0C6H, OFCH, 0C6H 

0C6H, OFCH, OOOH, OCOH, 040H, OOOH 

OOOH, OOOH, 0FEH,0C6H,0C6H, OOOH, OOOH, OOOH 

OCOH, OCOH, OCOH, OOOH, OOOH, OOOH 

OOOH, OOOH, OOOH, OOOH, FEH, 06CH, 06CH, 06CH 

06CH, 06CH, 06CH, OOOH, OOOH, OOOH 

OOOH, OOOH, OFEH,0C6H,060H,O30H, 01 8H,030H 

060H, 0C6H, OFEH, OOOH, OOOH, OOOH 

OOOH, OOOH, OOOH, OOOH, OOOH, 07EH, 0D8H, 0D8H 

0D8H, 0D8H, 070H, OOOH, OOOH, OOOH 

OOOH, OOOH, OOOH, OOOH, 066H, 066H, 066H, 066H 

07CH, 060H, 060H, OCOH, OOOH, OOOH 

OOOH, OOOH, OOOH, OOOH, 076H,0DCH,018H, 01 8H 

01 8H, 01 8H, 01 8H, OOOH, OOOH, OOOH 

OOOH, OOOH, 07EH, 01 8H, 03CH, 066H, 066H, 066H 

03CH, 01 8H,07EH, OOOH, OOOH, OOOH 

OOOH, OOOH, 038H, 06CH, 0C6H, 0C6H, OFEH, 0C6H 

0C6H, 06CH, 038H, OOOH, OOOH, OOOH 

OOOH, OOOH, 038H, 06CH, 0C6H, 0C6H, 0C6H, 06CH 

06CH, 06CH, OEEH, OOOH, OOOH, OOOH 
OO0H,000H,O1EH,O30H,018H,OOCH,O3EH,O66H 

066H, 066H, 03CH, OOOH, OOOH, OOOH 

OOOH, OOOH, OOOH, OOOH, OOOH, 07EH, ODBH, ODBH 

07EH, OOOH, OOOH, OOOH, OOOH, OOOH 

OOOH, OOOH, 003H,006H,07EH, ODBH, ODBH, 0F3H 

07EH, 060H, OCOH, OOOH, OOOH, OOOH 

OOOH, OOOH, 01 CH, 030H, 060H, 060H, 07CH, 060H 

060H,030H, 01 CH, OOOH, OOOH, OOOH 

OOOH, OOOH, OOOH, 07CH, 0C6H, 0C6H, 0C6H, 0C6H 



0C6H,( 
000H,( 



I, OOOH, 
I, OFEH, 



OOOH, OOOH 
OOOH, OOOH, 



OFEH, OOOH 
018H,018H 
00CH,018H 
030H,018H 
018H,018H 
018H,018H 
07EH,000H 
000H,076H 
OOOH, OOOH 
018H,018H 
000H,O18H 
OOCH,OECH 
06CH,000H 
0F8H,000H 
07CH,07CH 
OOOH, OOOH 



OOOH, OOOH, OOOH, OOOH, OOOH, OOOH 



BT_EF 
TH_FO 



0000 
0000 



PAGE, 120 

SUBTTL MONOCHROME CHARACTER GENERATOR - ALPHA SUPPLEMENT 
CODE SEGMENT PUBLIC 

PUBLIC CGMN_FDG 
CGMN_FDO LABEL BYTE 

STRUCTURE OF THIS FILE 

DB XXH WHERE XX IS THE HEX CODE FOR THE FOLLOWING CHAR 
DB [BYTES - 13 OF THAT CHARACTER] 

Db' OOH INDICATES NO MORE REPLACEMENTS TO BE DONE 



0009 

000 F 
0010 

0018 

001 E 
001 F 

0027 
002D 
002E 



00 00 00 00 24 66 

FF 66 

24 00 00 00 00 00 

22 

00 63 63 63 22 00 

00 00 

00 00 00 00 00 00 

2B 

00 00 00 18 18 18 

FF 18 

18 18 00 00 00 00 



OOOH, OOOH, OOOH, OOOH, 024H,066H,0FFH,066H ; TH_1D 

024H, OOOH, OOOH, OOOH, OOOH, OOOH ; BT_1D 

022H ; 

OOOH, 063H,063H,063H,022H, OOOH, OOOH, OOOH ; TH_22 ' 

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ; BT_22 ' 

02BH 

OOOH, OOOH, OOOH, 018H,018H,018H,OFFH,018H ; TH_2B h 

018H,018H, OOOH, OOOH, OOOH, OOOH ; BT_2B n 

02DH ; 

OOOH, OOOH, OOOH, OOOH, OOOH. OOOH, OFFH, OOOH ; TH_2D ■ 



August 2, 1984 



IBM Enhanced Graphics Adapter 159 



0036 


00 00 


00 


00 


00 


00 


003C 


no 










003D 


00 00 
C3 C3 


03 


E7 


FF 


DB 


0045 


C3 C3 


03 


00 


00 


00 


OOUB 


5U 










OOUC 


00 00 
18 18 


FF 


DB 


99 


18 


005U 


18 18 


3C 


00 


00 


00 


005A 


56 










005B 


00 00 
C3 C3 


C3 


C3 


C3 


C3 


0063 


66 3C 


18 


00 


00 


00 


0069 


57 










006A 


00 00 
DB DB 


C3 


C3 


C3 


C3 


0072 


FF 66 


66 


00 


00 


00 


0078 


58- 










0079 


00 00 
18 3C 


C3 


C3 


66 


3C 


0081 


66 C3 


C3 


00 


00 


00 


0087 


59 










0088 


00 00 
30 18 


C3 


C3 


C3 


66 


0090 


18 18 


3C 


00 


00 


00 


0096 


5A 










0097 


00 00 
18 30 


FF 


C3 


86 


OC 


009F 


61 C3 


FF 


00 


00 


00 


00A5 


60 










00A6 


00 00 
FF DB 


00 


00 


00 


E6 


OOAE 


DB DB 


DB 


00 


00 


00 


O0B4 


76 










0085 


00 00 
C3 C3 


00 


00 


00 


C3 


OOBD 


66 3C 


18 


00 


00 


00 


00C3 


77 










OOCU 


00 00 
C3 DB 


00 


00 


00 


C3 


OOCC 


DB FF 


66 


00 


00 


00 


00D2 


91 










00D3 


00 00 
IB 7E 


00 


00 


6E 


3B 


OODB 


D8 DC 


77 


00 


00 


00 


O0E1 


9B 










00E2 


00 18 
CO C3 


18 


7E 


C3 


CO 


00 EA 


7E 18 


18 


00 


00 


00 


00 FO 


9D 










oon 


00 00 
FF 18 


C3 


66 


30 


18 


00 F9 


FF 18 


18 


00 


00 


00 


OOFF 


9E 










0100 


00 FC 
66 6F 


66 


66 


70 


62 


0108 


66 66 


F3 


00 


00 


00 


010E 


F1 










010F 


00 00 
18 18 


18 


18 


18 


FF 


0117 


18 00 


FF 


00 


00 


00 


011D 


F6 










011E 


00 00 
FF 00 


18 


18 


00 


00 


0126 


00 18 


18 


00 


00 


00 


012C 


00 










012D 













OOOH 
0«tDH 
OOOH 

0C3H 
05UH 
OOOH. 

018H 
056H 
OOOH; 

066H 
057H 
OOOH. 

OFFH 
058H 
OOOH; 

066H 
059H 
OOOH; 

018H 
05AH 
OOOH 



ODBH 
076H 
OOOH; 

066H 
077H 
OOOH; 

ODBH 
091H 
OOOH; 

0D8H; 
09BH 
OOOH; 

07EH, 
09DH 
OOOH, 

OFFH; 
09EH 
OOOH, 

066H, 
0F1H 
OOOH, 

018H; 
0F6H 
OOOH 



, OOOH, OOOH, OOOH, 
,000H,0C3H,0E7H, 
,OC3H,OC3H,OOOH, 
,OO0H,OFFH,ODBH, 
,018H,03CH,000H, 
,OOOH,OC3H,OC3H, 
,03CH,018H,000H, 
,OOOH,OC3H,OC3H, 
,066H,066H,000H, 
,OOOH,OC3H,OC3H, 
,OC3H,OC3H,OOOH, 
,0O0H,0C3H,OC3H, 
,018H.03CH,000H, 
OOOH, OFFH, 0C3H, 
,0C3H. OFFH, OOOH, 
OOOH, OOOH, OOOH, 
, ODBH, ODBH, OOOH, 
OOOH, OOOH, OOOH, 
,03CH,018H,000H, 
, OOOH, OOOH, OOOH, 
,0FFH,066H,000H, 
OOOH, OOOH, OOOH, 
.0DCH,077H,000H, 
,018H,018H,07EH, 
018H,018H,000H, 
,000H,0C3H,066H, 
,018H,018H,000H, 
0FCH,066H,066H, 
066H,0F3H,000H, 
000H,018H,018H, 
OOOH, OFFH, OOOH, 
.000H,018H,018H, 
,018H,018H,00OH, 



OOOH, OOOH 


BT_2D 


- 




OFFH, ODBH, OC3H,OC3H 


TH_4D 


M 




OOOH, OOOH 


BT_4D 


M 




099H,018H,018H,018H 


TH_5U 


T 




OOOH, OOOH 


BT_5»t 


T 




0C3H,OC3H,OC3H,OC3H 


TH_56 


V 




OOOH, OOOH 


BT_56 


V 




OC3H,OC3H, ODBH, ODBH 


TH_57 


w 




OOOH, OOOH 


BT_57 


w 




066H,03CH,018H,03CH 


TH_58 


X 




OOOH, OOOH 


BT_58 


X 




0C3H,066H,03CH,018H 


TH_59 


Y 




OOOH, OOOH 


BT_59 


Y 




086H,OOCH,018H,030H 


TH_5A 


z 




OOOH, OOOH 


BT_5A 


z 




000H,0E6H,0FFH,0DBH 


TH_6D 


L.C. 


M 


OOOH, OOOH 


BT_6D 


L.C. 


M 


O00H,0C3H,OC3H,OC3H 


TH_76 


L.C. 


V 


OOOH. OOOH 


BT_76 


L.C. 


V 


OOOH, OC3H,OC3H, ODBH 


TH_77 


L.C. 


W 


OOOH, OOOH 


BT_77 


L.C. 


W 


06EH,03BH,O1BH,O7EH 


TH_91 






OOOH, OOOH 


BT_91 






0C3H, OCOH, OCOH, 0C3H 


TH_9B 






OOOH, OOOH 


BT_9B 






03CH,018H,OFFH,018H 


TH_9D 






OOOH, OOOH 


BT_9D 






07CH, 062H, 066H, 06FH 


TH_9E 






OOOH, OOOH 


BT_9E 






018H,0FFH,O18H,O18H 


TH_F1 






OOOH, OOOH 


BT_F1 






OOOH, OOOH, OFFH, OOOH 


TH_F6 






OOOH, OOOH 


BT F6 
NO MORE 





0000 














0000 














0000 


00 
00 


00 
00 


00 


00 


00 


00 


0008 


7E 
81 


81 

7E 


A5 


81 


60 


99 


0010 


7E 
FF 


FF 
7E 


DB 


FF 


C3 


E7 


0018 


6C 
10 


FE 
00 


FE 


FE 


70 


38 


0020 


10 
10 


38 
00 


70 


FE 


7C 


38 


0028 


38 
38 


7C 
7C 


38 


FE 


FE 


70 


0030 


10 
38 


10 
7C 


38 


7C 


FE 


70 


0038 


00 
00 


00 
00 


18 


30 


30 


18 


ooto 


FF 
FF 


FF 
FF 


E7 


C3 


C3 


E7 


00U8 


00 
30 


3C 
00 


66 


42 


42 


66 


0050 


FF 
C3 


C3 
FF 


99 


BD 


BD 


99 


0058 


OF 
CC 


07 
78 


OF 


7D 


CO 


CC 


0060 


3C 
7E 


66 
18 


66 


66 


30 


18 


0068 


3F 
FO 


33 
EO 


3F 


30 


30 


70 


0070 


7F 
E6 


63 
CO 


7F 


63 


63 


67 


0078 


99 
5A 


5A 
99 


30 


E7 


E7 


30 


0080 


80 
80 


EO 
00 


F8 


FE 


F8 


EO 


0088 


02 
02 


OE 
00 


3E 


FE 


3E 


OE 


0090 


18 
3C 


3C 
18 


7E 


18 


18 


7E 


0098 


66 
66 


66 
00 


66 


66 


66 


00 


OOAO 


7F 
IB 


DB 
00 


DB 


7B 


18 


IB 


00A8 


3E 
CC 


63 
78 


38 


60 


60 


38 


OOBO 


00 
7E 


00 
00 


00 


00 


7E 


7E 


00B8 


18 
18 


3C 
FF 


7E 


18 


7E 


3C 


0000 


18 


30 


7E 


18 


18 


18 



PAGE, 120 

SUBTTL DOUBLE DOT CHARACTER GENERATOR 

CODE SEGMENT PUBLIC 

PUBL I C OGDDOT, I NT_1 F_1 

CGDDOT LABEL BYTE 

DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, ( 

DB 07EH,081H,0A5H,O81H,0BDH,099H,O81H,( 

DB 07EH, OFFH, ODBH, OFFH, 0C3H,0E7H, OFFH, ( 

DB 06CH,0FEH,0FEH,0FEH,07CH,038H,010H,( 

DB 010H, 038H, 07CH, OFEH, 07CH, 038H, 010H, ( 

DB 038H, 07CH, 038H, OFEH, OFEH, 07CH, 038H, ( 

DB 010H, 01 OH, 038H, 07CH, OFEH, 07CH, 038H, ( 

DB OOOH, OOOH, 01 8H.03OH,03CH, 01 8H, OOOH, ( 

DB OFFH, OFFH, 0E7H,0C3H,0C3H,0E7H, OFFH, ( 

DB OOOH, 03CH, 066H, 042H, 0U2H, 066H, 03CH, ( 

DB OFFH, 0C3H, 099H, OBDH, OBDH, 099H, 003H, ( 

DB OOFH, 007H, OOFH, 07DH, OCCH, OOOH, OCOH, ( 

DB 03CH, 066H, 066H, 066H, 03CH, 01 8H, 07EH, ( 

DB 03FH,033H,03FH,030H,030H,070H,0F0H,( 

DB 07FH, 063H, 07FH, 063H, 063H, 067H, 0E6H, ( 

DB 099H, 05AH, 03CH, 0E7H, 0E7H, 03CH, 05AH, ( 

DB 080H, OEOH, 0F8H, OFEH, 0F8H, OEOH, 080H, ( 

DB 002H,00EH,03EH,0FEH,03EH,00EH,002H,( 

DB 018H,03CH,07EH,018H,018H,07EH,03CH,( 

DB 066H, 066H, 066H, 066H, 066H, OOOH, 066H, ( 

DB 07FH, ODBH, ODBH, 07BH, 01 BH, 01 BH, 01 BH, ( 

DB 03EH,063H,038H,06CH,06CH,038H,00CH,( 

DB OOOH, OOOH, OOOH, OOOH, 07EH, 07EH, 07EH, ( 

DB 018H, 03CH, 07EH, 018H, 07EH, 03CH, 018H, ( 

DB 018H,03CH,07EH,018H,018H,018H,018H,0 



OOOH 


DOUBLE DOT 
D_00 


07EH 


D_01 


07EH 


D_02 


OOOH 


D_03 


OOOH 


D_04 


07CH 


D_05 


07CH 


D_06 


OOOH 


D_07 


OFFH 


D_08 


OOOH 


D_09 


OFFH 


D_OA 


078H 


D_OB 


018H 


D_OC 


OEOH 


D_OD 


OCOH 


D_OE 


099H 


D_OF 


OOOH 


D_10 


OOOH 


D_11 


018H 


D_12 


OOOH 


D_13 


OOOH 


D_14 


078H 


D_15 


OOOH 


D_16 


OFFH 


D_17 


OOOH 


D_18 



160 IBM Enhanced Graphics Adapter 



August 2, 1984 





18 


00 










57 


00C8 


18 
18 


18 
00 


18 


18 


7E 


30 


58 
59 


OODO 


00 
00 


18 
00 


00 


FE 


00 


18 


60 
61 


00D8 


00 
00 


30 
00 


60 


FE 


60 


30 


62 
63 


OOEO 


00 
00 


00 
00 


CO 


CO 


CO 


FE 


64 
65 


00E8 


00 
00 


24 
00 


66 


FF 


66 


24 


66 
67 


00 FO 


00 
00 


18 
00 


30 


7E 


FF 


FF. 


68 
69 


OOFS 


00 
00 


FF 
00 


FF 


7E 


30 


18 


70 
71 
72 


0100 


00 
00 


00 
00 


00 


00 


00 


00 


73 
74 


0108 


30 
30 


78 
00 


78 


30 


30 


00 


75 
76 


0110 


6C 
00 


6C 
00 


60 


00 


00 


00 


77 
78 


0118 


60 
60 


6C 
00 


FE 


60 


FE 


60 


79 
80 


0120 


30 
30 


7C 
00 


CO 


78 


OC 


F8 


81 
82 


0128 


00 
C6 


06 
00 


CO 


18 


30 


66 


83 
84 


0130 


38 
76 


60 
00 


38 


76 


DC 


00 


85 
86 


0138 


60 
00 


60 
00 


00 


00 


00 


00 


87 
88 


0140 


18 
18 


30 
00 


60 


60 


60 


30 


89 
90 


01U8 


60 
60 


30 
00 


18 


18 


18 


30 


91 
92 


0150 


00 
00 


66 
00 


30 


FF 


3C 


66 


93 
94 


0158 


00 
00 


30 
00 


30 


FC 


30 


30 


95 
96 


0160 


00 
30 


00 
60 


00 


00 


00 


30 


97 
98 


0168 


00 
00 


00 
00 


00 


FC 


00 


00 


99 
100 


0170 


00 
30 


00 
00 


00 


00 


00 


30 


101 
102 


0178 


06 
80 


00 
00 


18 


30 


60 


00 


103 
104 
105 


0180 


70 
70 


06 
00 


CE 


DE 


F6 


E6 


106 
107 


0188 


30 
FC 


70 
00 


30 


30 


30 


30 


108 
109 


0190 


78 
FC 


OC 
00 


00 


38 


60 


00 


110 

111 


0198 


78 
78 


OC 
00 


00 


38 


OC 


CC 


112 
113 


01 AO 


10 
IE 


3C 
00 


60 


CO 


FE 


OC 


114 
115 


01 A8 


FC 
78 


CO 
00 


F8 


00 


00 


CO 


116 
117 


01 BO 


38 
78 


60 
00 


CO 


F8 


OC 


CO 


118 
119 


01 B8 


FC 
30 


OC 
00 


00 


18 


30 


30 


120 

121 


01C0 


78 
78 


OC 
00 


CO 


78 


CC 


CO 


122 
123 


01 C8 


78 
70 


OC 
00 


CO 


70 


00 


18 


124 
125 


01 DO 


00 
30 


30 
00 


30 


00 


00 


30 


126 
127 


01 D8 


00 
30 


30 
60 


30 


00 


00 


30 


128 
129 


01 EO 


18 
18 


30 
00 


60 


CO 


60 


30 


130 
131 


01 E8 


00 
00 


00 
00 


FO 


00 


00 


FO 


132 
133 


01 FO 


60 
60 


30 
00 


18 


00 


18 


30 


134 
135 


01 F8 


78 
30 


OC 
00 


00 


18 


30 


00 


136 
137 
138 


0200 


7C 
78 


06 
00 


DE 


DE 


DE 


CO 


139 
140 


0208 


30 
CO 


78 
00 


CC 


CC 


FC 


CC 


141 
142 


0210 


FC 
FC 


66 
00 


66 


70 


66 


66 


143 
144 


0218 


30 
3C 


66 
00 


CO 


00 


CO 


66 


145 
146 


0220 


F8 
F8 


6C 
00 


66 


66 


66 


60 


147 
148 


0228 


FE 
FE 


62 
00 


68 


78 


68 


62 


149 
150 


0230 


FE 
FO 


62 
00 


68 


78 


68 


60 


151 
152 


0238 


3C 
3E 


66 
00 


CO 


CO 


OE 


66 


153 
154 


02U0 


CO 
CC 


CC 
00 


CC 


FC 


CC 


CC 


155 
156 


0248 


78 
78 


30 
00 


30 


30 


30 


30 


157 
158 


0250 


IE 
78 


OC 
00 


00 


00 


OC 


00 


159 
160 


0258 


E6 
E6 


66 
00 


60 


78 


6C 


66 


161 
162 


0260 


FO 
FE 


60 
00 


60 


60 


62 


66 


163 
164 


0268 


06 
06 


EE 
00 


FE 


FE 


D6 


06 


165 
166 


0270 


06 
06 


E6 
00 


F6 


DE 


OE 


06 


167 
168 


0278 


38 
38 


6C 
00 


06 


C6 


06 


60 


169 
170 
171 


0280 


FC 
FO 


66 
00 


66 


70 


60 


60 


172 
173 


0288 


78 
1C 


CC 
00 


00 


00 


DC 


78 


174 
175 


0290 


FC 
E6 


66 
00 


66 


70 


6C 


66 


176 
177 


0298 


78 
78 


CC 
00 


EO 


70 


10 


00 


178 
179 


02A0 


FC 
78 


84 
00 


30 


30 


30 


30 


180 
181 


02A8 


CC 


OC 


00 


00 


00 


CC 


182 



018H,018H,018H,018H,07EH,03CH,018H,000H ; D_19 

000H,018H,00OH,0FEH,00CH,018H,000H,000H ; D_1A 

OOOH,030H,060H,OFEH,060H.030H,OOOH,OOOH ; D_1B 

000H,000H,0C0H,0O0H,0O0H,0FEH,000H,000H ; D_10 

000H,024H,066H,0FFH,066H,024H,000H,000H ; D_1D 

000H,018H,03OH,07EH,0FFH,0FFH,000H,000H ; D_1E 

000H,0FFH,0FFH,07EH,03CH,018H,000H,000H ; D_1F 



OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH 


SP D_20 


030H,078H,078H,030H,030H,OOOH,030H,OOOH 


! 


D_21 


060H, 06CH, 060H, OOOH, OOOH, OOOH, OOOH, OOOH 


" 


D_22 


060H, 06CH, OFEH, 06CH, OFEH, 06CH, 060H, OOOH 


# 


D_23 


030H, 07CH, OOOH, 078H, OOCH, 0F8H, 030H, OOOH 


$ 


D_24 


OOOH, OC6H,0COH,O18H,030H,O66H,0C6H. OOOH 


PER CENT D_25 


038H, 06CH, 038H, 076H, OOCH, OCCH, 076H, OOOH 


&: 


D_26 


060H, 060H, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH 


' 


D_27 


018H, 030H, 060H, 060H, 060H, 030H, 01 8H, OOOH 


( 


D_28 


060H,030H,018H,018H,018H,030H,060H,OOOH 


) 


D_29 


OOOH, 066H, 030H, OFFH, 03CH, 066H, OOOH, OOOH 


* 


D_2A 


OOOH, 030H, 030H, OFOH, 030H, 030H, OOOH, OOOH 


+ 


D_2B 


OOOH. OOOH, OOOH, OOOH, OOOH, 030H, 030H, 060H 




D_20 


OOOH, OOOH, OOOH, OFOH, OOOH, OOOH, OOOH, OOOH 


- 


D_2D 


OOOH, OOOH, OOOH, OOOH, OOOH, 030H, 030H, OOOH 




D_2E 


006H, OOCH, 018H, 030H, 060H, OOOH, 080H, OOOH 


/ 


D_2F 


07CH,0C6H,0CEH,ODEH,0F6H,OE6H,07OH,000H 





D_30 


030H,070H,030H,030H,030H,030H, OFOH, OOOH 


1 


D_31 


078H, OOOH, OOOH, 038H, 060H, OOCH, OFOH, OOOH 


2 


D_32 


078H, OOCH, OOOH, 038H, OOCH, OCCH, 078H, OOOH 


3 


D_33 


01 OH, 03CH, 060H, OOOH, OFEH, OOCH, 01 EH, OOOH 


4 


D_34 


OFOH, OOOH, 0F8H, OOOH, OOCH, OCCH, 078H, OOOH 


5 


D_35 


038H, 060H, OOOH, 0F8H, OOCH, OCCH, 078H, OOOH 


6 


D_36 


OFOH, OCCH, OOOH, O18H,O30H,O30H,O3OH, OOOH 


7 


D_37 


078H, OCCH, OCCH, 078H, OOCH, OCCH, 078H, OOOH 


8 


D_38 


078H, OCCH, OCCH, 070H, OOCH, 018H, 070H, OOOH 


9 


D_39 


OOOH, 030H,030H, OOOH, OOOH, O30H,03OH, OOOH 




D_3A 


OOOH, O30H,O3OH, OOOH, OOOH, 030H,030H,060H 




D_3B 


018H, 030H, 060H, OOOH, 060H, 030H, 018H, OOOH 


< 


D_30 


OOOH, OOOH, OFOH, OOOH. OOOH, OFOH, OOOH, OOOH 


= 


D_3D 


060H, 030H, 018H, OOOH, 01 8H, 030H, 060H, OOOH 


> 


D_3E 


078H, OOCH, OOOH, 018H,030H, OOOH, 030H, OOOH 


? 


D_3F 


070H, 006H, ODEH, ODEH, ODEH, OOOH, 078H, OOOH 


@ 


D_40 


030H, 078H, OCCH, OCCH, OFCH, OCCH, OCCH, OOOH 


A 


D_41 


OFOH, 066H,066H,070H,066H,066H, OFOH, OOOH 


B 


D_42 


030H, 066H, OOOH, OCOH, OCOH, 066H, 030H, OOOH 





D_43 


0F8H,06OH,066H,066H,O66H,06CH,OF8H,000H 


D 


D_44 


OFEH, 062H,068H,078H,068H,062H, OFEH, OOOH 


E 


D_45 


OFEH, 062H, 068H, 078H, 068H, 060H, OFOH, OOOH 


F 


D_46 


03CH, 066H, OOOH, OCOH, OOEH, 066H, 03EH, OOOH 


G 


D_47 


OCCH, OCCH, OCCH, OFCH, OCCH, OCCH, OCCH, OOOH 


H 


D_48 


078H, 030H, 030H, 030H, 030H, 030H, 078H, OOOH 


1 


D_49 


01 EH, OOCH, OOOH, OOOH, OOCH, OOCH, 078H, OOOH 


J 


D_4A 


0E6H, 066H, 06CH, 078H, 06CH, 066H, 0E6H, OOOH 


K 


D_4B 


OFOH, 060H, 060H, 060H, 062H, 066H. OFEH, OOOH 


L 


D_40 


006H, OEEH, OFEH, OFEH, 0D6H, 006H, 006H, OOOH 


M 


D_4D 


0O6H,0E6H,0F6H, ODEH, OOEH, 0C6H,0C6H, OOOH 


N 


D_4E 


038H, 06CH, 0C6H, 0C6H, 0C6H, 06CH, 038H, OOOH 





D_4F 



OFOH, 066H,066H,O7OH,060H,060H, OFOH, OOOH ; P D_50 

078H, OOCH, OOOH, OCOH, OOCH, 078H, 01 OH, OOOH ; Q D_51 

OFOH, O66H,066H,07OH,06CH,066H,0E6H, OOOH ; R D_52 

078H, OOCH, 0E0H,070H, 01 CH, OOCH, 078H, OOOH ; S D_53 

OFCH. 0B4H,030H,030H,030H,030H,078H, OOOH ; T D_54 

OOOH, OOCH. OOOH. OCOH. OOCH. OOCH. OFOH. OOOH ; U D_55 



August 2, 1984 



IBM Enhanced Graphics Adapter 161 





FC 


00 








183 


02B0 


CC 
30 


CC 
00 


CC CC 


CC 


78 


184 
185 


02B8 


C6 
C6 


C6 
00 


C6 D6 


FE 


EE 


186 
187 


02C0 


C6 
C6 


C6 
00 


60 38 


38 


6C 


188 
189 


02C8 


CC 
78 


CC 
00 


CC 78 


30 


30 


190 
191 


02D0 


FE 
FE 


C6 
00 


80 18 


32 


66 


192 
193 


02D8 


78 
78 


60 
00 


60 60 


60 


60 


194 
195 


02E0 


CO 
02 


60 
00 


30 18 


OO 


06 


196 
197 


02E8 


78 
78 


18 
00 


18 18 


18 


18 


198 
199 


02 FO 


10 
00 


38 
00 


60 C6 


00 


00 


200 
201 


02F8 


00 
00 


00 
FF 


00 00 


00 


00 


202 
203 
204 


0300 


30 
00 


30 
00 


18 00 


00 


00 


205 
206 


0308 


00 
76 


00 
00 


78 OC 


70 


CC 


207 
208 


0310 


EO 
DC 


60 
00 


60 7C 


66 


66 


209 
210 


0318 


00 
78 


00 
00 


78 CC 


CO 


CC 


211 
212 


0320 


1C 
76 


OC 
00 


OC 7C 


CO 


CC 


213 

214 


0328 


00 
78 


00 
00 


78 CC 


FO 


CO 


215 
216 


0330 


38 

FO 


6C 
00 


60 FO 


60 


60 


217 
218 


0338 


00 
OC 


00 
F8 


76 CC 


CO 


7C 


219 
220 


0340 


EO 
E6 


60 
00 


60 76 


66 


66 


221 
222 


0348 


30 
78 


00 
00 


70 30 


30 


30 


223 

224 


0350 


OC 
CC 


00 
78 


00 OC 


OO 


CC 


225 
226 


0358 


EO 
E6 


60 
00 


66 6C 


78 


60 


227 
228 


0360 


70 
78 


30 
00 


30 30 


30 


30 


229 
230 


0368 


00 
C6 


00 
00 


CO FE 


FE 


D6 


231 
232 


0370 


00 
CC 


00 
00 


F8 CC 


CO 


CC 


233 
234 


0378 


00 
78 


00 
00 


78 CC 


CO 


CC 


235 
236 
237 


0380 


00 
60 


00 
FO 


DO 66 


66 


70 


238 
239 


0388 


00 
OC 


00 
IE 


76 CC 


CC 


70 


240 
241 


0390 


00 
FO 


00 
00 


DC 76 


66 


60 


242 

243 


0398 


00 
F8 


00 
00 


70 CO 


78 


OC 


244 
245 


03A0 


10 
18 


30 
00 


70 30 


30 


34 


246 
247 


03A8 


00 
76 


00 
00 


CC CC 


CO 


CC 


248 
249 


03B0 


00 
30 


00 
00 


CC CC 


CO 


78 


250 
251 


03B8 


00 
6C 


00 
00 


C6 D6 


FE 


FE 


252 
253 


03C0 


00 
C6 


00 
00 


C6 6C 


38 


6C 


254 
255 


03C8 


00 
OC 


00 
F8 


CC CC 


CC 


70 


256 
257 


03D0 


00 
FC 


00 
00 


FC 98 


30 


64 


258 
259 


03D8 


1C 
1C 


30 
00 


30 EO 


30 


30 


260 
261 


03 EO 


18 
18 


18 
00 


18 00 


18 


18 


262 
263 


03E8 


EO 
EO 


30 
00 


30 1C 


30 


30 


264 
265 


03 FO 


76 
00 


DC 
00 


00 00 


00 


00 


266 
267 


03 F8 


00 
FE 


10 
00 


38 60 


C6 


06 


268 
269 
270 


0400 












271 
272 


0400 


78 
OC 


CC 
78 


CO CC 


78 


18 


273 
274 


0408 


00 
7E 


CC 
00 


00 CC 


CO 


CC 


275 
276 


0410 


1C 
78 


00 
00 


78 CC 


FC 


CO 


277 
278 


0418 


7E 
3F 


C3 
00 


30 06 


3E 


66 


279 
280 


0420 


CC 
7E 


00 
00 


78 OC 


7C 


CC 


281 
282 


0428 


EO 
7E 


00 
00 


78 OC 


70 


CC 


283 
284 


0430 


30 
7E 


30 
00 


78 OC 


70 


CC 


285 
286 


0438 


00 
OC 


00 
38 


78 CO 


CO 


78 


287 
288 


0440 


7E 
3C 


C3 
00 


30 66 


7E 


60 


289 
290 


0448 


CC 
78 


00 
00 


78 CC 


FO 


CO 


291 
292 


0450 


EO 
78 


00 
00 


78 CC 


FO 


CO 


293 
294 


0458 


CC 
78 


00 
00 


70 30 


30 


30 


295 
296 


0460 


7C 
3C 


C6 
00 


38 18 


18 


18 


297 
298 


0468 


EO 
78 


00 
00 


70 30 


30 


30 


299 
300 


0470 


C6 
C6 


38 
00 


6C 06 


FE 


06 


301 
302 


0478 


30 
CC 


30 
00 


00 78 


CC 


FC 


303 
304 
305 


0480 


1C 
FC 


00 
00 


FC 60 


78 


60 


306 
307 


0488 


00 


00 


7F OC 


7F 


CC 


308 



OCCH, OCCH, OCCH, OCCH, OCCH, 078H, 030H, OOOH 


V D_56 




OC6H,OC6H,OC6H,OD6H,OFEH,0EEH,OC6H,OOOH 


W D_57 




0C6H, 0C6H, 06CH, 038H, 038H, 06CH, 0C6H, OOOH 


X D_58 




OCCH, OCCH, OCCH, 078H,030H,030H,078H, OOOH 


Y D_59 




0FEH,0C6H,08CH,018H,032H,066H,OFEH,000H 


Z D_5A 




078H, 060H, 060H, 060H, 060H, 060H, 078H, OOOH 


[ D_5B 




OCOH, 060H, 030H, 01 8H, OOOH, 006H, 002H, OOOH 


BACKSLASH D_5C 


078H,018H,018H,018H,018H,018H.078H.000H 


] D_5D 




01 OH, 038H, 06CH, 0C6H, OOOH, OOOH, OOOH, OOOH 


CIRCUMFLEX D_5E 


OOOH, OOOH, OOOH. OOOH, OOOH, OOOH, OOOH, OFFH 


_ D_5F 




030H, 030H, 01 8H, OOOH, OOOH, OOOH, OOOH, OOOH 


• D_60 




OOOH, OOOH, 078H, OOOH, 07CH, OCCH, 076H, OOOH 


LOWER CASE A D_61 


OEOH, 060H, 060H, 07CH, 066H, 066H, ODCH, OOOH 


L.C. B 


D_62 


OOOH, OOOH, 078H, OCCH, OCOH, OCCH, 078H, OOOH 


L.C. C 


D_63 


01 CH, OOOH, OOCH, 07CH, OCCH, OCCH, 076H, OOOH 


L.C. D 


D_64 


OOOH, OOOH, 078H, OCCH, OFCH, OCOH, 078H, OOOH 


L.C. E 


D_65 


038H,06CH,060H,0F0H,060H,060H,0F0H,000H 


L.C. F 


D_66 


OOOH, OOOH, 076H, OCCH, OCCH, 07CH, OOCH, 0F8H 


L.C. G 


D_67 


OEOH, 060H, 06CH, 076H, 066H, 066H, 0E6H, OOOH 


L.C. H 


D_68 


030H, OOOH, 070H, 030H, 030H, 030H, 078H, OOOH 


L.C. 1 


D_69 


OOCH, OOOH, OOCH, OOCH, OOCH, OCCH, OCCH, 078H 


L.C. J 


D_6A 


OEOH, 060H, 066H, 06CH, 078H, 06CH, 0E6H, OOOH 


L.C. K 


0_6B 


070H, 030H, 030H, 030H, 030H, 030H, 078H, OOOH 


L.C. L 


D_6C 


OOOH, OOOH, OCCH, OFEH, OFEH, 0D6H, 0C6H, OOOH 


L.C. M 


D_6D 


OOOH, OOOH, 0F8H, OCCH, OCCH, OCCH, OOCH, OOOH 


L.C. N 


D_6E 


OOOH, OOOH, 078H, OCCH, OCCH, OCCH, 078H, OOOH 


L.C. 


D_6F 


OOOH, OOOH, ODCH, 066H, 066H, 07CH, 060H, OFOH 


L.C. P 


D_70 


OOOH, 000H,076H, OCCH, OCCH, 07CH,00CH, 01 EH 


L.C. Q 


D_71 


OOOH, OOOH, ODCH, 076H, 066H, 060H, OFOH, OOOH 


L.C. R 


D_72 


OOOH, OOOH, 07CH, OCOH, 078H, OOCH, 0F8H, OOOH 


L.C. S 


D_73 


010H,030H,07CH,030H,030H,034H,018H,OOOH 


L.C. T 


D_74 


OOOH, OOOH, OCCH, OCCH, OCCH, OCCH, 076H, OOOH 


L.C. U 


D_75 


OOOH, OOOH, OCCH, OCCH, OCCH, 078H, 030H, OOOH 


L.C. V 


D_76 


OOOH, OOOH, OC6H,0D6H,OFEH,OFEH,06CH, OOOH 


L.C. W 


D_77 


OOOH, OOOH, 0C6H, 06CH, 038H, 06CH, 0C6H, OOOH 


L.C. X 


D_78 


OOOH, OOOH, OCCH, OCCH, OCCH, 07CH, OOCH, 0F8H 


L.C. Y 


D_79 


OOOH, OOOH, OFCH, 098H, 030H, 064H, OFOH, OOOH 


L.C. Z 


D_7A 


01CH,030H,030H, OEOH, 030H,030H,01OH, OOOH 


L BRAK 


D_7B 


018H,018H,018H,000H,018H,018H,018H,000H 


1 D_7C 




OEOH, O3OH,O3OH,01CH,O3OH,030H, OEOH, OOOH 


R BRAK 


D_7D 


076H, ODCH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH 


TILDE D_7E 


OOOH, 010H, 038H, 06CH, 0C6H, 0C6H. OFEH, OOOH 


DELTA D_7F 


LABEL BYTE 






078H, OCCH, OCOH, OCCH, 078H, 01 8H, OOCH, 078H 


D_80 




OOOH, OCOH, OOOH, OCCH, OCCH, OCCH, 07EH, OOOH 


D_81 




01 CH, OOOH, 078H, OCCH, OFCH, OCOH, 078H, OOOH 


D_82 




07EH, 0C3H, 03CH, 006H, 03EH, 066H, 03FH, OOOH 


D_83 




OCCH, OOOH, 078H, OOCH, 07CH. OCCH, 07EH, OOOH 


D_84 




OEOH, OOOH, 078H, OOCH, 07CH, OCCH, 07EH, OOOH 


D_85 




030H,030H,078H, OOCH, 07CH, OCCH, 07EH, OOOH 


D_86 




OOOH. OOOH, 078H, OCOH, OCOH, 078H, OOCH, 038H 


D_87 




07EH,OC3H,03CH,066H,07EH,060H,03CH,OOOH 


D_88 




OOOH, OOOH, 078H, OCCH, OFCH, OCOH, 078H, OOOH 


0_89 




OEOH, OOOH, 078H, OCCH, OFCH, OCOH, 078H, OOOH 


D_8A 




OCCH, OOOH, 070H, 030H, 030H, 030H, 078H, OOOH 


D_8B 




07CH,OC6H,038H,018H,018H,018H,03CH,OOOH 


D_8C 




OEOH, OOOH, 070H, 030H, 030H, 030H, 078H, OOOH 


D_8D 




0C6H, 038H, 06CH, 0C6H, OFEH, 0C6H, 0C6H, OOOH 


D_8E 




030H, 030H, OOOH, 078H, OCCH, OFCH, OCCH, OOOH 


D_8F 





01CH, OOOH, 0FCH,060H,078H,060H, OFCH, OOOH ; D_90 
OOOH, OOOH, 07FH, OOCH, 07FH, OCCH, 07FH, OOOH ; D_91 



162 IBM Enhanced Graphics Adapter 



August 2, 1984 





7F 


00 










309 


0490 


3E 
CE 


6C 
00 


CC 


FE 


CC 


CC 


310 
311 


0498 


78 
78 


CC 
00 


00 


78 


CC 


CC 


312 
313 


04A0 


00 
78 


CC 
00 


00 


78 


CC 


CC 


314 
315 


OttAS 


00 
78 


EO 
00 


00 


78 


CC 


CC 


316 
317 


04B0 


78 
7E 


CC 
00 


00 


CC 


CC 


CC 


318 
319 


0tB8 


00 
7E 


EO 
00 


00 


CC 


CC 


CC 


320 
321 


04C0 


00 
OC 


CC 
F8 


00 


CC 


CC 


7C 


322 
323 


cues 


C3 

18 


18 
00 


30 


66 


66 


3C 


324 
325 


OUDO 


CC 
78 


00 
00 


CC 


CC 


CC 


CC 


326 

327 


0UD8 


18 
18 


18 
18 


7E 


CO 


CO 


7E 


328 
329 


OUEO 


38 
FC 


6C 
00 


64 


FO 


60 


E6 


330 
331 


04E8 


CC 
30 


CC 
30 


78 


FC 


30 


FC 


332 
333 


OUFO 


F8 
C6 


CC 
C7 


CC 


FA 


C6 


CF 


334 
335 


04F8 


OE 
D8 


IB 
70 


18 


3C 


18 


18 


336 
337 
338 


0500 


1C 
7E 


00 
00 


78 


OC 


7C 


CC 


339 
340 


0508 


38 
78 


00 
00 


70 


30 


30 


30 


341 
342 


0510 


00 
78 


1C 
00 


00 


78 


CC 


CC 


343 
344 


0518 


00 
7E 


1C 
00 


00 


CC 


CC 


CC 


345 
346 


0520 


00 
CC 


F8 
00 


00 


F8 


CC 


CC 


347 
348 


0528 


FC 
CC 


00 
00 


CC 


EC 


FC 


DC 


349 
350 


0530 


3C 
00 


6C 
00 


6C 


3E 


00 


7E 


351 
352 


0538 


38 
00 


6C 
00 


6C 


38 


00 


7C 


353 
354 


05U0 


30 
78 


00 
00 


30 


60 


CO 


CC 


355 
356 


0548 


00 
00 


00 
00 


00 


FC 


CO 


CO 


357 
358 


0550 


00 
00 


00 
00 


00 


FC 


OC 


OC 


359 
360 


0558 


C3 
CC 


C6 
OF 


CC 


DE 


33 


66 


361 
362 


0560 


C3 
CF 


C6 
03 


CC 


DB 


37 


6F 


363 
364 


0568 


18 
18 


18 
00 


00 


18 


18 


18 


365 
366 


0570 


00 
00 


33 
00 


66 


CC 


66 


33 


367 
368 


0578 


00 
00 


CC 
00 


66 


33 


66 


CC 


369 
370 
371 


0580 


22 
22 


88 
88 


22 


88 


22 


88 


372 
373 


0588 


55 
55 


AA 
AA 


55 


AA 


55 


AA 


374 
375 


0590 


DB 
DB 


77 
EE 


DB 


EE 


DB 


77 


376 
377 


0598 


18 
18 


18 
18 


18 


18 


18 


18 


378 
379 


05A0 


18 
18 


18 
18 


18 


18 


F8 


18 


380 
381 


05A8 


18 
18 


18 
18 


F8 


18 


F8 


18 


382 
383 


05B0 


36 
36 


36 
36 


36 


36 


F6 


36 


384 
385 


05B8 


00 
36 


00 
36 


00 


00 


FE 


36 


386 
387 


05C0 


00 
18 


00 
18 


F8 


18 


F8 


18 


388 
389 


05C8 


36 
36 


36 
36 


F6 


06 


F6 


36 


390 
391 


05D0 


36 
36 


36 
36 


36 


36 


36 


36 


392 
393 


05D8 


00 
36 


00 
36 


FE 


06 


F6 


36 


394 
395 


05E0 


36 
00 


36 
00 


F6 


06 


FE 


00 


396 
397 


05E8 


36 
00 


36 
00 


36 


36 


FE 


00 


398 
399 


05 FO 


18 
00 


18 
00 


F8 


18 


F8 


00 


400 
401 


05F8 


00 
18 


00 
18 


00 


00 


F8 


18 


402 
403 
404 


0600 


18 
00 


18 
00 


18 


18 


IF 


00 


405 
406 


0608 


18 
00 


18 
00 


18 


18 


FF 


00 


407 
408 


0610 


00 
18 


00 
18 


00 


00 


FF 


18 


409 
410 


0618 


18 
18 


18 
18 


18 


18 


IF 


18 


411 
412 


0620 


00 
00 


00 
00 


00 


00 


FF 


00 


413 
414 


0628 


18 
18 


18 
18 


18 


18 


FF 


18 


415 
416 


0630 


18 
18 


18 
18 


IF 


18 


IF 


18 


417 
418 


0638 


36 
36 


36 
36 


36 


36 


37 


36 


419 
420 


0640 


36 
00 


36 
00 


37 


30 


3F 


00 


421 
422 


0648 


00 
36 


00 
36 


3F 


30 


37 


36 


423 
424 


0650 


36 
00 


36 
00 


F7 


00 


FF 


00 


425 
426 


0658 


00 
36 


00 
36 


FF 


00 


F7 


36 


427 
428 


0660 


36 
36 


36 
36 


37 


30 


37 


36 


429 
430 


0668 


00 
00 


00 
00 


FF 


00 


FF 


00 


431 
432 


0670 


36 
36 


36 
36 


F7 


00 


F7 


36 


433 
434 



03EH, 
078H, 
OOOH, 
OOOH, 
078H, 
OOOH, 
OOOH, 
0C3H, 
OCCH, 
018H, 
038H, 
OCCH, 
0F8H, 
OOEH, 

01CH, 
038H, 
OOOH, 
OOOH, 
OOOH, 
OFCH, 
03CH, 
038H, 
030H, 
OOOH, 
OOOH, 
0C3H, 
0C3H, 
018H; 
OOOH, 
OOOH, 

022H, 
055H, 
ODBH, 
018H, 
018H, 
018H, 
036H, 
OOOH, 
OOOH, 
036H, 
036H, 
OOOH, 
036H, 
036H, 
018H, 
OOOH, 



06CH, 
OCCH, 
OCCH, 
OEOH, 
OCCH, 
OEOH, 
OCCH, 
018H, 
OOOH, 
018H, 
06CH, 
OCCH, 
OCCH, 
01BH, 

OOOH, 
OOOH, 
01CH, 
01CH, 
0F8H, 
OOOH, 
06CH, 
06CH, 
OOOH, 
OOOH, 
OOOH, 
0C6H, 
0C6H, 
018H, 
033H, 
OCCH, 

088H, 
OAAH, 
077H, 
018H, 
018H, 
018H, 
036H, 
OOOH, 
OOOH, 
036H, 
036H, 
OOOH, 
036H, 
036H, 
018H, 
OOOH, 



OCCH, 
OOOH, 
OOOH, 
OOOH, 
OOOH, 
OOOH, 
OOOH, 
03CH, 
OCCH, 
07EH, 
064H, 
078H, 
OCCH, 
018H, 

078H, 
070H, 
OOOH, 
OOOH, 
OOOH, 
OCCH, 
06CH, 
06CH, 
030H, 
OOOH, 
OOOH, 
OCCH, 
OCCH, 
OOOH, 
066H, 
066H, 

022H, 
055H, 
ODBH, 
018H, 
018H, 
0F8H, 
036H, 
OOOH, 
0F8H, 
0F6H, 
036H, 
OFEH, 
0F6H, 
036H, 
0F8H, 
OOOH, 



OFEH, OCCH, 
078H,0CCH, 
078H,0CCH, 
078H,0CCH, 
OCCH, OCCH, 
OCCH, OCCH, 
OCCH, OCCH, 
066H,066H, 
OCCH, OCCH, 
OCOH,OC0H, 
OFOH,060H, 
OFCH,030H, 
0FAH,0C6H, 
03CH.018H, 



OOCH, 
030H, 
078H, 
OCCH, 
0F8H, 
OECH, 
03EH, 
038H, 
060H, 
OFCH, 
OFCH, 
ODEH, 
ODBH, 
018H, 
OCCH, 
033H, 



07CH, 
030H, 
OCCH, 
OCCH, 
OCCH, 
OFCH, 
OOOH, 
OOOH, 
OCOH, 
OCOH, 
OOCH, 
033H, 
037H, 
018H 
066H 
066H, 



088H,022H, 
OAAH,055H, 
OEEH.ODBH, 
018H,018H, 
018H,0F8H, 
018H,0F8H, 
036H,0F6H, 
OOOH, OFEH, 
018H,0F8H, 
006H,0F6H, 
036H,036H, 
006H,0F6H, 
006H,0FEH, 
036H,OFEH, 
018H,0F8H, 
O0OH,OF8H, 



OCCH, 
OCCH, 
OCCH, 
OCCH, 
OCCH, 
OCCH, 
07CH, 
03CH, 
OCCH, 
07EH, 
0E6H, 
OFCH, 
OCFH, 
018H, 

OCCH, 
030H, 
OCCH, 
OCCH, 
OCCH, 
ODCH, 
07EH, 
07CH, 
OCCH, 
OCOH, 
OOCH, 
066H, 
06FH, 
018H, 
033H, 
OCCH, 

088H, 
OAAH, 
077H, 
018H, 
018H, 
018H, 
036H, 
036H, 
018H, 
036H, 
036H, 
036H, 
OOOH, 
OOOH, 
OOOH, 
018H, 



018H,018H,018H, 
018H,018H,018H, 
OOOH, OOOH, OOOH, 
018H,018H,018H, 
OOOH, OOOH, OOOH, 
018H,018H,018H, 
018H,018H,01FH, 
036H,036H,036H, 
036H,036H,037H, 
OOOH, OOOH, 03FH, 
036H,036H,0F7H, 
OOOH, OOOH, OFFH, 
036H,036H,037H^ 
OOOH, OOOH, OFFH 
036H,036H,0F7H. 



018H, 
018H, 
OOOH, 
018H, 
OOOH, 
018H, 
018H, 
036H, 
030H, 
030H, 
OOOH, 
OOOH, 
030H, 
OOOH, 
OOOH, 



01 FH, OOOH, 
OFFH, OOOH, 
0FFH,018H, 
01FH,018H, 
OFFH, OOOH, 
0FFH,018H, 
01FH,018H, 
037H,036H, 
O3FH,O0OH 
037H,036H 
OFFH, OOOH, 
0F7H,036H 
037H,036H 
OFFH, OOOH 
0F7H,036H, 



0CEH,000H ; 
078H,000H ; 
078H,000H ; 
078H,000H ; 
07EH,000H ; 
07EH.000H ; 
00CH,0F8H ; 
018H,000H ; 
078H,000H ; 
018H,018H ; 
OFCH, OOOH ; 
030H,030H ; 
0C6H,0C7H ; 
0D8H,070H ; 

07EH,O0OH 
078H,000H 
078H,000H 
07EH,000H 
OCCH, OOOH 
OCCH, OOOH , 
OOOH, OOOH 
OOOH, OOOH , 
078H,000H 
OOOH, OOOH 
OOOH, OOOH 
OCCH,OOFH 
0CFH,003H 
018H,000H 
OOOH, OOOH 
OOOH, OOOH 

022H,088H 
055H,0AAH 
ODBH,OEEH 
018H,018H 
018H,018H 
018H,018H 
036H,036H 
036H,036H 
018H,018H 
036H,036H 
036H,036H 
036H,036H 
OOOH. OOOH 
OOOH, OOOH 
OOOH, OOOH 
018H,018H 

OOOH, OOOH 
OOOH, OOOH 
018H,018H 
018H,018H 
OOOH, OOOH 
,018H,018H 
,018H,018H 
,036H,036H 
, OOOH, OOOH 
,036H,036H 
, OOOH, OOOH 
,036H,036H 
,036H,036H 
, OOOH, OOOH 
,036H,036H 



D_92 
D_93 
D_94 
D_95 
D_96 
D_97 
D_98 
D_99 
D_9A 
D_9B 
D_9C 
D_9D 
D_9E 
D_9F 

D_AO 
D_A1 
D_A2 
D_A3 
D_A4 
D_A5 
D_A6 
D_A7 
D_A8 
D_A9 
D_AA 
D_AB 
D_AC 
D_AD 
D_AE 
D_AF 

D_BO 
D_B1 
D_B2 
D_B3 
D_B4 
D_B5 
D_B6 
D_B7 
D_B8 
D_B9 
D_BA 
D_BB 
D_BC 
D_BD 
D_BE 
D_BF 

D_CO 
D_C1 
D_C2 
D_C3 
D_C4 
D_C5 
D_C6 
D_C7 
D_C8 
D_C9 
D_CA 
D_CB 
D_CC 
D_CD 
0_CE 



August 2, 1984 



IBM Enhanced Graphics Adapter 163 



0678 


18 
00 


18 
00 


FF 


00 




00 


435 
436 
437 


0680 


36 
00 


36 
00 


36 


36 




00 


438 
439 


0688 


00 
18 


00 
18 


FF 


00 




18 


440 
441 


0690 


00 
36 


00 
36 


00 


DO 




36 


442 
443 


0698 


36 
00 


36 
00 


36 


36 




00 


444 
445 


06A0 


18 
00 


18 
00 


IF 


18 




00 


446 
447 


06A8 


00 
18 


00 
18 


IF 


18 




18 


448 
449 


06B0 


00 
36 


00 
36 


00 


00 




36 


450 
451 


06B8 


36 
36 


36 
36 


36 


36 




36 


452 
453 


06C0 


18 
18 


18 
18 


FF 


18 




18 


454 
455 


06C8 


18 
00 


18 
00 


18 


18 




00 


456 
457 


06D0 


00 
18 


00 
18 


00 


00 




18 


458 
459 


06D8 


FF 
FF 


FF 
FF 


FF 


FF 




FF 


460 
461 


06E0 


00 
FF 


00 
FF 


00 


00 




FF 


462 
463 


06E8 


FO 
FO 


FO 
FO 


FO 


FO 


FO 


FO 


464 
465 


06F0 


OF 
OF 


OF 
OF 


OF 


OF 


OF 


OF 


466 
467 


06F8 


FF 
00 


FF 
00 


FF 


FF 


00 


00 


468 
469 
470 


0700 


00 
76 


00 
00 


76 


DC 


C8 


DC 


471 
472 


0708 


00 
CO 


78 
CO 


CC 


F8 


CC 


F8 


473 
474 


0710 


00 
CO 


FC 
00 


CC 


CO 


CO 


CO 


475 
476 


0718 


00 
60 


FE 
00 


6C 


6C 


6C 


6C 


477 
478 


0720 


FC 
FC 


CC 
00 


60 


30 


60 


CC 


479 
480 


0728 


00 
70 


00 
00 


7E 


D8 


D8 


08 


481 
482 


0730 


00 
60 


66 
CO 


66 


66 


66 


7C 


483 
484 


0738 


00 
18 


76 
00 


DC 


18 


18 


18 


485 
486 


0740 


FC 
30 


30 
FC 


78 


CC 


CC 


78 


487 
488 


07U8 


38 
38 


6C 
00 


C6 


FE 


C6 


6C 


489 
490 


0750 


38 
EE 


6C 
00 


C6 


C6 


6C 


6C 


491 
492 


0758 


1C 
78 


30 
00 


18 


7C 


CC 


CC 


493 
494 


0760 


00 
00 


00 
00 


7E 


DB 


DB 


7E 


495 
496 


0768 


06 
60 


OC 
CO 


7E 


DB 


DB 


7E 


497 
498 


0770 


38 
38 


60 
00 


CO 


F8 


CO 


60 


499 
500 


0778 


78 
CC 


CC 
00 


CC 


CC 


CC 


CC 


501 
502 
503 


0780 


00 
00 


FC 
00 


00 


FC 


00 


FC 


504 
505 


0788 


30 
FC 


30 
00 


FC 


30 


30 


00 


506 
507 


0790 


60 
FC 


30 
00 


18 


30 


60 


00 


508 
509 


0798 


18 
FC 


30 
00 


60 


30 


18 


00 


510 
511 


07A0 


OE 
18 


IB 
18 


IB 


18 


18 


18 


512 
513 


07A8 


18 
D8 


18 

70 


18 


18 


18 


D8 


514 
515 


07B0 


30 
30 


30 
00 


00 


FC 


00 


30 


516 
517 


07B8 


00 
00 


76 
00 


DC 


00 


76 


DC 


518 
519 


07C0 


38 
00 


6C 
00 


6C 


38 


00 


00 


520 
521 


07C8 


00 
00 


00 
00 


00 


18 


18 


00 


522 
523 


07D0 


00 
00 


00 
00 


00 


00 


18 


00 


524 
525 


07D8 


OF 
3C 


OC 
1C 


OC 


OC 


EC 


6C 


526 
527 


07E0 


78 
00 


6C 
00 


6C 


6C 


6C 


00 


528 
529 


07E8 


70 
00 


18 
00 


30 


60 


78 


00 


530 
531 


07F0 


00 
00 


00 
00 


3C 


3C 


3C 


3C 


532 
533 


07F8 


00 
00 


00 
00 


00 


00 


00 


00 


534 
535 


0800 














536 
537 



018H,O18H,0FFH,00OH,OFFH,OOOH,OO0H,0O0H 



036H, 
OOOH, 
OOOH, 
036H, 
018H, 
OOOH, 
OOOH, 
036H, 
018H, 
018H, 
OOOH, 
OFFH, 
OOOH, 
OFOH, 
OOFH, 
OFFH, 

OOOH, 
OOOH, 
OOOH, 
OOOH, 
OFCH, 
OOOH, 
OOOH, 
OOOH, 
OFCH, 
038H, 
038H, 
01CH, 
OOOH, 
006H, 
038H, 
078H, 



036H, 
OOOH, 
OOOH, 
036H, 
018H, 
OOOH, 
OOOH, 
036H, 
018H, 
018H, 
OOOH, 
OFFH, 
OOOH, 
OFOH, 
OOFH, 
OFFH, 

OOOH, 
078H, 
OFCH, 
OFEH, 
OCCH, 
OOOH, 
066H, 
076H, 
030H, 
06CH, 
06CH, 
030H, 
OOOH, 
OOCH, 
060H, 
OCCH, 



OOOH, OFCH, 
030H,030H, 
060H,030H, 
018H,030H, 
00EH,01BH, 
018H,018H, 
030H,030H, 
000H,076H, 
038H,06CH, 
OOOH, OOOH, 
OOOH, OOOH, 
OOFH, OOCH, 
078H,06CH, 
070H,018H, 
OOOH, OOOH, 
OOOH, OOOH, 



036H, 
OFFH, 
OOOH, 

,036H, 
01FH, 
01FH, 
OOOH, 

,036H, 
OFFH, 

,018H, 

,000H, 
OFFH, 
OOOH, 
OFOH, 
OOFH, 

,OFFH, 

,076H, 
,OCCH, 
,OCCH, 
,06CH, 
,060H, 
,07EH, 
,066H, 
,ODCH, 
,078H, 
,0C6H, 
,0C6H, 
,018H, 
,07EH, 
,07EH, 
,0C0H, 
,OCCH, 

,000H, 
,0FCH, 
,018H, 
.060H, 
,01BH, 
,018H, 
,000H, 
,ODCH, 
,06CH, 
,000H, 
,000H, 
,OOCH, 
,06CH, 
,030H, 
,03CH, 
,000H, 



036H,OFFH, 
OOOH. OFFH, 
OOOH, OFFH, 
036H,03FH, 
018H,01FH, 
018H,01FH, 
000H.03FH, 
036H,0FFH, 
018H,0FFH, 
018H,0F8H, 
OOOH.OIFH, 
OFFH, OFFH, 
OOOH, OFFH, 
OFOH, OFOH, 
OOFH, OOFH, 
OFFH, OOOH, 



OOOH, 
018H, 
036H, 
OOOH, 
OOOH, 
018H, 
036H, 
036H, 
018H, 
OOOH, 
018H, 
OFFH, 
OFFH, 
OFOH, 
OOFH, 
OOOH, 



OOOH, OOOH 
018H,018H 
036H,036H 
OOOH, OOOH 
OOOH, OOOH 
018H,018H 
036H.036H 
036H,036H 
018H,018H 
OOOH, OOOH 
018H,018H 
OFFH, OFFH 
OFFH, OFFH 
OFOH, OFOH 
OOFH, OOFH 
OOOH, OOOH 



ODCH, 
0F8H, 
OCOH, 
06CH, 
030H, 
0D8H, 
066H, 
018H, 
OCCH, 
OFEH, 
0C6H, 
07CH, 
ODBH, 
ODBH, 
0F8H, 
OCCH, 

OFCH, 
030H, 
030H, 
030H, 
018H, 
018H, 
OFCH, 
OOOH, 
038H, 
018H, 
OOOH, 
OOCH, 
06CH, 
060H, 
03CH, 
OOOH, 



0C8H, 
OCCH, 
OCOH, 
06CH, 
060H, 
0D8H, 
066H, 
018H, 
OCCH, 
0C6H, 
06CH, 
OCCH, 
ODBH, 
ODBH, 
OCOH, 
OCCH, 



0DCH,076H, 
0F8H,0C0H, 
OCOH, OCOH, 
06CH,06CH, 
OCCH, OFCH, 
0D8H,070H, 
07CH,060H, 
018H,018H, 
O78H,O30H, 
06CH,038H, 
06CH,0EEH, 
0CCH,078H, 
07EH,OOOH, 
07EH,060H. 
060H,038H, 
OCCH, OCCH, 



OOOH, OFCH, OOOH, 
030H, OOOH, OFCH, 
060H, OOOH, OFCH, 
018H, OOOH, OFCH, 
018H,018H,018H, 
018H,0D8H,0D8H, 
000H,030H,030H, 
076H, ODCH, OOOH, 
OOOH, OOOH, OOOH, 
018H, OOOH, OOOH, 
018H, OOOH, OOOH, 
0ECH,06CH,03CH, 
06CH, OOOH, OOOH, 
078H, OOOH, OOOH, 
03CH,03CH,OOOH, 
OOOH, OOOH, OOOH, 



OOOH 
OCOH 
OOOH 
OOOH 
OOOH 
OOOH 
OCOH 
OOOH 
OFCH 
OOOH 
OOOH 
OOOH 
OOOH 
OCOH 
OOOH 
OOOH 

OOOH 
OOOH 
OOOH 
OOOH 
018H 
070H 
OOOH 
OOOH 
OOOH 
OOOH 
OOOH 
01CH 
OOOH 
OOOH 
OOOH 
OOOH 



D_CF 

D_DO 
D_D1 
D_D2 
D_D3 
D_D4 
D_D5 
D_D6 
D_D7 
D_D8 
D_D9 
D_DA 
D_DB 
D_DC 
D_DD 
D_DE 
D_DF 

D_EO 
D_E1 
D_E2 
D_E3 
D_E4 
D_E5 
D_E6 
D_E7 
D_E8 
D_E9 
D_EA 
D_EB 
D_EC 
D_ED 
D_EE 
D_EF 

D_FO 
D_F1 
D_F2 
D_F3 
D_F4 
D_F5 
D_F6 
D_F7 
D_F8 
D_F9 
D_FA 
D_FB 
D_FC 
D_FD 
D_FE 
D_FF 



PAGE, 120 

SUBTTL END ADDRESS 
CODE SEGMENT PUBLIC 
PUBLIC END_ADDRESS 
END_ADDRESS LABEL BYTE 
CODE ENDS 

END 



164 IBM Enhanced Graphics Adapter 



August 2, 1984 



Index 



Attribute Address Register 56 
Attribute Controller 

description 3 

registers 56 



B 



BIOS 

description 4 

vectors with special 
meanings 103 
BIOS listing 103 
Bit Mask Register 54 



compatibility issues 74 
configuration switches 80 
CRT Controller 
description 3 
registers 24 
CRT Controller Address 

Register 24 
CRT Controller Overflow 

Register 30 

Cursor End Register 33 
Cursor Location High 

Register 35 
Cursor Location Low 

Register 35 
Cursor Start Register 32 



D 



Data Rotate Register 49 
direct drive connector 83 
display buff er 4 



character generator 

ROM 1 
Character Map Select 

Register 21 

Clocking Mode Register 19 
Color Compare Register 48 
Color Don't Care Register 53 
color mapping 10 
Color Plane Enable 

Register 60 



E 



Enable Set/Reset Register 47 
End Horizontal Blanking 

Register 27 
End Horizontal Retrace 

Register 29 



Index- 1 



End Vertical Blanking 
Register 40 



feature connector 76 
Feature Control Register 14 



Input Status Register One 15 
Input Status Register Zero 14 
Interface 76 

feature connector 76 



Graphics Controller 
description 3 
registers 45 
Graphics 1 and 2 Address 
Register 46 
Graphics 1 Position 
Register 45 
Graphics 2 Position 
Register 46 



H 



Horizontal Display Enable End 

Register 26 
Horizontal Pel Panning 

Register 60 
Horizontal Total Register 25 



Light Pen High Register 36 
light pen interface 84 
Light Pen Low Register 37 
Line Compare Register 43 



M 



Map Mask Register 20 
Maximum Scan Line 
Register 32 
Memory Mode Register 23 
Miscellaneous Output 

Register 12 
Miscellaneous Register 52 
Mode Control Register 41, 58 
Mode Register 50 
modes 

alphanumeric 8 
graphics 8 

IBM Color Display 5 
IBM Enhanced Color 
Display 6 
IBM Monochrome 
Display 6 



Index-2 



o 



Off set Register 38 
Overscan Color Register 59 



Graphics Controller 45 
Sequencer 18 
Reset Register 18 



Palette Registers 57 
Preset Row Scan Register 3 1 
programming 
considerations 62 
compatibility issues 74 
creating a split screen 73 
creating a 512 character 
set 70 

creating an 80 by 43 
alphanumeric mode 71 
programming registers 62 
RAM loadable character 
generator 69 
vertical interrupt feature 72 



R 



Sequencer 

description 3 
registers 18 

Sequencer Address Register 18 

Set/Reset Register 47 

specifications 79 

configuration switch 
settings 81 
configuration switches 80 
direct drive connector 83 
light pen interface 84 
system board switches 79 

Start Address High Register 34 

Start Address Low Register 34 

Start Horizontal Blanking 
Register 26 

Start Horizontal Retrace Pulse 
Register 28 

Start Vertical Blanking 
Register 39 

support logic 4 



RAM loadable character 
generator 69 

Read Map Select Register 50 

registers 

Attribute Controller 56 
CRT Controller 24 
external 12 



u 



Underline Location 
Register 39 



Index-3 



\^ Vertical Retrace End 

Register 36 
Vertical Retrace Start 
Vertical Display Enable End Register 36 

Register 38 Vertical Total Register 30 

vertical interrupt feature 72 



Index-4 



Personal Computer 
Hardware Reference 
Library 



IBM Printer Adapter 



6361507 



Contents 



Description 1 

Programming Considerations 3 

Specifications 7 

Logic Diagrams 9 



m 



IV 



Description 



The IBM Printer Adapter is specifically designed to attach 
printers with a parallel port-interface, but it can be used as a 
general input/output port for any device or application that 
matches its input/output capabilities. It has 12 TTL-buffer 
output points, which are latched and can be written and read 
under program control using the microprocessor In or Out 
instruction. The adapter also has five steady-state input points 
that may be read using the microprocessor's In instructions. 

In addition, one input can also be used to create a microprocessor 
interrupt. This interrupt can be enabled and disabled under 
program control. A reset from the power-on circuit is also ORed 
with a program output point, allowing a device to receive a 
'power-on reset' when the system unit's microprocessor is reset. 

The input/output signals are made available at the back of the 
adapter through a right-angle, printed-circuit-board-mounted, 
25 -pin, D-shell connector. This connector protrudes through the 
rear panel of the system unit or expansion unit, where a cable may 
be attached. 

When this adapter is used to attach a printer, data or printer 
commands are loaded into an 8 -bit, latched, output port, and the 
strobe line is activated, writing data to the printer. The program 
then may read the input ports for printer status indicating when 
the next character can be written, or it may use the interrupt line 
to indicate ''not busy" to the software. 

The output ports may also be read at the card's interface for 
diagnostic loop functions. This allows faults to be isolated to the 
adapter or the attaching device. 

This same function is also part of the IBM Monochrome Display 
and Printer Adapter. 



Printer Adapter 1 



The following is a block diagram of the Printer Adapter. 



Trans- 
ceiver 

DIR 



*V- 



AEN. 



Command 
Decoder 



DIR 



Read 
Data 



Bus Buffer 
Enable 



Data Latch 



8 



f-> 



Write Data 



Write Control 



Read Status 



Read 
Control 



Bus 
Buffers 



Enable 



P Enable 



Clock 



25-Pin D-Shell 
Connector 



O.C. 
Drivers 



Control 
Latch 



Reset 



Clock 



^ Clear 



Printer Adapter Block Diagram 



SLOT IN 



STROBE 
AUTO 
FDXT 
INIT 



ERROR 

SLOT 

PE 

ACK 

BUSY 



2 Printer Adapter 



Programming Considerations 



The Printer Adapter responds to five I/O instructions; two output 
and three input. The output instructions transfer data into two 
latches whose outputs are presented on pins of a 25 -pin D-shell 
connector. 

Two of the three input instructions allow the system unit's 
microprocessor to read back the contents of the two latches. The 
third allows the system unit's microprocessor to read the real-time 
status from a group of pins on the connector. 

A description of each instruction follows. 



Printer Adapter 



Output to address hex 378 



Bit 3 
Pin 5 



Bit 2 
Pin 4 



Bit 1 
Pin 3 



BitO 
Pin 2 



The instruction captures data from the data bus and is present on 
the respective pins. Each of these pins is capable of sourcing 2.6 
mA and sinking 24 mA. 

It is essential that the external device does not try to pull these 
Unes to ground. 



Printer Adapter 



Output to address hex 37A 



Bit 3 
Pin 17 



Bit 2 
Pin 16 



Bit 1 
Pin 14 



BitO 
Pin 1 



This instruction causes the latch to capture the five least 
significant bits of the data bus. The four least significant bits 
present their outputs, or inverted versions of their outputs, to the 



Printer Adapter 3 



respective pins as shown in the previous figure. If bit 4 is written 
as a 1 , the card will interrupt the system unit's microprocessor on 
the condition that pin 10 changes from high to low. 

These pins are driven by open-collector drivers pulled to +5 Vdc 
through 4.7 kfi resistors. They can each sink approximately 7 mA 
and maintain 0.8 volts down-level. 



Printer Adapter 



Input from address hex 378 



This instruction presents the system unit's microprocessor with 
data present on the pins associated with the output to hex SBC. 
This should normally reflect the exact value that was last written 
to hex SBC. If an external device should be driving data on these 
pins at the time of an input (in violation of usage ground rules), 
this data will be ORed with the latch contents. 



Printer Adapter 



Input from address hex 379 



This instruction presents the real-time status to the system unit's 
microprocessor from the pins, as follows. 



Bit 7 


Bite 


Bit 5 


Bit 4 


Bit 3 


Bit 2 


Bit 1 


BitO 


Pin 11 


Pin 10 


Pin 12 


Pin 13 


Pin 15 


- 


- 


- 



Printer Adapter 



Input from address hex 37A 



4 Printer Adapter 



This instruction causes the data present on pins 1, 14, 16, 17, and 
the IRQ bit to be read by the system unit's microprocessor. In 
the absence of external drive appUed to these pins, data read by 
the system unit's microprocessor will match data last written to 
hex 3 BE in the same bit positions. Notice that data bits 0-2 are 
not included. If external drivers are dotted to these pins, that 
data will be ORed with data appUed to the pins by the hex 3BE 
latch. 



Bit 7 


Bite 


Bit 5 


Bit 4 

IRQ 
Enable 

Por = 


Bits 


Bit 2 
Pin 16 

Por = 


Bit 1 


BitO 


Pin 17 
Por=1 


Pin 14 
Por=1 


Pin 1 
Por=1 



These pins assume the states shown after a reset from the system 
unit's microprocessor. 



Printer Adapter 5 



6 Printer Adapter 



Specifications 



25-Pin D-Shell 
Connector 






At Standard TTL Levels 
Signal 
Name 


Adapter 
Pin Number 
1 








- Strobe 








+ Data Bit 


2 








+ Data Bit 1 


3 








+ Data Bit 2 


4 








+ Data Bit 3 


5 








+ Data Bit 4 


6 








+ Data Bit 5 


7 








+ Data Bit 6 


8 






Printer 


+ Data Bit 7 


9 




Printer 




- Acknowledge 


10 




Adapter 




+ Busy 


11 








+ P.End (out of paper) 


12 








+ Select 


13 








- Auto Feed 


14 








- Error 


15 








- initialize Printer 


16 








- Select Input 


17 








Ground 


18-25 

















Connector Specifications 



Printer Adapter 7 



8 Printer Adapter 



Logic Diagrams 



The following page contains the logic diagram for the IBM Printer 
Adapter. 



Printer Adapter 9 



CARD EDGE TABS 




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Printer Adapter (Sheet 1 of 1) 



Personal Computer 
Hardware Reference 
Library 



roM 5-1/4 ' Diskette 
Drive Adapter 



6361505 



Contents 



Description 1 

Programming Considerations 3 

Digital-Output Register 3 

Floppy Disk Controller 4 

Command Summary 8 

Programming Summary 17 

Interface 19 

System I/O Channel Interface 19 

Drive A and B Interface 20 

Specifications 23 

Logic Diagrams 25 



lU 



IV 



Description 



The IBM 5-1/4" Diskette Drive Adapter fits into one of the 
expansion slots in the system unit. It is connected to one or two 
diskette drives through an internal, daisy-chained flat cable. The 
adapter has a connector at the other end that extends through the 
rear panel of the system unit. This connector has signals for two 
additional external diskette drives; thus, the 5-1/4 inch diskette 
drive adapter can attach four 5-1/4 inch drives — two internal 
and two external. 

The adapter is designed for double-density, MFM-coded, diskette 
drives and uses write precompensation with an analog phase-lock 
loop for clock and data recovery. The adapter is a 
general-purpose device using the NEC /xPD765 or equivalent 
controller. Therefore, the diskette drive parameters are 
programmable. In addition, the attachment supports the diskette 
drive's write-protect feature. The adapter is buffered on the I/O 
bus and uses the system board's direct memory access (DMA) for 
record data transfers. An interrupt level also is used to indicate 
when an operation is complete and that a status condition requires 
microprocessor attention. 

In general, the 5-1/4 inch diskette drive adapter presents a 
high-level command interface to software I/O drivers. 



Diskette Adapter 1 



K) 



> 

a. 



Clock 
and 
Timing 
Circuit 



NEC 

LK >, K Floppy 

^ Buffer |(^ ^ Disk 

Controller 



O 



Write 
Data 



Write 

Precompensate 

Circuit 



VCO SYNC, 



,STD. DATA 



.Data Window 



■< 



Reset 



Digital 

Control 

Port 



INTR. 



<: 



Write Data 




-[>- 



>- 



<t- 



>T^.r^ 



Step 



O- 



Direction 



Write Enable 



o- 



Head Select 



index 



-0 



Write Protect 



Track 



Decoder 



B 
C 
D 



^ 



Drive A Motor On 



B 
C 
D 



-t> 



Drive A Select 



G^ 


>^ 


pr 


<: 


CD 


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H-^ 


> 


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CL 


O 


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T5 


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ts 




CTQ 








(/3 




P 




cr 








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fTQ 




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CD 



5-1/4 Inch Diskette Drive Adapter Block Diagram 



Programming Considerations 



This attachment consists of an 8 -bit digital output register in 
parallel with a NEC /xPD765 or equivalent floppy disk controller 
(FDC). 

In the following description, drive numbers 0, 1,2, and 3 are 
equivalent to drives A, B, C, and D. 



Digital-Output Register 

The Digital-Output register (DOR) is an output-only register used 
to control drive motors, drive selection, and feature enable. All 
bits are cleared by the I/O interface 'reset' line. The bits have the 
following functions: 

Bits and 1 These bits are decoded by the hardware to 

select one drive if its motor is on: 



Bit 10 


Drive 


00 


0(A) 


01 


KB) 


10 


2(C) 


1 1 


3(D) 



Bit 2 The FDC is held reset when this bit is clear. 

It must be set by the program to enable the 
FDC. 

Bit 3 This bit allows the FDC interrupt and DMA 

requests to be gated onto the I/O interface. 
If this bit is cleared, the interrupt and DMA 
request I/O interface drivers are disabled. 

Bits 4, 5, 6, These bits control, respectively, the motors of 

and 7 drives 0, 1, 2 (A, B, C), and 3 (D). If a bit is 

clear, the associated motor is off, and the 

drive cannot be selected. 



Diskette Adapter 3 



Floppy Disk Controller 

The floppy disk controller (FDC) contains two registers that may 
be accessed by the system unit's microprocessor: a status register 
and a data register. The 8 -bit main status register contains the 
status information of the FDC and may be accessed at any time. 
The 8-bit data register (actually consisting of several registers in a 
stack with only one register presented to the data bus at a time) 
stores data, commands, parameters, and provides floppy disk 
drive (FDD) status information. Data bytes are read from or 
written to the data register in order to program or obtain results 
after a particular command. The main status register can only be 
read and is used to facilitate the transfer of data between the 
system unit's microprocessor and FDC. 

The bits in the main status register (hex 34F) are defined as 
follows: 



Bit 








Number 


Name 


Symbol 


Description 


DBO 


FDD A Busy 


DAB 


FDD number is in the Seek mode. 


DB1 


FDD B Busy 


DBB 


FDD number 1 is in the Seek mode. 


DB2 


FDD C Busy 


DCB 


FDD number 2 is in the Seek mode. 


DB3 


FDD D Busy 


DDB 


FDD number 3 is in the Seek mode. 


DB4 


FDC Busy 


CB 


A read or write command is in process. 


DB5 


Non-DMA 
Mode 


NDM 


The FDC is in the non-DMA mode. 


DB6 


Data Input/ 


DIG 


Indicates direction of data transfer 




Output 




between FDC and processor. If DIO = " 1 ," 
then transfer is from FDC data register to 
the processor. If DIO = "0," then transfer 
is from the processor to FDC data register. 


DB7 


Request for 


ROM 


Indicates data register is ready to send or 




Master 




receive data to or from the processor. Both 
bits DIO and ROM should be used to 
perform the handshaking functions of 
"ready" and "direction" to the processor. 



The FDC is capable of performing 15 different commands. Each 
command is initiated by a multi-byte transfer from the system 
unit's microprocessor, and the result after execution of the 
command may also be a multi-byte transfer back to the system 



4 Diskette Adapter 



unit's microprocessor. Because of this multi-byte interchange of 
information between the FDC and the system unit's 
microprocessor, it is convenient to consider each command as 
consisting of three phases: 



Command Phase 

The FDC receives all information required to perform a particular 
operation from the system unit's microprocessor. 



Execution Phase 

The FDC performs the operation it was instructed to do. 

Result Phase 

After completion of the operation, status and other housekeeping 
information are made available to the system unit's 
microprocessor. 

The following tables define the symbols used in the command 
summary. The command summary immediately follows these 
tables. 



Diskette Adapter 5 



Symbol 


Name 


Description 


AO 


Address Line 


AO controls selection of main status 
register (A0 = 0) or data register (A0= 1). 


C 


Cylinder Number 


C stands for the current/selected cylinder 
(track) number of the medium. 


D 


Data 


D stands for the data pattern that is going 
to be written into a sector. 


D7-D0 


Data Bus 


8-bit data bus, where D7 stands for a 
most significant bit, and DO stands for a 
least significant bit. 


DTL 


Data Length 


When N is defined as 00, DTL stands for 
the data length that users are going to 
read from or write to the sector. 


EOT 


End of Track 


EOT stands for the final sector number on 
a cylinder. 


GPL 


Gap Length 


GPL stands for the length of gap 3 
(spacing between sectors excluding VCO 
sync field). 


H 


Head Address 


H stands for head number or 1 , as 
specified in ID field. 


HD 


Head 


HD stands for a selected head number 
or 1 . (H = HD in all command words). 


HLT 


Head Load Time 


HLT stands for the head load time in the 
FDD (4 to 512 ms in 4-ms increments). 


HUT 


Head Unload Time 


HUT stands for the head unload time after 
a read or write operation has occurred (0 
to 480 ms in 32-ms increments). 


MF 


FMorMFMMode 


If MF is low, FM mode is selected; if it is 
high, MFM mode is selected only if MFM 
is implemented. 


MT 


Multi-Track 


If MT is high, a multi-track operation is to 
be performed. (A cylinder under both HDO 
and HD1 will be read or written.) 


N 


Number 


N stands for the number of data bytes 
written in a sector. 



Symbol Descriptions (Part 1 of 2) 



6 Diskette Adapter 



Symbol 


Name 


Description 


NCN 


New Cylinder 
Number 


NCN stands for a new cylinder number, 
which is going to be reached as a result 
of the seek operation. (Desired position of 
the head.) 


ND 


Non-DMA Mode 


ND stands for operation in the non-DMA 
mode. 


PCN 


Present Cylinder 
Number 


PCN stands for cylinder number at the 
completion of sense-interrupt-status 
command indicating the position of the 
head at present time. 


R 


Record 


R stands for the sector number, which 
will be read or written. 


R/W 


Read/Write 


R/W stands for either read (R) or write 
(W) signal. 


SC 


Sector 


SC indicates the number of sectors per 
cylinder. 


SK 


Skip 


SK stands for skip deleted-data address 
mark. 


SRT 


Step Rate Time 


SRT stands for the stepping rate for the 
FDD (2 to 32 ms in 2-ms increments). 


STO 
ST1 
ST 2 
ST 3 


Status 
Status 1 
Status 2 
Status 3 


STO-3 stand for one of four registers that 
store the status information after a 
command has been executed. This 
information is available during the result 
phase after command execution. These 
registers should not be confused with the 
main status register (selected by AO = 0) . 
ST 0-3 may be read only after a command 
has been executed and contain 
information relevant to that particular 
command. 


STP 


Scan Test 


During a scan operation, if STP = 1 , the 
data in contiguous sectors is compared 
byte-by-byte with data sent from the 
processor (or DMA), and if STP= 2, then 
alternate sectors are read and compared. 


USO, 
US1 


Unit Select 


US stands for a selected drive number 
encoded the same as bits and 1 of the 
digital output register (DOR). 



Symbol Descriptions (Part 2 of 2) 



Diskette Adapter 7 



Command Summary 

In the following table, indicates ''logical 0" for that bit, 1 means 
''logical 1," and X means "don't care." 







Data Bus 




Phase 


R/W 


D7 D6 D5 D4 D3 D2 D1 DO 


Remarks 






Read Data 




Command 


W 


MT MP SK 1 10 


Command Codes 




w 


X X X X X HDUS1US0 






w 


c 


Sector ID information 




w 


H 


prior to command 




w 


R 


execution. 




w 


N 






w 


EOT 






w 


GPL 






w 


DTL 




Execution 






Data transfer 
between the FDD 
and main system. 


Result 


R 


STO 


Status information 




R 


ST 1 


after command 




R 


ST 2 


execution. 




R 


C 


Sector ID information 




R 


H 


after command 




R 


R 


execution. 




R 


N 








Read Deleted Data 




Command 


W 


MT MF SK 1 10 


Command Codes 




W 


X X X X X HDUS1US0 






W 


C 


Sector ID information 




W 


H 


prior to command 




W 


R 


execution. 




W 


N 






W 


EOT 






W 


GPL 






W 


DTL 




Execution 






Data transfer 
between the FDD 
and main system. 


Result 


R 


STO 


Status information 




R 


ST 1 


after command 




R 


ST 2 


execution. 




R 


c 


Sector ID information 




R 


H 


after command 




R 


R 


execution. 




R 


N 





8 Diskette Adapter 











Data Bus 




Phase 


R/W 


D7 


D6 


D5 D4 D3 D2 D1 DO 


Remarks 










Write Data 




Command 


W 


MT 


MF 


10 1 


Command Codes 




w 


X 


X 


XXX HDUS1US0 






w 






C 


Sector ID information 




w 






H 


prior to command 




w 






R 


execution. 




w 






N 






w 






EOT 






w 






GPL 






w 






DTL 




Execution 










Data transfer 
between the main 
system and FDD. 


Result 


R 






STO 


Status information 




R 






ST1 


after command 




R 






ST 2 


execution. 




R 






C 


Sector ID information 




R 






H 


after command 




R 






R 


execution. 




R 






N 












Write Deleted Data 




Command 


W 


iVlT 


MF 


10 1 


Command Codes 




W 


X 


X 


XXX HDUS1US0 






W 






C 


Sector ID information 




W 






H 


prior to command 




W 






R 


execution. 




W 






N 






W 






EOT 






W 






GPL 






W 






DTL 




Execution 










Data transfer 
between the FDD and 
main system. 


Result 


R 






STO 


Status ID information 




R 






ST 1 


after command 




R 






ST 2 


execution. 




R 






C 


Sector ID information 




R 






H 


after command 




R 






R 


execution. 




R 






N 





Diskette Adapter 9 











Data Bus 






Phase 


R/W 


D7 D6 


D5 


D4 D3 


D2 D1 DO 


Remarks 








Read a Track 




Command 


W 


MF 


SK 





1 


Command Codes 




w 


X X 


X 


X X 


HD US1US0 






w 






c 




Sector ID information 




w 






H 




prior to command 




w 






R 




execution. 




w 






N 








w 






EOT 








w 






GPL 








w 






DTL 






Execution 












Data transfer 
between the FDD 
and main system. 
FDC reads all of 
cylinder's contents 
from index hole to 
EOT. 


Result 


R 
R 
R 
R 
R 
R 
R 






STO 
ST1 
ST 2 

C 

H 

R 

N 




Status information 

after command 

execution. 

Sector ID information 

after command 

execution. 










Read ID 






Command 


W 


MF 





1 


1 


Command Codes 




W 


X X 


X 


X X 


HD US1US0 




Execution 












The first correct ID 
information on the 
cylinder is stored in 
data register. 


Result 


R 
R 
R 
R 
R 
R 
R 






STO 
ST1 
ST 2 

C 

H 

R 

N 




Status information 

after command 

execution. 

Sector ID information 

during execution 

phase. 



10 Diskette Adapter 







Data Bus 




Phase 


R/W 


D7 D6 D5 D4 D3 D2 D1 DO 


Remarks 






Format a Track 




Command 


W 


MP 1 1 


Command Codes 




w 


X X X X X HDUS1US0 






w 


N 


Bytes/Sector 




w 


SC 


Sector/Track 




w 


GPL 


Gap 3 




w 


D 


filler byte. 


Execution 






FDC formats an 
entire cylinder. 


Result 


R 


STO 


Status information 




R 


ST1 


after command 




R 


ST 2 


execution. 




R 


C 


In this case, the ID 




R 


H 


information has no 




R 


R 


meaning. 




R 


N 








Scan Equal 




Command 


W 


MT MF SK 1 1 


Command Codes 




W 


X X X X X HDUS1US0 






W 


C 


Sector ID information 




W 


H 


prior to command 




W 


R 


execution. 




W 


N 






W 


EOT 






W 


GPL 






W 


STP 




Execution 






Data compared 
between the FDD 
and the main system. 


Result 


R 


STO 


Status information 




R 


ST1 


after Command 




R 


ST 2 


execution. 




R 


C 


Sector ID information 




R 


H 


after command 




R 


R 


execution. 




R 


N 





Diskette Adapter 1 1 







Data Bus 




Phase 


R/W 


D7 D6 D5 D4 D3 D2 D1 DO 


Remarks 






Scan Low or Equal 




Command 


W 


MT MF SK 1 1 1 


Command Codes 




w 


X X X X X HDUS1US0 






w 


C 


Sector ID information 




w 


H 


prior to command 




w 


R 


execution. 




w 


N 






w 


EOT 






w 


GPL 






w 


STP 




Execution 






Data compared 
between the FDD 
and main system. 


Result 


R 


STO 


Status information 




R 


ST1 


after command 




R 


ST 2 


execution. 




R 


C 


Sector ID information 




R 


H 


after command 




R 


R 


execution. 




R 


N 








Scan High or Equal 




Command 


W 


MT MF SK 1 1 1 1 


Command Codes 




W 


X X X X X HDUS1US0 






W 


C 


Sector ID information 




W 


H 


prior to command 




W 


R 


execution. 




W 


N 






W 


EOT 






W 


GPL 






W 


STP 




Execution 






Data compared 
between the FDD 
and main system. 


Result 


R 


STO 


Status information 




R 


ST1 


after command 




R 


ST 2 


execution. 




R 


c 


Sector ID information 




R 


H 


after command 




R 


R 


execution. 




R 


N 





12 Diskette Adapter 









Data Bus 




Phase 


R/W 


D7 


D6 D5 D4 D3 D2 D1 DO 


Remarks 








Recalibrate 




Command 


W 





1 1 1 


Command Codes 




w 


X 


X X X X US1US0 




Execution 








Head retracted to 


No Result 








track 


Phase 
















Sense Interrupt Status 




Command 


w 





10 


Command Codes 


Result 


R 




STO 


Status information at 




R 




PCN 


the end of seek 
operation about the 
FDC 








Specify 




Command 


W 
W 
W 





1 1 
SRT HUT 

HLT ND 


Command Codes 


No Result 








Phase 
















Sense Drive Status 




Command 


W 





10 


Command Codes 




W 


X 


X X X X HDUS1US0 




Result 


R 




ST 3 


Status information 
about FDD. 








Seek 




Command 


W 





1111 


Command Codes 




W 


X 


X X X X HDUS1US0 






W 




NCN 




Execution 








Head is positioned 
over proper cylinder 
on diskette. 


No Result 










Phase 
















Invalid 




Command 


W 




Invalid Codes 


Invalid command 
codes (NoOp - FDC 
goes into standby 
state). 


Result 


R 




STO 


ST 0^:80. 



Diskette Adapter 13 



Bit 


Description 


No. 


Name 


Symbol 


D7 
D6 


Interrupt 
Code 


IC 


D7 = OandD6 = 

Normal termination of command (NT). 

Command was completed and properly 

executed. 

D7 = OandD6 = 1 

Abnormal termination of command (AT). 

Execution of command was started, but 

was not successfully completed. 

D7 = 1 andD6 = 

Invalid command issue (IC). Command 

that was issued was never started. 

D7 = 1 andD6 = 1 

Abnormal termination because, during 

command execution, the ready signal 

from FDD changed state. 


D5 


Seek End 


SE 


When the FDC completes the seek 
command, this flag is set to 1 (high). 


D4 


Equipment 
Check 


EC 


If a fault signal is received from the 
FDD, or if the track signal fails to occur 
after 77 step pulses (recalibrate 
command), then this flag is set. 


D3 


Not Ready 


NR 


When the FDD is in the not-ready state 
and a read or write command is issued, 
this flag is set. If a read or write command 
is issued to side 1 of a single-sided drive, 
then this flag is set. 


D2 


Head Address 


HD 


This flag is used to indicate the state of 
the head at interrupt. 


D1 
DO 


Unit Select 1 
Unit Select 


US 1 
USO 


These flags are used to indicate a drive 
unit number at interrupt. 



Command Status Register 



14 Diskette Adapter 



Bit 


Description 


No. 


Name 


Symbol 


D7 


End of 
Cylinder 


EN 


When the FDC tries to access a sector 
beyond the final sector of a cylinder, this 
flag is set. 


D6 


- 


- 


Not used. This bit is always (low). 


D5 


Data Error 


DE 


When the FDC detects a CRC error in 
either the ID field or the data field, this 
flag is set. 


D4 


Over Run 


OR 


If the FDC is not serviced by the main 
system during data transfers within a 
certain time interval, this flag is set. 


D3 


- 


- 


Not used. This bit is always (low). 


D2 


No Data 


ND 


During execution of a read data, write 
deleted data, or scan command, if the 
FDC cannot find the sector specified in 
the ID register, this flag is set. During 
execution of the read ID command, if the 
FDC cannot read the ID field without an 
error, then this flag is set. During the 
execution of the read a cylinder 
command, if the starting sector cannot be 
found, then this flag is set. 


D1 


Not Writable 


NW 


During execution of a write data, write 
deleted data, or format-a-cylinder 
command, if the FDC detects a 
write-protect signal from the FDD, then 
this flag is set. 


DO 


Missing 
Address 
Mark 


MA 


If the FDC cannot detect the ID address 
mark, this flag is set. Also, at the same 
time, the MD (missing address mark in 
the data field) of status register 2 is set. 



Command Status Register 1 



Diskette Adapter 15 



Bit 


Description 


No. 


Name 


Symbol 


D7 


- 


- 


Not used. This bit is always (low). 


D6 


Control Mark 


CM 


During execution of the read data or scan 
command, if the FDC encounters a sector 
that contains a deleted data address 
mark, this flag is set. 


D5 


Data Error in 
Data Field 


DD 


If the FDC detects a CRC error in the data, 
then this flag is set. 


D4 


Wrong 
Cylinder 


WC 


This bit is related to the ND bit, and when 
the contents of C on the medium are 
different from that stored in the ID 
register, this flag is set. 


D3 


Scan Equal 
Hit 


SH 


During execution of the scan command, if 
the condition of "equal" is satisfied, this 
flag is set. 


D2 


Scan Not 
Satisfied 


SN 


During execution of the scan command, 
if the FDC cannot find a sector on the 
cylinder that meets the condition, then 
this flag is set. 


D1 


Bad Cylinder 


BC 


This bit is related to the ND bit, and when 
the contents of C on the medium are 
different from that stored in the ID 
register, and the contents of C is FF, then 
this flag is set. 


DO 


Missing 
Address Mark 
in Data Field 


MD 


When data is read from the medium, if 
the FDC cannot find a data address mark 
or deleted data address mark, then this 
flag is set. 



Command Status Register 2 



16 Diskette Adapter 



Bit 


Description 


No. 


Name 


Symbol 


D7 


Fault 


FT 


This bit is the status of the fault signal 
from the FDD. 


D6 


Write 
Protected 


WP 


This bit is the status of the 
write-protected signal from the FDD. 


D5 


Ready 


RY 


This bit is the status of the ready signal 
from the FDD. 


D4 


Track 


TO 


This bit is the status of the track signal 
from the FDD. 


D3 


Two Side 


TS 


This bit is the status of the two-side 
signal from the FDD. 


D2 


Head Address 


HD 


This bit is the status of the side-select 
signal from the FDD. 


D1 


Unit Select 1 


US 1 


This bit is the status of the unit-select-1 
signal from the FDD. 


DO 


Unit Select 


USO 


This bit is the status of the unit-select-0 
signal from the FDD. 



Command Status Register 3 



Programming Summary 



FDC Data Register 


I/O Address Hex 3F5 


FDCMain 


Status Register 


I/O Address Hex 3F4 


Digital Output Register 


I/O Address Hex 3F2 


BitO 


Drive 


00: DR #A 10: DR #C 


1 


Select 


01: DR #B 11: DR #D 


2 


Not FDC Reset 


3 


Enable INT & DMA Requests 


4 


Drive A Motor Enable 


5 


Drive B Motor 


Enable 


6 


Drive C Motor Enable 


7 


Drive D Motor 


Enable 


All bits cleared with channel reset. 



DPC Registers 



Diskette Adapter 17 



FDC Constants (in hex) 



N: 02 GPL Format: 05 

SC: 08 GPLR/W: 2 A 

HUT: F HLT: 01 

SRT: C (6 ms track-to-track) 

Drive Constants 

Head Load 35 ms 

Head Settle 15 ms 

Motor Start 250 ms 



Comments 

• Head loads with drive select, wait HD load time before R/W. 

• Following access, wait HD settle time before R/W. 

• Drive motors should be off when not in use. Only A or B and 
C or D may run simultaneously. Wait motor start time before 

R/W. 

• Motor must be on for drive to be selected. 

• Data errors can occur while using a home television as the 
system display. Placing the TV too close to the diskette area 
can cause this to occur. To correct the problem, move the TV 
away from, or to the opposite side of the system unit. 



18 Diskette Adapter 



Interface 



System I/O Channel Interface 

All signals are TTL-compatible: 

Most Positive Up Level +5.5 Vdc 

Least Positive Up Level + 2.7 Vdc 

Most Positive Down Level +0.5 Vdc 

Least Positive Down Level - 0.5 Vdc 

The following lines are used by this adapter. 

+D0-7 (Bidirectional, Load: 1 74LS, Driver: 74LS 3-state): 
These eight lines form a bus through which all 
commands, status, and data are transferred. Bit is 
the low-order bit. 

+A0-9 (Adapter input. Load: 1 74LS): These 10 lines form an 
address bus by which a register is selected to receive or 
supply the byte transferred through lines DO-7. Bit 
is the low-order bit. 

+AEN (Adapter input, load: 1 74LS): The content of lines 
AO-9 is ignored if this line is active. 

-lOW (Adapter input, Load: 1 74LS): The content of lines 
DO-7 is stored in the register addressed by lines AO-9 
or DACK2 at the trailing edge of this signal. 

-lOR (Adapter input. Load: 1 74LS): The content of the 
register addressed by lines AO-9 or DACK2 is gated 
onto lines DO-7 when this line is active. 

-DACK2 (Adapter input, load: 2 74LS): This line being active 
degates output DRQ2, selects the FDC data register as 
the source or destination of bus DO-7, and indirectly 
gates T/C to IRQ6. 



Diskette Adapter 19 



+T/C (Adapter input, load: 4 74LS): This line along with 

DACK2 being active indicates that the byte of data for 
which the DMA count was initialized is now being 
transferred. 

+RESET (Adapter input, load: 1 74LS): An up level ends any 
operation in process and clears the digital output 
register (DOR). 

+DRQ2 (Adapter output, driver: 74LS 3-state): This line is 

made active when the attachment is ready to transfer a 
byte of data to or from main storage. The Hne is made 
inactive by DACK2 becoming active or an I/O read of 
the FDC data register. 

+IRQ6 (Adapter output, driver: 74LS 3-state): This line is 
made active when the FDC has completed an 
operation. It results in an interrupt to a routine that 
should examine the FDC result bytes to reset the line 
and determine the ending condition. 



Drive A and B Interi^ace 

All signals are TTL-compatible: 

Most Positive Up Level +5.5 Vdc 

Least Positive Up Level + 2.4 Vdc 

Most Positive Down Level + 0.4 Vdc 

Least Positive Down Level - 0.5 Vdc 

All adapter outputs are driven by open-collector gates. The 
drives must provide termination networks to Vcc (except 'motor 
enable', which has a 2,000-ohm resistor to Vcc). 

Each adapter input is terminated with a 150-ohm resistor to Vcc. 



20 Diskette Adapter 



Adapter Outputs 



-Drive Select A and B 



(Driver: 7438): These two lines are 
used by drives A and B to degate all 
drivers to the adapter and receivers 
from the attachment (except 'motor 
enable') when the line associated 
with a drive is inactive. 



-Motor Enable A and B 



(Driver: 7438): The drive associated 
with each of these lines must control 
its spindle motor such that it starts 
when the line becomes active and 
stops when the line becomes 
inactive. 



-Step 



(Driver: 7438): The selected drive 
moves the read/ write head one 
cyUnder in or out per the direction 
line for each pulse present on this 
line. 



-Direction 



(Driver: 7438): For each recognized 
pulse of the 'step' line, the 
read/write head moves one cylinder 
toward the spindle if this line is 
active, and away from the spindle if 
inactive. 



-Head Select 



(Driver: 7438): Head 1 (upper 
head) will be selected when this line 
is active (low). 



-Write Data 



(Driver: 7438): For each 
inactive-to-active transition of this 
line while 'write enable' is active, the 
selected drive causes a flux change 
to be stored on the diskette. 



-Write Enable 



(Driver: 7348): The drive disables 
write current in the head unless this 
Hne is active. 



Diskette Adapter 21 



Adapter Inputs 



-Index 



The selected drive must supply one pulse per 
diskette revolution on this line. 



-Write Protect The selected drive must make this line active 

if a write-protected diskette is in the drive. 



-Track 



The selected drive must make this line active 
if the read/write head is over track 0. 



-Read Data 



The selected drive supplies a pulse on this 
hne for each flux change encountered on the 
diskette. 



22 Diskette Adapter 



Specifications 




34- Pin Keyed 
Edge Connector 



Component 
Side 



Note: Lands 1-33 (odd numbers) are on the back of the 

board. Lands 2-34 (even numbers) are on the front or 
component side. 





At Standard TTL Levels 
Ground-Odd Numbers 


LandN 
1-33 


jmb 


er 










Unused 


2,4,6 








Index 


8 








Motor Enable A 


10 








Drive Select B 


12 








Drive Select A 


14 








Motor Enable B 


16 






Diskette 


Direction (Stepper Motor) 


18 




Drive 


Drives 


Step Pulse 


20 




Adapter 




Write Data 


22 








Write Enable 


24 








Track 


26 








Write Protect 


28 








Read Data 


30 








Select Head 1 


32 








Unused 


34 

















Connector Specifications (Part 1 of 2) 



Diskette Adapter 23 



37-Pin D-Shell 
Connector 



20 




37 







At Standard TTL Levels 
Unused 


Pin Nun 
1-5 


iber 
















index 


6 










Motor Enable C 


7 










Drive Select D 


8 










Drive Select C 


9 










Motor Enable D 


10 










Direction (Stepper Motor) 


11 






External 




Step Pulse 


12 




Drive 


Drives 




Write Data 


13 




Adapter 






Write Enable 


14 










Track 


15 










Write Protect 


16 










Read Data 


17 










Select Head 1 


18 










Ground 


20-37 



















Connector Specifications (Part 2 of 2) 



24 Diskette Adapter 



- MOTOR ENABLE 2 



(2) - DRIVE SEUCT 3 
m - DRIVE SELECT 4 
(2) - MOTOR ENABLE 3 



ft 



a. 



TO 10 

2 ALLDRIVES ARE JUMPERED FOR MULTIPLEX OPERATION. HEAD L( 

WITH DRIVE SELECT AND DRIVE SELECT VIA INPUT PIN 12. TERMINATING 
R-PACS ARE LEFT IN DRIVES I & ^ ONLV 
Uj .047UFD SHOULD BE ADJACENT TO MODULES MC 31487, 7^^8. 74S7W. I6MHZ0SC. 
RP-I.MCH0*.MCM02M.7MLSI6I» 74LSI<>1 8.2uR) CAPS SHOULD BE NEAR ASSOCIATED PI PINS 



S MAKE NO CONNECTION TO UNUSED PINS ON THE VCO, CHARGE PUMP & DATA SEPARATOR MODULES 














829 , 803 


RP- 


J 






•1 

1 


*| 8.2 uFD 
1 831,801 


GND^ 


CI 

cq 




>^^_Jn0Te(3]C23 


CIS 


822 












l\ 



r 

o 

o* 
g 

dQ 

5 

(/5 



ALL VOLTAGE AND GROUND CONNECTIONS TO THE VCO. CHARGE PUMP ANC 
COMPONENTS SHOULD BE SEPARATE FROM OTHER CIRCUITS AND THEN Ji 
CIRCUITS AT ONE POINT 






5-1/4 Inch Diskette Drive Adapter (Sheet 1 of 4) 



9\ 







5-1/4 Inch Diskette Drive Adapter (Sheet 2 of 4) 



f 



I 






(1) + INDEX - 
(1) ♦WRITE PROTECT ^ 



(2) + DM A GATE 



NOTE 



s],PRE 5ET 



I I 



iO 



FR/STP 
SEEK 



^^ 



Oj 



f;^ 



t> 



TO 






note: U'4C74LS08J PINS 12 AND 13 ARE 
CONNECTED ONLY ON CARDS 
BUILT USING RAW CARD P/N 5001293 



5-1/4 Inch Diskette Drive Adapter (Sheet 3 of 4) 



+ 16 MHZ (4) 

+S00 KHZ WRITE aOCK (4) 



+ WRITE DATA (1) 
+ DIRECTION (1) 



+ WRITE ENABLE (1) 
+STEP (1) 



+V FO SYNC (4) 

+ SELECT HEAD I (1) 



- +DACK & TC (2) 



00 



i 
1 



(3) +16 MHZ CLOCK 



(1)+READOATA 



DIGITAL ONE-SHOT 



<3)+VCOSYNC 



+STANOARD DATA (3 




+DATA WINDOW (3) 



5-1/4 Inch Diskette Drive Adapter (Sheet 4 of 4) 



Personal Computer 
Hardware Reference 
Library 



IBM Fixed Disk 
Adapter 



6361503 



Contents 



Description 1 

Fixed Disk Controller 1 

Programming Considerations 3 

Status Register 3 

Sense Bytes 4 

Data Register 7 

Control Byte 8 

Command Summary 10 

Programming Summary 14 

Interface 15 

Specifications 17 

Logic Diagrams 19 

BIOS Listing 25 



m 



IV 



Description 



The Fixed Disk Adapter attaches to one or two fixed disk drive 
units through an internal, daisy-chained, flat cable (data/control 
cable). Each system supports a maximum of one Fixed Disk 
Adapter and two fixed disk drives. 

The adapter is buffered on the I/O bus and uses the system 
board's direct memory access (DMA) for record data transfers. 
An interrupt level also is used to indicate operation completion 
and status conditions that require microprocessor attention. 

The Fixed Disk Adapter provides automatic 11 -bit burst error 
detection and correction in the form of 32-bit error checking and 
correction (ECC). 

The device level control for the Fixed Disk Adapter is contained 
on a ROM module on the adapter. A listing of this device level 
control can be found in "BIOS Listing" of this section. 

Warning: The last cylinder on the fixed disk drive is reserved 
for diagnostic use. The diagnostic write test will destroy any 
data on this cylinder. 



Fixed Disk Controller 

The disk controller has two registers that may be accessed by the 
system unit's microprocessor: a status register and a data register. 
The 8 -bit status register contains the status information of the 
disk controller, and can be accessed at any time. The 8-bit data 
register (actually consisting of several registers in a stack with 
only one register presented to the data bus) stores data, 
commands, and parameters, and provides the disk controller's 
status information. Data bytes are read from, or written to the 
data register in order to program or obtain the results after a 
particular command. The status register is a read-only register 
that is used to help the transfer of data between the system unit's 
microprocessor and the disk controller. The controller-select 
pulse is generated by writing to port address hex 322. 



Fixed Disk Adapter 1 






> 

a. 



State Machine 



Edge \j — 
Connector 



I/O 
Interface 



< 



-N 



Control 



C 



Serializer/ 
Deserializer 



J> 



SERDES 
ECC 






Data 
Separator 




J2 




J3 




w 





To 
Drives 



Data Bus 



DB7-DB0 



8-Bit 
Processor 



CO 



A 
V 



:> 



Sector 
Buffer 



CD 



O 

3 



a; 

o 

^^ 

p* 

OQ 

P 

3 

o 



tr 

l-H 

dd 



31 



Fixed Disk Adapter Block Diagram 



> 



Programming Considerations 



Status Register 

At the end of all commands from the system board, the disk 
controller sends a completion status byte to the system board. 
This byte informs the system unit's microprocessor if an error 
occurred during the execution of the command. The following 
shows the format of this byte. 



Bit 


7 


6 


5 


4 


3 


2 


1 













d 











e 






Bits 0, 1, 2, 3, 4, 6, 7 These bits are set to zero. 

Bit 1 When set, this bit shows an error has 

occurred during command execution. 

Bit 5 This bit shows the logical unit number 

of the drive. 

If the interrupts are enabled, the controller sends an interrupt 
when it is ready to transfer the status byte. Busy from the disk 
controller is unasserted when the byte is transferred to complete 
the command. 



Fixed Disk Adapter 3 



Sense Bytes 

If the status register receives an error (bit 1 set), the disk 
controller requests four bytes of sense data. The format for the 
four bytes is as follows: 



Bits 


7 6 


5 4 3 2 1 





ByteO 


Address 
Valid 





Error Type 


Error Code 


Byte 1 





d 


Head Number 


Byte 2 


Cylinder High 


Sector Number 


Byte 3 


Cylinder Low 



Remarks 
d = drive 



Byte Bits 0, 1, 2, 3 

Byte Bits 4, 5 

ByteO Bit 6 

ByteO Bit 7 



Error code. 

Error type. 

Set to (spare) 

The address-valid bit. Set only when 
the previous command required a 
disk address, in which case it is 
returned as a 1 ; otherwise, it is 0. 



4 Fixed Disk Adapter 



Disk Controller Error Tables 

The following disk controller error tables list the error types and 
error codes found in byte 0: 





Error Type 


Error Code 


Description 


Bits 


5 4 


3 2 10 










The controller did not detect any error 
during the execution of the previous 
operation. 







1 


The controller did not detect an index signal 
from the drive. 







10 


The controller did not get a seek-complete 
signal from the drive after a seek operation 
(for all non-buffered step seeks). 







11 


The controller detected a write fault from 
the drive during the last operation. 







10 


After the controller selected the drive, the 
drive did not respond with a ready signal. 







10 1 


Not used. 







110 


After stepping the maximum number of 
cylinders, the controller did not receive the 
track 00 signal from the drive. 







111 


Not used. 







10 


The drive is still seeking. This status is 
reported by the Test Drive Ready command 
for an overlap seek condition when the 
drive has not completed the seek, No 
time-out is measured by the controller for 
the seek to complete. 



Fixed Disk Adapter 5 





Error Type 


Error Code 


Description 


Bits 


5 4 


3 2 10 




1 





ID Read Error: The controller detected an 
ECC error in the target ID field on the disk. 




1 


1 


Data Error: The controller detected an 
uncorrectable ECC error in the target sector 
during a read operation. 




1 


10 


Address Mark: The controller did not detect 
the target address mark (AM) on the disk. 




1 


11 


Not used. 




1 


10 


Sector Not Found: The controller found the 
correct cylinder and head, but not the 
target sector. 




1 


10 1 


Seek Error: The cylinder or head address 
(either or both) did not compare with the 
expected target address as a result of a 
seek. 




1 


110 


Not used. 




1 


111 


Not used. 




1 


10 


Correctable Data Error: The controller 
detected a correctable ECC error in the 
target field. 




1 


10 1 


Bad Track: The controller detected a bad 
track flag during the last operation. No 
retries are attempted on this error. 





Error Type 


Error Code 


Description 


Bits 


5 4 


3 2 1 







1 








Invalid Command: The controller has 
received an invalid command from the 
system unit. 




1 





1 


Illegal Disk Address. The controller 
detected an address that is beyond the 
maximum range. 



6 Fixed Disk Adapter 





Error Type 


Error Code 


Description 


Bits 


5 4 


3 2 10 




1 1 





RAM Error: The Gontroller detected a data 
error during the RAM sector-buffer 
diagnostic test. 




1 1 


1 


Program Memory Checksum Error: During 
this internal diagnostic test, the controller 
detected a program-memory checksum 
error. 




1 1 


10 


ECC Polynominal Error: During the 
controller's internal diagnostic tests, the 
hardware ECC generator failed its test. 



Data Register 

The system unit's microprocessor specifies the operation by 
sending the 6-byte device control block (DCB) to the controller. 
The figure below shows the coniposition of the DCB, and defines 
the bytes that make up the DCB. 



Bit 


7 6 


5 4 3 2 1 





ByteO 


Command 
Class 


Opcode 


Byte 1 





d 


Head Number 


Byte 2 


Cylinder High 


Sector Number 


Byte 3 


Cylinder Low 


Byte 4 


Interleave or Block Count 


Byte 5 


Control Field 



Byte Bits 7,6, and 5 identify the class of the command. 

Bits 4 through contain the Opcode command. 

Byte 1 Bit 5 identifies the drive number. Bits 4 through 

contain the disk head number to be selected. Bits 
6 and 7 are not used. 



Fixed Disk Adapter 7 



Byte 2 Bits 6 and 7 contain the two most significant bits 

of the cylinder number. Bits through 5 contain 
the sector number. 

Byte 3 Bits through 7 are the eight least-significant bits 

of the cylinder number. 

Byte 4 Bits through 7 specify the interleave or block 

count. 

Byte 5 Bits through 7 contain the control field. 



Control Byte 

Byte 5 is the control field of the DCB and allows the user to 
select options for several types of disk drives. The format of this 
byte is as follows: 



Remarks 

r = retries 
s = step option 
a = retry option on data ECC 
error 



Bit 7 Disables the four retries by the controller on all 

disk-access commands. Set this bit only during the 
evaluation of the performance of a disk drive. 

Bit 6 If set to during read commands, a reread is 

attempted when an ECC error occurs. If no error 
occurs during reread, the command will finish 
without an error status. If this bit is set to 1, no 
reread is attempted. 

Bits 5, 4, 3 Set to 0. 



Bits 


7 


6 


5 


4 


3 


2 


1 







r 


a 











s 


s 


s 



8 Fixed Disk Adapter 



Bits 2, 1, These bits define the type of drive and select the 
step option. See the following figure. 



Bits 2, 


1, 
















This drive is pot specified and defaults to 3 milliseconds 
stQp 


per 








1 


N/A 





1 





N/A 





1 


1 


N/A 


1 








200 microseconds per step. 


1 





1 


70 microseconds per step (specified by BIOS). 


1 


1 





3 milliseconds per step. 


1 


1 


1 


3 milliseconds per step. 



Fixed Disk Adapter 9 



Command Summary 



Command 



Data Control Block 



Remarks 



Test Drive 
Ready 
(Class 0, 
Opcode 00) 

Recalibrate 
(Class 0, 
Opcode 01) 



Reserved 
(Class 0, 
Opcode 02) 
Request Sense 
Status 
(Class 0, 
Opcode 03) 

Format Drive 
(Class 0, 
Opcode 04) 



Ready Verify 
(Class 0, 
Opcode 05) 



Bit 


7 6 5 4 3 2 10 


ByteO 








Byte 1 


d 


X X X X X 




Bit 


7 6 5 4 3 2 10 


Byte 





1 


Byte 1 


d 


X X X X X 


Byte 5 


r s s s 



Bit 


7 6 5 4 3 2 10 


Byted 





11 


Byte 1 


d 


X X X X X 



Bit 


7 6 5 4 3 2 10 


ByteO 





10 


Byte 1 


d 


Head Number 


Byte 2 


ch 





Byte 3 


Cylinder Low 


Byte 4 





Interleave 


Byte 5 


r s s s 



Bit 


7 6 5 4 3 2 10 


ByteO 





10 1 


Byte 1 


d 


Head Number 


Byte 2 


ch 


Sector Number 


Byte 3 


Cylinder Low 


Byte 4 


Block Count 


Byte 5 


r a s s s 



d = drive (Oor 1) 

X = don't care 

Bytes 2, 3, 4, 5 = don't 

care 

d = drive (0 or 1 ) 

X = don't care 

r = retries 

s = Step Option 

Bytes 2, 3, 4 = don't 

care 

ch = cylinder high 

This Opcode is not 
used. 

d = drive (Oor 1) 

X = don't care 

Bytes 2, 3, 4, 5 = don't 

care 

d = drive (Oor 1) 
r = retries 
s = step option 
ch = cylinder high 

Interleave 1 to 1 6 
for 51 2-byte sectors. 

d = drive (Oor 1) 

r = retries 

s = step option 

a = retry option on 

data ECC 

ch = cylinder high 



10 Fixed Disk Adapter 



Command 



Data Control Block 



Remarks 



Format Track 
(Class 0, 
Opcode 06) 



Format Bad 
Track 
(Class 0, 
Opcode 07) 



Read 
(Class 0, 
Opcode 08) 



Reserved 
(Class 0, 
Opcode 09) 

Write 
(Class 0, 
Opcode OA) 



Seek 
(Class 0, 
Opcode OB) 



Bit 


7 6 5 4 3 2 10 


ByteO 





110 


Byte 1 


d 


Head Number 


Byte 2 


ch 





Byte 3 


Cylinder Low 


Byte 4 





Interleave 


Byte 5 


r s s s 



Bit 


7 6 5 4 3 2 10 


ByteO 





111 


Byte 1 


d 


Head Number 


Byte 2 


ch 





Byte 3 


Cylinder Low 


Byte 4 





Interleave 


Byte 5 


r s s s 



Bit 


7 6 5 4 3 2 10 


ByteO 





10 


Byte 1 


d 


Head Number 


Byte 2 


ch 


Sector Number 


Byte 3 


Cylinder Low 


Byte 5 


r a s s s 



Bit 


7 6 


5 4 3 2 10 


ByteO 








10 10 


Byte 1 





d 


Head Number 


Byte 2 


ch 


Sector Number 


Byte 3 


Cylinder Low 


Byte 4 


Block Count 


Byte 5 


r 


s s s 




Bit 


7 6 


5 4 3 2 10 


ByteO 








10 11 


Byte 1 





d 


Head Number 


Byte 2 


ch 





Byte 3 


Cylinder Low 


Byte 4 


X X 


X X X X X X 


Byte 5 


r 


s s s 



d = drive (Oor 1) 
r = retries 
s = step option 
ch = cylinder high 

Interleave 1 to 16 
for 512-byte sectors. 

d = drive (Oor 1) 
r = retries 
s = step option 
ch = cylinder high 

Interleave 1 to 1 6 
for 51 2-byte sectors. 

d = drive (0 or 1 ) 
r = retries 
a = retry option on 
data ECC error 
s - step option 
ch = cylinder high 

This Opcode is not 
used. 



d = drive (Oor 1) 
r = retries 
s = step option 
ch = cylinder high 



d = drive (Oor 1) 
r = retries 
s ^ step option 
X = don't care 
ch = cylinder high 



Fixed Disk Adapter 1 1 



Command 



Data Control Block 



Remarks 



Initialize 
Drive 

Characteristics* 
(Class 0, 
Opcode OC) 

Read ECC Burst 
Error Length 
(Class 0, 
Opcode OD) 

Read Data from 
Sector Buffer 
(Class 0, 
Opcode OE) 

Write Data to 
Sector Buffer 
(Class 0, 
Opcode OF) 

RAM 

Diagnostic 
(Class 7, 
Opcode 00) 

Reserved 
(Class 1, 
Opcode 01) 

Reserved 
(Class 7, 
Opcode 02) 



Bit 


7 6 5 4 3 2 10 


ByteO 





110 



Bit 


7 6 5 4 3 2 10 


ByteO 





110 1 




Bit 


7 6 5 4 3 2 10 


ByteO 





1110 




Bit 


7 6 5 4 3 2 10 


ByteO 





1111 




Bit 


7 6 5 4 3 2 10 


ByteO 


1 1 1 






Bytes 1, 2, 3,4, 5, 
don't care 



Bytes 1, 2, 3, 4, 5, 
don't care 



Bytes 1, 2, 3,4, 5, 
don't care 



Bytes 1, 2, 3, 4, 5, 
don't care 



Bytes 1, 2, 3,4, 5, 
don't care 



This Opcode is not 
used. 



This Opcode is not 
used. 



^Initialize Drive Characteristics: The DBC must be followed by eight additional bytes. 
Maximum number of cylinders (2 bytes) 

Maximum number of heads (1 byte) 

Start reduced write current cylinder (2 bytes) 

Start write precompensation cylinder (2 bytes) 

Maximum ECC data burst length (1 byte) 



12 Fixed Disk Adapter 



Command 



Data Control Block 



Remarks 



Drive 

Diagnostic 
(Class 7, 
Opcode 03) 



Controller 
Internal 
Diagnostics 
(Class 7, 
Opcode 04) 

Read Long* 
(Class 7, 
Opcode 05) 



Write Long** 
(Class 7, 
Opcode 06) 



Bit 


7 6 5 4 3 2 10 


ByteO 


1 1 1 


11 


Byte 1 


d 


X X X X X 


Byte 2 


xxxxxxxx 


Byte 3 


xxxxxxxx 


Byte 4 


xxxxxxxx 


Byte 5 


r s s s 




Bit 


7 6 5 4 3 2 10 


ByteO 


1 1 1 


10 



Bit 


7 6 5 4 3 2 10 


ByteO 


1 1 1 


10 1 


Byte 1 


d 


Head Number 


Byte 2 


ch 


Sector Number 


Byte 3 


Cylinder Low 


Byte 4 


Block Count 


Byte 5 


r s s s 




Bit 


7 6 5 4 3 2 10 


ByteO 


1 1 1 


110 


Byte 1 


d 


Head Number 


Byte 2 


ch 


Sector Number 


Byte 3 


Cylinder Low 


Byte 4 


Block Count 


Byte 5 


r s s s 



d = drive (Oor 1) 
s = step option 
r = retries 
X = don't care 



Bytes 1, 2, 3, 4, 5, 
don't care 



d = drive (Oor 1) 
s = step option 
r = retries 
ch = cylinder high 



d = drive (0 or 1 ) 
s = step option 
r = retries 
ch = cylinder high 



*Returns 512 bytes plus 4 bytes of ECC data per sector. 
* *Requires 512 bytes plus 4 bytes of ECC data per sector. 



Fixed Disk Adapter 13 



Programming Summary 

The two least-significant bits of the address bus are sent to the 
system board's I/O port decoder, which has two sections. One 
section is enabled by the I/O read signal (-IOR) and the other by 
the I/O write signal (-IOW). The result is a total of four 
read/write ports assigned to the disk controller board. 

The address enable signal (AEN) is asserted by the system board 
when DMA is controlling data transfer. When AEN is asserted, 
the I/O port decoder is disabled. 

The following figure is a table of the read/ write ports. 



R/W 


Port Address 


Function 


Read 
Write 


320 
320 


Read data (from controller to system unit). 
Write data (from system unit to controller). 


Read 
Write 


321 
321 


Read controller hardware status. 
Controller reset. 


Read 
Write 


322 
322 


Reserved. 

Generate controller-select pulse. 


Read 
Write 


323 
323 


Not used. 

Write pattern to DMA and interrupt mask 

register. 



14 Fixed Disk Adapter 



Interface 



The following lines are used by the disk controller: 

A0-A19 Positive true 20-bit address. The least-significant 10 
bits contain the I/O address within the range of hex 
320 to hex 323 when an I/O read or write is 
executed by the system unit. The full 20 bits are 
decoded to address the read-only memory (ROM) 
between the addresses of hex C8000 and C9FFF. 

DO-D7 Positive 8-bit data bus over which data and status 

information is passed between the system board and 
the controller. 

-lOR Negative true signal that is asserted when the system 

board reads status or data from the controller under 
either programmed I/O or DMA control. 

-low Negative true signal that is asserted when the system 

board sends a command or data to the controller 
under either programmed I/O or DMA control. 

AEN Positive true signal that is asserted when the DMA in 

the system board is generating the I/O Read (-IOR) 
or I/O Write (-IOW) signals and has control of the 
address and data buses. 

RESET Positive true signal that forces the disk controller to 
its initial power-up condition. 

IRQ 5 Positive true interrupt-request signal that is asserted 

by the controller when enabled to interrupt the 
system board on the return ending status byte from 
the controller. 

DRQ 3 Positive true DMA-request signal that is asserted by 

the controller when data is available for transfer to 
or from the controller under DMA control. This 
signal remains active until the system board's DMA 
channel activates the DMA-acknowledge signal 
(-DACK 3) in response. 



Fixed Disk Adapter 15 



-DACK 3 This signal is true when negative, and is generated by 
the system board DMA channel in response to a 
DMA request (DRQ 3). 



16 Fixed Disk Adapter 



Specifications 



The Fixed Disk Adapter connector and interface specifications 
follow. 



Fixed Disk Adapter 17 



Pin 34 



Pin 20 



Pin 2 




Pin 1 



Pin 1 



Position 5 has No Pin 
(for Cable Orientation) 







Signal 

Ground-Odd Numbers 


Pin Number 

1-33 














Reserved 


4,16,30,32 










- Reduced Write Current 


2 










-Write Gate 


6 










- Seek Complete 


8 






Disk 




-Track 00 


10 




Disk 


Drive 




- Write Fault 


12 




Adapter 


Connector 




-Head Select 2° 


14 




Connector 


J1 




-Head Select 21 


18 




J1 






- Index 


20 










- Ready 


22 








- 


-Step 


24 








- Drive Select 1 


26 










- Drive Select 2 


28 








hi- 


- Direction In 


34 





















Signal 
Ground 


Pin Number 

2,4,6,8,12,16,20 
















Drive Select 


1 












Reserved 


3J 












Spare 


9,10,5(No 


Pin) 






Disk 




Ground 


11 






Disk 


Drive 




MFM Wire Data 


13 






Adapter 


Connector 




- MTM Write Data 


14 






Connector 


J2orJ3 




Ground 


15 






J2orJ3 






MFM Read Data 


17 












-MFM Read Data 


18 












Ground 


19 










. 



















Fixed Disk Adapter Interface Specifications 
18 Fixed Disk Adapter 



> 

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Fixed Disk Adapter (Sheet 1 of 6) 



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//////////// 



/ INTERNAL PATA BUS/ 7;^ 3 



Fixed Disk Adapter (Sheet 2 of 6) 



f 

a. 
O 



-ORB SEL ( J3-1 > 
-DRA SEL ( J21 
-INDEX ( J1-20 



-READY ( Jl-22 > 

-SEEK COMP ( Jl-8 > 

-WRITE FAULT ( Jl-12 > 
-TRACK QH! 



2 \ yy.\Hu m\ .m m^ . 



REDUCE WRITE CURRENT 




Fixed Disk Adapter (Sheet 3 of 6) 



bJ 



a. 




Fixed Disk Adapter (Sheet 4 of 6) 



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Fixed Disk Adapter (Sheet 5 of 6) 



-CLAMP 



4.7,yH ^C13 
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* ENABLE NRZ DATA 






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T ex |1 PART) 
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T CX(28 PARTS! 
-"- .01 //F 



■F 1 POINT GROUND 



+ ! C19 
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I 10V 



Tex (2 PARTS), 
i.01+F 

^ AG 



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NOTES: 

UNLESS OTHERWISE SPECIFIED: 

1. ALL RESISTORS 1/4 W. 5%. CARBON FILTER. 

2. ALL CAPS +10V OR GREATER +10%. 

3. NO MORE THAN 15 LOADS PER PULLUP NET. 



Fixed Disk Adapter (Sheet 6 of 6) 



BIOS Listing 

The BIOS Listing for the IBM Fixed Disk Adapter follows. 



Fixed Disk Adapter 25 



$T1TLE( FIXED DISK BIOS FOR IBM DISK CONTROLLER) 

;— INT 13 - - 

; FIXED DISK I/O INTERFACE 

; THIS INTERFACE PROVIDES ACCESS TO 5 1/^" FIXED DISKS 
; THROUGH THE IBM FIXED DISK CONTROLLER. 



THE BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH 
SOFTWARE INTERRUPTS ONLY. ANY ADDRESSES PRESENT IN 
THE LISTINGS ARE INCLUDED ONLY FOR COMPLETENESS, 
NOT FOR REFERENCE. APPLICATIONS WHICH REFERENCE 
ABSOLUTE ADDRESSES WITHIN THE CODE SEGMENT 
VIOLATE THE STRUCTURE AND DESIGN OF BIOS. 



: HEX VALUE) 



(AH)=00 
(AH)=01 



(AH)=02 
(AH)=03 
(AH) = 0<i 
(AH)=05 
(AH)=06 
(AH)=07 
(AH)=08 



RESET DISK (DL = 80H,81H) / DISKETTE 

READ THE STATUS OF THE LAST DISK OPERATION INTO (AL) 

NOTE: DL < 80H - DISKETTE 

DL > 80H - DISK 
READ THE DESIRED SECTORS INTO MEMORY 
WRITE THE DESIRED SECTORS FROM MEMORY 
VERIFY THE DESIRED SECTORS 
FORMAT THE DESIRED TRACK 

FORMAT THE DESIRED TRACK AND SET BAD SECTOR FLAGS 
FORMAT THE DRIVE STARTING AT THE DESIRED TRACK 
RETURN THE CURRENT DRIVE PARAMETERS 



(AH)=09 INITIALIZE DRIVE PAIR CHARACTERISTICS 

INTERRUPT 'fl POINTS TO DATA BLOCK 
(AH)=OA READ LONG 
(AH)=OB WRITE LONG 

NOTE: READ AND WRITE LONG ENCOMPASS 512 ♦ 4 BYTES ECC 
(AH)=OC SEEK 

(AH)=PD ALTERNATE DISK RESET (SEE DL) 
(AH)=OE READ SECTOR BUFFER 
(AH)=OF WRITE SECTOR BUFFER, 

(RECOMMENDED PRACTICE BEFORE FORMATTING) 
(AH)=10 TEST DRIVE READY 
(AH)=11 RECALIBRATE 
(AH)=12 CONTROLLER RAM DIAGNOSTIC 
(AH)=13 DRIVE DIAGNOSTIC 
(AH) = 1<» CONTROLLER INTERNAL DIAGNOSTIC 

REGISTERS USED FOR FIXED DISK OPERATIONS 

(DL) - DRIVE NUMBER (80H-87H FOR DISK, VALUE CHECKED) 

(DH) - HEAD NUMBER (0-7 ALLOWED, NOT VALUE CHECKED) 

(CH) - CYLINDER NUMBER (0-1023, NOT VALUE CHECKED)(SEE CD 

(CD - SECTOR NUMBER (1-17, NOT VALUE CHECKED) 

NOTE: HIGH 2 BITS OF CYLINDER NUMBER ARE PLACED 
IN THE HIGH 2 BITS OF THE CL REGISTER 
(10 BITS TOTAL) 
(AL) - NUMBER OF SECTORS (MAXIMUM POSSIBLE RANGE 1-80H, 
FOR READ/WRITE LONG 1-79H) 
(INTERLEAVE VALUE FOR FORMAT 1-16D) 
(ES:BX) - ADDRESS OF BUFFER FOR READS AND WRITES, 
(NOT REQUIRED FOR VERIFY) 



AH = STATUS OF CURRENT OPERATION 

STATUS BITS ARE DEFINED IN THE EQUATES BELOW 
CY = SUCCESSFUL OPERATION (AH=0 ON RETURN) 
CY = 1 FAILED OPERATION (AH HAS ERROR REASON) 

NOTE: ERROR IIH INDICATES THAT THE DATA READ HAD A RECOVERABLE 
ERROR WHICH WAS CORRECTED BY THE ECC ALGORITHM. THE DATA 
IS PROBABLY GOOD, HOWEVER THE BIOS ROUTINE INDICATES AN 
ERROR TO ALLOW THE CONTROLLING PROGRAM A CHANCE TO DECIDE 
Pnp ITSELF. THE ERROR MAY NOT RECUR IF TH£ O&TA IS 



26 Fixed Disk Adapter 



REWRITTEN. (AD CONTAINS THE BURST LENGTH. 

IF DRIVE PARAMETERS MERE REQUESTED, 

DL = NUMBER OF CONSECUTIVE ACKNOWLEDGING DRIVES ATTACHED (0-2) 

(CONTROLLER CARD ZERO TALLY ONLY) 
DM = MAXIMUM USEABLE VALUE FOR HEAD NUMBER 
CH = MAXIMUM USEABLE VALUE FOR CYLINDER NUMBER 
CL = MAXIMUM USEABLE VALUE FOR SECTOR NUMBER 
AND CYLINDER NUMBER HIGH BITS 

REGISTERS WILL BE PRESERVED EXCEPT WHEN THEY ARE USED TO RETURN 
INFORMATION. 

NOTE: IF AN ERROR IS REPORTED BY THE DISK CODE, THE APPROPRIATE 
ACTION IS TO RESET THE DISK, THEN RETRY THE OPERATION. 



0080 
0040 
0020 
0011 
0010 
OOOB 
0009 
0007 
0005 
0004 
0002 
0001 



SENSE.FAIL 

UNDEF_ERR 

TIME_OUT 

BAD_SEEK 

BAD_CNTLR 

DATA_CORRECTED 

BAD_ECC 

BAD_TRACK 

DMA.BOUNDARY 

INIT_FAIL 

BAD_RESET 

RECORD_NOT_FND 

BAD_ADDR_MARK 

BAD_CMD 



EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 



OFFH 
OBBH 
80H 
40H 
20H 
IIH 
lOH 
OBH 
09H 
07H 
05H 
04H 
02H 
OIH 



1 SENSE OPERATION FAILED 

I UNDEFINED ERROR OCCURRED 

; ATTACHMENT FAILED TO RESPOND 

I SEEK OPERATION FAILED 

; CONTROLLER HAS FAILED 

; ECC CORRECTED DATA ERROR 

I BAD ECC ON DISK READ 

i BAD TRACK FLAG DETECTED 

I ATTEMPT TO DMA ACROSS 64K BOUNDARY 

( DRIVE Parameter activity failed 

I RESET FAILED 

; REQUESTED SECTOR NOT FOUND 

1 ADDRESS MARK NOT FOUND 

t BAD COMMAND PASSED TO DISK I/O 



0034 
0034 
004C 
004C 
0064 
0064 
0078 
0078 
0100 
0100 
0104 
0104 
7C00 
7C00 



113 
114 
115 
116 
117 
118 
119 
120 
121 
122 
123 
124 
125 
126 
127 
128 
129 
130 



INTERRUPT AND STATUS AREAS 



DUMMY SEGMENT 

ORG 
HDISK_INT 

ORG 
ORG_VECTOR 

ORG 
BOOT_VEC 

ORG 
DISKETTE_PARM 

ORG 
DISK_VECTOR 

ORG 
HF_TBL_VEC 

ORG 
B0OT_L0CN 
DUMMY ENDS 



AT 

0DH»4 

UBEL 

13H*4 

LABEL 

19H»4 

LABEL 

1EH»»4 

UBEL 

040H*4 

LABEL 

041H«4 

UBEL 

7C00H 

UBEL 



DWORD 
DWORD 
DWORD 
DWORD 
DWORD 
DWORD 
FAR 



J FIXED DISK INTERRUPT VECTOR 

; DISK INTERRUPT VECTOR 

} BOOTSTRAP INTERRUPT VECTOR 

; DISKETTE PARAMETERS 

; NEW DISKETTE INTERRUPT VECTOR 

5 FIXED DISK PARAMETER VECTOR 

5 BOOTSTRAP LOADER VECTOR 



0042 
0042 

0042 (7 ' 
006C 

006C ???• 
0072 

0072 ???; 
0074 

0074 ?? 

0075 ?? 

0076 ?? 

0077 ?? 



133 
134 
135 
136 
137 
138 
139 
140 
141 
142 
143 
144 
145 
146 
147 



DATA 



SEGMENT AT 40H 



ORG 
CMD_BLOCK 
HD_ERROR 

ORG 
TIMER_LOW 

ORG 
RESET_FUG 

ORG 
DISK_STATUS 
HF_NUM 
CONTROL_BYTE 
PORT_OFF 
DATA ENDS 



42H 
UBEL 



BYTE 

7 DUP(?) 



; OVERUYS DISKETTE STATUS 

; TIMER LOW WORD 

; 1234H IF KEYBOARD RESET UNDERWAY 

; FIXED DISK STATUS BYTE 
; COUNT OF FIXED DISK DRIVES 
; CONTROL BYTE DRIVE OPTIONS 
; PORT OFFSET 



149 
150 



; HARDWARE SPECIFIC VALUES 



153 
154 



CONTROLLER I/O PORT 
> WHEN READ FROMi 



Fixed Disk Adapter 27 



157 
158 



163 
le^i 
165 



HF_PORT+0 - READ DATA (FROM CONTROLLER TO CPU) 
HF_P0RT+1 - READ CONTROLLER HARDWARE STATUS 

(CONTROLLER TO CPU) 
HF_P0RT+2 - READ CONFIGURATION SWITCHES 
HF_P0RT+3 - NOT USED 
► WHEN WRITTEN TO: 
HF_PORT+0 - WRITE DATA (FROM CPU TO CONTROLLER) 
HF .PORT+1 - CONTROLLER RESET 
HF_P0RT+2 - GENERATE CONTROLLER SELECT PULSE 
HF_P0RT+3 - WRITE PATTERN TO DMA AND INTERRUPT 

MASK REGISTER 



0320 
0008 
0004 
0002 
0001 

0047 
004B 
0000 
0082 

0000 
0001 
0003 
0004 
0005 
0006 
0007 
0008 
OOOA 
OOOB 
OOOC 
0000 
OOOE 
OOOF 
OOEO 
00E3 
00E4 
00E5 
00E6 

0020 
0020 

0008 
0002 



0000 

0000 55 

0001 AA 

0002 10 



167 
168 
169 



173 
174 
175 
176 
177 
178 



183 
184 
185 



193 
194 
195 
196 
197 
198 
199 
200 
201 
202 
203 
204 
205 
206 
207 
208 
209 
210 



HF_PORT 

R1_BUSY 

R1_BUS 

R1_I0M0DE 

Rl.REQ 

DMA_READ 
DMA_WRITE 
DMA 
DMA_HIGH 

TST_RDY_CMO 

RECAL_CMD 

SENSE_CMD 

FMTDRV_CMD 

CHK_TRK_CMD 

FMTTRK_CMD 

FMTBAD_CMD 

READ_CMD 

WRITE_CMD 

SEEK_CMD 

INIT_DRV_CMD 

RD_ECC_CMD 

RD_BUFF_CMD 

WR_BUFF_CMD 

RAM_DIAG_CMD 

CHK_DRV_CMD 

CNTLR_DIAG_CMD 

RD_LONG_CMD 

WR_LONG_CMD 



EQU 0320H 

EQU OOOOIOOOB 

EQU OOOOOIOOB 

EQU OOOOOOIOB 

EQU OOOOOOOIB 

EQU OlOOOlllB 

EQU OlOOlOllB 

EQU 

EQU 082H 



EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 
EQU 



MAX_FILE 
S_MAX_FILE 



EQU 
EQU 



OOOOOOOOB 
OOOOOOOIB 
OOOOOOHB 
OOOOOIOOB 
OOOOOIOIB 
OOOOOllOB 
OOOOOIUB 
OOOOIOOOB 
OOOOIOIOB 
OOOOIOIIB 
OOOOllOOB 
OOOOIIOIB 
OOOOlllOB 
OOOOllUB 
lllOOOOOB 
lllOOOHB 
IIIOOIOOB 
IIIOOIOIB 
lllOOllOB 



INT_CTL_PORT EQU 20H 
EOI EQU 20H 



ASSUME CS:CODE 

ORG OH 

DB 055H 

OB OAAH 

DB 16D 



DISK PORT 

DISK PORT 1 BUSY BIT 

COMMAND/DATA BIT 
MODE BIT 
REQUEST BIT 

CHANNEL 3 ( 047H ) 

CHANNEL 3 ( 04BH ) 

DMA ADDRESS 

PORT FOR HIGH 4 BITS OF DMA 



CNTLR READY 


(OOH) 


RECAL 


(OIH) 


SENSE 


(03H) 


DRIVE 


(04H) 


T CHK 


(05H) 


TRACK 


(06H) 


BAD 


(07H) 


READ 


(08H) 


WRITE 


(OAH) 


SEEK 


(OBH) 


INIT 


(OCH) 


BURST 


(ODH) 


BUFFR 


(OEH) 


BUFFR 


(OFH) 


RAM 


(EOH) 


DRV 


(E3H) 


CNTLR 


(E4H) 


RLONG 


(E5H) 


WLONG 


(E6H) 



8259 CONTROL PORT 

END OF INTERRUPT COMMAND 



; GENERIC BIOS HEADER 



0003 

0003 EBIE 

0005 35303030303539 
2028432 9434F50 
59524947485420 
2049424D203139 
3832 

0023 

0023 2BC0 
0025 8ED8 



212 
213 
214 
215 
216 
217 
218 
219 
220 
221 
222 
223 



224 
225 
226 
227 



FIXED DISK I/O SETUP 

- ESTABLISH TRANSFER VECTORS FOR THE FIXED DISK 

- PERFORM POWER ON DIAGNOSTICS 

SHOULD AN ERROR OCCUR A "1701" MESSAGE IS DISPLAYED 



DISK_SETUP 
JMP 



PROC FAR 
SHORT L3 
'5000059 (OCOPYRIGHT 



; COPYRIGHT NOTICE 



ASSUME DS: DUMMY 
SUB AX, AX 
MOV DS.AX 



28 Fixed Disk Adapter 



0027 FA 


228 


0028 A14C00 


229 


002B A30001 


230 


002E AHEOO 


231 


0031 A30201 


232 


003^ C7064C005602 


233 


003A 8C0E<«E00 


23"* 


003E B86007 


235 


oo<n ^^l(^oo 


236 


00^<» 8C0E36OO 


237 


00^8 C70664008601 


238 


004E 6C0E6600 


239 


0052 C7060<tOlE703 


240 


0056 8C0E0601 


2<»1 


005C FB 


242 




243 




244 


005D BS-iOOO 


245 


0060 8E08 


246 


0062 C6067<»0000 


247 


0067 C606750000 


248 


006C C606430000 


249 


0071 C606770000 


250 




251 


0076 B92500 


252 


0079 


253 


0079 E8F200 


254 


007C 7305 


255 


007E E2F9 


256 


0080 E9BF00 


257 


0083 


258 


0083 B90100 


259 


0086 BA8000 


260 




261 


0089 B80012 


262 


008C CD13 


263 


008E 7303 


264 


0090 E9AF00 


265 


0093 


266 


0093 B8001<i 


267 


0096 C013 


268 


0098 7303 


269 


009A E9A500 


270 


009D 


271 


0090 C7066COOOOOO 


272 


00A3 A17200 


273 


00A6 3D3412 


274 


00A9 7506 


275 


OOAB C7066C009A01 


276 


OOBl 


277 


OOBl E421 


278 


00B3 2^FE 


279 


00B5 E621 


280 


00B7 


281 


00B7 E8B<^00 


282 


OOBA 7207 


283 


OOBC B80010 


284 


OOBF CD13 


285 


OOCl 730B 


286 


00C3 


287 


00C3 A16C00 


288 


00C6 3DBE01 


289 


00C9 72EC 


290 


OOCB EB7590 


291 


OOCE 


292 


OOCE B90100 


293 


0001 BA8000 


294 




295 


OODC^ B80011 


296 


0007 C013 


297 


0009 7267 


298 




299 


OODB B80009 


300 


OOOE CD13 


301 


OOEO 7260 


302 




303 


00E2 B800C& 


304 



CLI 
MOV 
MOV 
MOV 
MOV 
MOV 
MOV 
MOV 
MOV 
MOV 
MOV 
MOV 
MOV 
MOV 
STI 

ASSUME 

MOV 

MOV 

MOV 

MOV 

MOV 

MOV 



AX, WORD PTR ORG.VECTOR 

WORD PTR DISK_VECTOR,AX 

AX, WORD PTR 0RG_VECT0R+2 

WORD PTR DISK_VECT0R+2,AX 

WORD PTR ORG_VECTOR, OFFSET DISK_10 

WORD PTR CRG_VECT0R+2,CS 

AX, OFFSET HD_1NT 

WORD PTR HDISK_1NT,AX 

WORD PTR H0ISK_INT+2,CS 

WORD PTR BOOT_VEC, OFFSET B0OT_STRAP 

WORD PTR B00T_VEC+2,CS 

WORD PTR HF_TBL_VEC, OFFSET FD.TBL 

WORD PTR HF_TBL_VEC+2,CS 



; GET DISKETTE VECTOR 
; INTO INT 40H 



; HDISK HANDLER 
} HDISK INTERRUPT 

5 BOOTSTRAP 

; PARAMETER TBL 



OS: DATA 
AX, DATA 
OS, AX 

DISK_STATUS,0 
HF_NUM,0 
CMD_B LOCK +1,0 
PORT_OFF,0 



CALL 


HD_RESET_1 


JNC 


L7 


LOOP 


L4 


JMP 


ERROR_EX 


MOV 


CX,1 


MOV 


DX,80H 


MOV 


AX,1200H 


INT 


13H 


JNC 


P7 


JMP 


ERROR_EX 


MOV 


AX,1400H 


INT 


13H 


JNC 


P9 


JMP 


ERROR_EX 


MOV 


TIMER_LOW,0 


MOV 


AX,RESET_FLAG 


CMP 


AX,1234H 


JNE 


P8 


MOV 


TIMER_LOW,410C 


IN 


AL,021H 


AND 


AL,OFEH 


OUT 


021H,AL 


CALL 


H0_RESET_1 


JC 


PIO 


MOV 


AX,1000H 


INT 


13H 


JNC 


P2 


MOV 


AX, TIMER. LOW 


CMP 


AX, 4460 


JB 


P4 


JMP 


ERROR_EX 


MOV 


CX.l 


MOV 


DX,80H 


MOV 


AX.llOOH 


INT 


13H 


JC 


ERROR_EX 


MOV 


AX,0900H 


INT 


13H 


JC 


ERROR_EX 


MOV 


AX.OCBOOH 



t ESTABLISH SEGMENT 

5 RESET TWE STATUS INDICATOR 

J ZERO COUNT OF DRIVES 

; DRIVE ZERO, SET VALUE IN BLOCK 

J ZERO CARD OFFSET 

; RETRY COUNT 

; RESET CONTROLLER 

5 TRY RESET AGAIN 



J CONTROLLER DIAGNOSTICS 

{ CONTROLLER DIAGNOSTICS 

} ZERO TIMER 

; KEYBOARD RESET 

; SKIP WAIT ON RESET 

5 TIMER 

; ENABLE TIMER 

; START TIMER 

; RESET CONTROLLER 

i READY 



; 25 SECONDS 



I RECALIBRATE 



1 SET DRIVE PARAMETERS 



5 DMA TO BUFFER 



Fixed Disk Adapter 29 



00E5 8EC0 
00E7 2BDB 
00E9 B8000F 
OOEC CD13 
OOEE 7252 



305 
306 
307 
308 
309 



MOV ES.AX 

SUB BX,BX 

MOV AX.OFOOH 

INT 13H 

JC ERROR EX 



! SET SEGMENT 

5 WRITE SECTOR BUFFER 



OOFO FE067500 

00F4 BA1302 

00F7 BOOO 

00F9 EE 

OOFA BA2103 

OOFD EC 

OOFE 240F 

0100 3C0F 

0102 7<i06 

0104 C7066C00A'*01 

OlOA 

OlOA BA1302 

OlOD BOFF 

OlOF EE 

0110 B90100 
0113 BA8100 
0116 

0116 2BC0 
0118 CD13 
OllA 7240 
one B80011 
OllF CD13 
0121 730B 
0123 A16C00 
0126 3DBE01 
0129 72EB 
012B EB2F90 
012E 

012E B80009 
0131 C013 
0133 7227 
0135 FE067500 

0139 81FA6100 
013D 731D 
013F 42 

0140 EBD4 



313 
314 
315 
316 
317 
318 
319 
320 



323 
324 
325 
326 
327 
328 
329 



333 
334 
335 
336 
337 
338 
339 
340 
341 
342 
343 
344 
345 
346 
347 
348 
349 
350 



MOV 
MOV 
OUT 
MOV 
IN 
AND 
CMP 



MOV 
MOV 
OUT 

MOV 
MOV 

SUB 
INT 
JC 
MOV 
INT 
JNC 
MOV 
CMP 



MOV 
INT 
JC 
INC 
CMP 
JAE 
INC 
JMP 



DX,213H 

AL,0 

DX,AL 

DX,321H 

AL.DX 

AL.OFH 

AL.OFH 

BOX_ON 

TIMER_LOW,420D 

DX,213H 
AL.OFFH 
DX.AL 

CX.l 
DX,081H 



POD_DONE 
AX.OllOOH 



AX.TIMER.LOW 
AX,446D 



AX,0900H 

13H 

POD_D0NE 

HF_NUM 

DX,(80H + S_MAX_FILE - 

POD_DONE 

DX 



; DRIVE ZERO RESPONDED 

5 EXPANSION BOX 

i TURN BOX OFF 

J TEST IF CONTROLLER 

I ... IS IN THE SYSTEM UNIT 



5 CONTROLLER IS IN SYSTEM UNIT 

5 EXPANSION BOX 

i TURN BOX ON 

J ATTEMPT NEXT DRIVES 



25 SECONDS 



INITIALIZE CHARACTERISTICS 



5 TALLY ANOTHER DRIVE 



0142 




0142 


BDOFOO 


0145 


2BC0 


0147 


8BF0 


0149 


B9060090 


014D 


B700 


014F 




014F 


2E8A846801 


0154 


B40E 


0156 


CDIO 


0158 


46 


0159 


E2F4 


015B 


F9 


015C 




015C 


FA 


015D 


E421 


015F 


OCOl 


0161 


E621 


0163 


FB 


0164 


E8A500 


0167 


CB 


0168 


31373031 


016C 


OD 


016D 


OA 


0006 


016E 




016E 


51 


016F 


52 



352 
353 
354 
355 
356 
357 
358 
359 



363 
364 
365 
366 
367 
368 
369 
370 



373 
374 



ERROR^EX: 

MOV 
SUB 
MOV 
MOV 
MOV 

OUT^CH: 

MOV 
MOV 
INT 
INC 
LOOP 
STC 

POO_DONE : 

CLI 

IN 

OR 

OUT 

STI 

CALL 

RET 



BP.OFH 
AX, AX 
SI, AX 
CX,F17L 
BH,0 

AL,CS:F17[SI] 
AH,14D 



AL,021H 
AL.OIH 
021H,AL 



•1701',0DH,0AH 



; POO ERROR FLAG 



i MESSAGE CHARACTER COUNT 
5 PAGE ZERO 

I GET BYTE 

; VIDEO OUT 

; DISPLAY CHARACTER 

; NEXT CHAR 

; DO MORE 



5 BE SURE TIMER IS DISABLED 



377 


HD_RE 


SET_1 


PROC 


NEAR 


378 




PUSH 


CX 




379 




PUSH 


DX 





SAVE REGISTER 



30 Fixed Disk Adapter 



0170 F8 

0171 B90001 
0174 

017'+ Ee0706 

0177 EE 

0178 E80306 
017B EC 
017C 2402 
017E 7403 
0180 E2F2 

0182 F9 
0183 

0183 5A 

0184 59 

0185 C3 



0186 2BC0 
0188 8ED8 



018A FA 

0138 C7060401E703 
0191 8C0E0601 
0195 C70678000102 
019B 8C0E7A00 
019F FB 



OlAO B90300 
01A3 
01A3 51 
01A4 2BD2 
01A6 2BC0 
01A8 CD13 
OlAA 720F 
OlAC B80102 

OlAF 2BD2 
OlBl 8EC2 
01B3 BB007C 

01B6 B90100 
01B9 CD13 
OIBB 59 
OIBC 730A 
OIBE 80FC80 
OlCl 740A 
01C3 E2DE 
01C5 EB0690 



01C8 



382 
383 



387 
388 



393 
394 
395 
396 
397 
398 
399 
400 
401 
402 
403 
404 
405 
406 
407 
408 
409 
410 
411 
412 
413 
414 
415 
416 
417 
418 
419 
420 
421 
422 
423 
424 
425 
426 
427 
428 
429 
430 
431 
432 
433 
434 
435 
436 
437 
438 
439 
440 
441 
442 
443 
444 
445 
446 
447 
448 
449 
450 
451 
452 
453 
454 
455 
456 



CLC 
MOV 

CALL 
OUT 
CALL 



LOOP 
STC 



P0RT_1 

DX.AL 

P0RT_1 

AL,DX 

AL,2 

R3 



; CLEAR CARRY 
RETRY COUNT 



CHECK STATUS 
ERROR BIT 



RESTORE REGISTER 



POP 
RET 
HD_RESET_1 



INTERRUPT 19 BOOT STRAP LOADER 

- THE FIXED DISK BIOS REPLACES THE INTERRUPT 19 

BOOT STRAP VECTOR WITH A POINTER TO THIS BOOT ROUTINE 

- RESET THE DEFAULT DISK AND DISKETTE PARAMETER VECTORS 

- THE BOOT BLOCK TO BE READ IN WILL BE ATTEMPTED FROM 
CYLINDER SECTOR 1 OF THE DEVICE. 

- THE BOOTSTRAP SEQUENCE IS: 

> ATTEMPT TO LOAD FROM THE DISKETTE INTO THE BOOT 
LOCATION (0000:7C00) AND TRANSFER CONTROL THERE 

> IF THE DISKETTE FAILS THE FIXED DISK IS TRIED FOR A 
VALID BOOTSTRAP BLOCK. A VALID BOOT BLOCK ON THE 
FIXED DISK CONSISTS OF THE BYTES 055H OAAH AS THE 
LAST TWO BYTES OF THE BLOCK 

> IF THE ABOVE FAILS CONTROL IS PASSED TO RESIDENT BASIC 



BOOT_STRAP: 

ASSUME DS: DUMMY, ES: DUMMY 

SUB AX, AX 

MOV DS,AX 



5 ESTABLISH SEGMENT 



■ RESET PARAMETER VECTORS 



CLI 
MOV 
MOV 
MOV 
MOV 
STI 



WORD PTW HF_TBL_VEC, OFFSET rD_TBL 

WORD PTR HF_TBL_VEC+2, CS 

WORD PTR DISKETTE_PARM, OFFSET DISKETTE_TBL 

WORD PTR DISKETTE_PARM+2, CS 



• ATTEMPT BOOTSTRAP FROM DISKETTE 



PUSH 


CX 


SUB 


DX,DX 


SUB 


AX, AX 


INT 


13H 


JC 


H2 


MOV 


AX,0201H 



SUB DX.DX 

MOV ES,DX 

MOV BX, OFFSET BOOT_LOCN 

MOV CX,l 

INT 13H 

POP CX 

JNC H4 

CMP AH, BOH 

JZ H5 

LOOP HI 

JMP H5 



! SET RETRY COUNT 
5 IPL_SYSTEM 
; SAVE RETRY COUNT 
; DRIVE ZERO 

RESET THE DISKETTE 

FILE 10 CALL 

IF ERROR, TRY AGAIN 

READ IN THE SINGLE SECTOR 



; ESTABLISH SEGMENT 



; SECTOR 1, TRACK 

i FILE 10 CALL 

; RECOVER RETRY COUNT 

( CF SET BY UNSUCCESSFUL READ 

; IF TIME OUT, NO RETRY 

; TRY FIXED DISK 

( DO IT FOR RETRY TIMES 

; UNABLE TO IPL FROM THE DISKETTE 

i IPL WAS SUCCESSFUL 



Fixed Disk Adapter 31 



01C8 EA007C0000 



OICD 

OICD 2BC0 
OICF 2BD2 
OlDl CD13 
0103 B90300 
01D6 
01D6 51 
01D7 BA8000 
OlDA 2BC0 
OlDC CD13 
OlDE 7212 
OlEO B80102 
01E3 2BDB 
01E5 8EC3 
01E7 BB007C 
OlEA BA8000 
OlED B90100 
OlFO CD13 
01F2 59 
01F3 7208 
01F5 A1FE7D 
01F8 3D55AA 
OlFB 74CB 
OlFD 
OlFD E207 



0201 CF 

0202 02 

0203 25 
020<+ 02 
020$ 08 

0206 2A 

0207 FF 

0208 50 

0209 F6 
020A 19 
020B 0<+ 



020C 


IE 


020D 


B84000 


0210 


8E08 


0212 


8A267700 


0216 


50 


0217 


C606770000 


021C 


E86905 


021F 


2AC0 


0221 


EE 


0222 


C60677000<t 


0227 


E85E05 


022A 


2AC0 


022C 


EE 


022D 


C606 770008 


0232 


E85305 


0235 


2AC0 


0237 


EE 


0238 


C60677000C 


0230 


E84805 


02'tO 


2AC0 


0242 


EE 


02'^3 


B007 


0245 


E60A 



457 
458 
459 
460 
461 
462 
463 
464 
465 
466 
467 
468 
469 
470 
471 
472 
473 
474 
475 
476 
477 
478 
479 
480 
481 
482 
483 
484 
485 
486 
487 
468 
489 
490 
491 
492 
493 
494 
495 
496 
497 
498 
499 
500 
501 
502 
503 
504 
505 
506 
507 
508 
509 
510 
511 
512 
513 
514 
515 
516 
517 
518 
519 
520 
521 
522 
523 
524 
525 
526 
527 
528 
529 
530 
531 
532 
533 



■ ATTEMPT BOOTSTRAP FROM FIXED DISK 



SUB 


AX, AX 






5 RESET DISKETTE 


SUB 


DX.DX 








INT 


13H 








MOV 


CX,3 






5 SET RETRY COUNT 
; IPL_SYSTEM 


PUSH 


CX 






J SAVE RETRY COUNT 


MOV 


DX.OOBOH 






; FIXED DISK ZERO 


SUB 


AX, AX 






; RESET THE FIXED DISK 


INT 


13H 






i FILE 10 CALL 


JC 


H7 






I IF ERROR, TRY AGAIN 


MOV 


AX,0201H 






! READ IN THE SINGLE SECTOR 


SUB 


BX,BX 








MOV 


ES,BX 








MOV 


BX, OFFSET BOOT. 


.LOCN 


; TO THE BOOT LOCATION 


MOV 


DX.eOH 






; DRIVE NUMBER 


MOV 


CX,1 






; SECTOR 1, TRACK 


INT 


13H 






; FILE 10 CALL 


POP 


CX 






; RECOVER RETRY COUNT 


JC 


H6 








MOV 


AX, WORD PTR 


BOOT_L0CN^ 


h510D 


CMP 


AX,0AA55H 






; TEST FOR GENERIC BOOT BLOC 



DO IT FOR RETRY TIMES 



• UNABLE TO IPL FROM THE DISKETTE OR FIXED DISK 



RESIDENT BASIC 



DISKETTE_TBL: 



02AH 
OFFH 
050H 
0F6H 
25 



SRT=C, HD UNLOAD=OF - 1ST SPEC BYTE 
HD L0AD=1, MODE=DMA - 2ND SPEC BYTE 
WAIT AFTER OPN TIL MOTOR OFF 
512 BYTES PER SECTOR 
EOT (LAST SECTOR ON TRACK) 
; GAP LENGTH 
DTL 

GAP LENGTH FOR FORMAT 
FILL BYTE FOR FORMAT 
HEAD SETTLE TIME (MILLISECONDS) 
MOTOR START TIME (1/8 SECOND) 



■ MAKE SURE THAT ALL HOUSEKEEPING IS DONE BEFORE EXIT 



NEAR 
DS:DATA 



PROC 

ASSUME 

PUSH OS 

MOV AX, DATA 

MOV OS, AX 



MOV 
PUSH 

MOV 
CALL 
SUB 
OUT 
MOV 
CALL 
SUB 
OUT 
MOV 
CALL 
SUB 
OUT 
MOV 
CALL 
SUB 
OUT 
MOV 
OUT 



AH,PORT_OFF 



PORT_OFF,0H 

P0RT_3 

AL,AL 

DX.AL 

P0RT_0FF,4H 

P0RT_3 

AL.AL 

DX.AL 

P0RT_0FF,8H 

P0RT_3 

AL.AL 

DX,AL 

PORT_OFF,0CH 

P0RT_3 

AL,AL 

DX.AL 

AL*07H 

DMA+10,AL 



SAVE SEGMENT 



SAVE OFFSET 



; RESET INT/DMA MASK 



; RESET INT/DMA MASK 



1 RESET INT/DMA MASK 



RESET INT/DMA MASK 



; SET DMA MODE TO DISABLE 



32 Fixed Disk Adapter 



02<+7 FA 

02<*8 E<i21 

02^A 0C2O 

02^C E621 

02'^E FB 

02':fF 58 

0250 86267700 

025<:f IF 

0255 C3 



0256 80FA80 

0259 7305 
025B CD^O 
025D 

0250 CA0200 
0260 

0260 FB 

0261 OAE-i 
0263 7509 
0265 C040 
0267 2AE* 
0269 80FA81 
026C 77EF 
026E 

026E 80FC08 
0271 7503 
0273 E91A01 
0276 

0276 53 

0277 51 

0278 52 

0279 IE 
027A 06 
027B 56 
027C 57 

027D E86A00 

0280 50 

0281 EeSSFF 
0284 B84000 
0287 8ED8 
0289 58 

028A 8A267400 
028E 80FC01 

0291 F5 

0292 5F 

0293 5E 

0294 07 

0295 IF 

0296 5A 

0297 59 

0298 5B 

0299 CA0200 



029C 

029C 3803 
029E 4D03 
02AO 5603 
02A2 6003 
02A4 6A03 
02A6 7203 
02A8 7903 
02AA 8003 
02AC 3003 
02AE 2704 
02B0 CF04 
02B2 D004 



534 
535 
536 
537 
538 
539 
540 
541 
542 
543 
544 
545 
546 
547 
548 
549 
550 
551 
552 
555 
554 
555 
556 
557 
558 
559 
560 
561 
562 
563 
564 
565 
566 
567 
568 
569 
570 
571 
572 
573 
574 
575 
576 
577 
578 
579 
580 
581 
582 
583 
584 
585 
586 
587 
588 
589 
590 
591 
592 
593 
594 
595 
596 
597 
598 
599 
600 
601 
602 
603 
604 
605 
606 
607 
608 
609 
610 



IN 


AL.OZIH 


OR 


AL,020H 


OUT 


021H,AL 


STI 




POP 


AX 


MOV 


PORT_OFF,AH 


POP 


DS 


RET 




ENDP 





! DISABLE INTERRUPTS 



; DISABLE INTERRUPT 5 
; ENABLE INTERRUPTS 
} RESTORE OFFSET 

i RESTORE SEGMENT 



FIXED DISK BIOS ENTRY POINT 



OISK_IO PROC FAR 

ASSUME DS: NOTHING, ES: NOTHING 

CMP DL.eOH 

JAE HARD_DISK 

INT 40H 
RET_2: 

RET 2 
HARD_DISK: 

ASSUME OS: DATA 

STI 

OR AH, AH 



JNZ 
INT 
SUB 
CMP 



CMP 
JNZ 
JMP 

PUSH 
PUSH 
PUSH 
PUSH 
PUSH 
PUSH 
PUSH 



PUSH 
CALL 
MOV 
MOV 
POP 
MOV 
CMP 
CMC 
POP 
POP 
POP 
POP 
POP 
POP 
POP 
RET 
DISK_IO ENDP 



A3 



DL,(80H + S_MAX_FILE • 
RET_2 



GET FARM N 



DISK_IO_CONT 



DSBL 

AX, DATA 

DS.AX 

AX 

AH,DISK_STATUS 

AH,1 



WORD 

DISK_RESET 

RETURN_STATUS 

DISK_READ 

DISK^WRITE 

DISK_VERF 

FMT_TRK 

FMT_BAD 

FMT_DRV 

BAD_COMMANO 

INIT_DRV 

RD_LONG 

WR_LONG 



; TEST FOR FIXED DISK DRIVE 
; YES, HANDLE HERE 
i DISKETTE HANDLER 

5 BACK TO CALLER 



} ENABLE INTERRUPTS 



; RESET NEC WHEN AH=0 



; GET PARAMETERS IS A SPECIAL CASE 



; SAVE REGISTERS DURING OPERATION 



; PERFORM THE OPERATION 

; BE SURE DISABLES OCCURRED 

} ESTABLISH SEGMENT 

GET STATUS FROM OPERATION 

SET THE CARRY FLAG TO INDICATE 

SUCCESS OR FAILURE 
RESTORE REGISTERS 



THROW AHAY SAVED FUCS 



FUNCTION TRANSFER TABLE 

OOOH 

; OOIH 

; 002H 

1 003H 

; 004H 

; 005H 

; 006H 

I 007H 

; 008H 

; 009H 

I OOAH 

I OOBH 



Fixed Disk Adapter 33 



02B<+ F20^ 
02B6 3803 
02B8 F90^ 
02BA 0705 
02BC 1505 
02BE 1C05 
02CO 2305 
02C2 2A05 
02C^ 3105 
002A 



02C6 C606740000 
02CB 51 



02CC 8AEA 
02CE 80CA01 
02D1 FECA 
02D3 D0E2 
02D5 88167700 
02D9 8AD5 
02DB 80E201 

02DE BIOS 
02E0 D2E2 
02E2 0AD6 
02E<+ 8816-^300 
02E8 59 
02E9 C3 



02EA 
02EA 50 
02EB BS^OOO 
02EE 8E08 
02F0 58 
02F1 80FC01 
02F'+ 7503 
02F6 EB5590 
02F9 

02F9 80EA80 
02FC 80FA08 
02FF 732F 

0301 E8C2FF 



030^ 


FEC9 


0306 


C606^20000 


030B 


880Ei*^00 


030F 


882E^500 


0313 


A2^600 


0316 


A07600 


0319 


A24700 


031C 


50 


031D 


8AC4 


031F 


32E'* 


0321 


DIEO 


0323 


6BF0 


0325 


3D2A00 


0328 


58 


0329 


7305 


032B 


2EFFA^9C02 


0330 




0330 


06067-^0001 


0335 


BOOO 


0337 


C3 



611 
612 
613 
614 
615 
616 
617 
618 
619 
620 
621 
622 
623 
62-* 
625 
626 
627 
628 
629 
630 
631 
632 
633 
634 
635 
636 
637 
638 
639 
640 
641 
642 
643 
644 
645 
646 
647 
648 
649 
650 
651 
652 
653 
654 
655 
656 
657 
658 
659 
660 
661 
662 
663 
664 
665 
666 
667 
668 
669 
670 
671 
672 
673 
674 
675 
676 
677 
678 
679 
680 
681 
682 
683 
684 
6PS 
686 
687 



DISK_SEEK 

DISK_RESET 

RD_BUFF 

WR_BUFF 

TST_RDY 

HDISK_RECAL 

RAM_DIAG 

CHK_DRV 

CNTLR_DIAG 

$-Ml 



SETUP_A PROC 



MOV DISK_STATUS,0 
PUSH CX 



■ CALCULATE THE PORT OFFSET 



CH.DL 

DL.l 

DL 

DL.l 

PORT_OFF,DL 

DL.CH 

DL.l 

CL,5 

DL.CL 

DL.DH 

CMD_BL0CK+1,DL 

CX 



DEC 
SHL 
MOV 
MOV 
AND 

MOV 
SHL 
OR 
MOV 
POP 
RET 
SETUP_A ENDP 

DISK_IO_CONT 
PUSH 
MOV 
MOV 
POP 
CMP 
JNZ 
JMP 



A4: 



SUB 
CMP 
JAE 



AX, DATA 
DS.AX 



RETURN_STATUS 

DL,80H 

DL,MAX_FILE 

BAD_COMMAND 



• SET UP COMMAND BLOCK 



DEC 
MOV 
MOV 
MOV 
MOV 
MOV 
MOV 
PUSH 
MOV 
XOR 
SAL 
MOV 
CMP 
POP 
JNB 
JMP 

BAD_COMMAND : 
MOV 
MOV 
RET 

DISK_IO_CONT 



OOCH 
OODH 
OOEH 
OOFH 
OIDH 
OllH 
012H 
013H 
014H 



; RESET THE STATUS INDICATOR 
I SAVE CX 



GENERATE OFFSET 
STORE OFFSET 
RESTORE DL 



; SHIFT COUNT 

5 DRIVE NUMBER (0,1) 

J HEAD NUMBER 



CL 

CMD_B LOCK +0,0 

CMD_BL0CK+2,CL 

CMD_BL0CK+3,CH 

CMD_BL0CK+4,AL 

AL,C0NTRPL_BYTE 

CMD_BL0CK+5,AL 

AX 

AL.AH 

AH, AH 

AX,1 

SI, AX 

AX, MIL 

AX 

BAD_C0MMAND 

WORD PTR CS:[SI + OFI 

D I SK_ST ATUS , B AD_CMD 
AL,0 



; ESTABLISH SEGMENT 
5 RETURN STATUS 



; CONVERT DRIVE NUMBER TO BASED RANGE 
; LEGAL DRIVE TEST 



; SECTORS 0-16 FOR CONTT^OLLER 

; SECTOR AND HIGH 2 BITS CYLINDER 

5 CYLINDER 

; INTERLEAVE / BLOCK COUNT 

; CONTROL BYTE (STEP OPTION) 

; SAVE AX 

; GET INTO LOW BYTE 

; ZERO HIGH BYTE 

; *2 FOR TABLE LOOKUP 

; PUT INTO SI FOR BRANCH 

; TEST WITHIN RANGE 

; RESTORE AX 



; COMMAND ERROR 



RESET THE DISK SYSTEM (AH : 



34 Fixed Disk Adapter 



LINE SOURCE 



0338 


688 


DISK_RESET 


PROC NEAR 




0338 E84304 


689 


CALL 


P0RT_1 i 


RESET PORT 


033B EE 


690 


OUT 


DX.AL J 


ISSUE RESET 


033C E83F04 


691 


CALL 


P0RT_1 


CONTROLLER HARDWARE STATUS 


033F EC 


692 


IN 


AL.DX 5 


GET STATUS 


03^0 2402 


693 


AND 


AL,2 ; 


ERROR BIT 


0342 7406 


694 


JZ 


DRl 




0344 C606740005 


695 


MOV 


DISK_STATUS ,BAD_RESET 




0349 C3 


696 


RET 






034 A 


697 


DRl: 






034A E9DA00 


698 


JMP 


INIT_DRV ; 


SET THE DRIVE PARAMETERS 




699 


DISK_RESET 


ENDP 






700 










701 
702 










; DISK 


STATUS ROUTINE (AH = OOIH) 






703 
704 
















034D 


705 


RETURN_STATUS 


PROC NEAR 




034D A07400 


706 


MOV 


AL,DISK_STATUS ; 


OBTAIN PREVIOUS STATUS 


0350 C606740000 


707 


MOV 


DISK_STATUS,0 J 


RESET STATUS 


0355 C3 


708 


RET 








709 


RETURN_STATUS 


ENDP 






710 










711 
712 










; DISK 


READ ROUTINE (AH = 002H) 






713 
714 
















0356 


715 


DISK_READ 


PROC NEAR 




0356 B047 


716 


MOV 


AL,DMA_READ i 


MODE BYTE FOR DMA READ 


0358 C606420008 


717 


MOV 


CMD_BLOCK+0,READ_CMD 




035D E9E501 


718 


JMP 


DMA_OPN 






719 


DISK_READ 


ENDP 






720 










721 


















722 


; DISK 


WRITE ROUTINE (AH = 003H) 






723 


















724 








0360 


725 


DISK_WRITE 


PROC NEAR 




0360 B04B 


726 


MOV 


AL,DMA_WRITE J 


MODE BYTE FOR DMA WRITE 


0362 C60642000A 


727 


MOV 


CMD_B LOCK + , WR ITE_CMD 




0367 E90B01 


728 


JMP 


DMA_OPN 






729 


DISK_WRITE 


ENDP 






730 










731 


















732 


; DISK 


VERIFY (AH = 004H) 






733 


















734 








036A 


735 


DISK.VERF 


PROC NEAR 




036A C606420005 


736 


MOV 


CMD_BLOCK+0 , CHK_TRK_CMD 




036F E9C401 


737 


JMP 


NDMA_OPN 






738 


DISK_VERF 


ENDP 






739 










740 


5 







FORMATTING (AH = 005H 006H 007H) 





743 








0372 


744 


FMT TRK 


PROC 


NEAR 


0372 C606420006 


745 




MOV 


CMD_BLOCK , FMTTRK.CMD 


0377 EBOC 


746 




JMP 


SHORT FMT CONT 




747 


FMT TRK 


ENDP 






748 








0379 


749 


FMT BAD 


PROC 


NEAR 


0379 C606420007 


750 




MOV 


CMD_B LOCK , FMTBAD_CMD 


037E EB05 


751 




JMP 


SHORT FMT_CONT 




752 


FMT_BAD 


ENDP 






753 








0380 


754 


FMT DRV 


PROC 


NEAR 


0380 C606420004 


755 




MOV 


CMD_BLOCK , FMTDRV_CMD 




756 


FMT DRV 


ENDP 






757 








0385 


758 


FMT CONT: 




0385 A04400 


759 




MOV 


AL,CMD_BL0CK+2 


0388 24C0 


760 




AND 


AL.llOOOOOOB 


038A A24400 


761 




MOV 


CMD_BL0CK+2,AL 


038D E9A601 


762 
763 




JMP 


NDMA_OPN 



; FORMAT TRACK (AH = 005H) 



; FORMAT BAD TRACK (AH = 006H) 



FORMAT DRIVE (AH = 007H ) 



; ZERO OUT SECTOR FIELD 



Fixed Disk Adapter 35 



LINE SOURCE 



0390 
0390 

0390 IE 

0391 06 

0392 53 



0395 


8E0a 


0397 


C41E0401 


039B 


68<i000 


0S9E 


8ED8 


03A0 


80EA80 


03A3 


80FA08 


03A6 


732F 


03A8 


E61BFF 


03AB 


E8DF03 


03AE 


7227 


03B0 


03D8 


03B2 


268B07 


03B5 


200200 


03B8 


8AE8 


03BA 


250003 


03BO 


DIES 


03BF 


D1E8 


03C1 


OCll 


03C3 


8AC8 


03C5 


268A7702 


03C9 


FECE 


03CB 8A167500 


03CF 


2BC0 


03D1 




0301 


SB 


0302 


07 


0303 


IF 


0304 


CA0200 


0307 




0307 C6067<*0007 


03lbC 


B407 


03DE 


2AC0 


o3eo 


2B02 


03E2 


2BC9 


03E4 


F9 


03E5 


EBEA 



764 
765 
766 
767 
768 
769 
770 
771 
772 
773 
774 
775 
^76 
777 
778 
779 
780 
781 
782 
783 
784 
785 
786 
787 
788 
789 
790 
791 
792 
793 
794 
795 
796 
797 
798 
799 



802 
803 
804 
805 
806 
807 
608 
809 
810 
811 
812 



815 
816 
817 
818 
819 
820 
821 
822 
823 
824 
825 
826 
827 
828 
829 
830 
831 
832 
833 
834 
835 
836 
837 
838 
839 
840 
841 



GET PARAMETERS (AH = 8) 



GET_PARM^N 

GET^PARM 

PUSH 
PUSH 
PUSH 

ASSUME 

SUB 

MOV 

LES 

ASSUME 

MOV 

MOV 

SUB 
CMP 
JAE 



LABEL 
PROC 



MOV 
SUB 

MOV 
ANO 
SHR 
SHR 



MOV 
DEC 
MOV 
SUB 

POP 
POP 
POP 
RET 

MOV 
MOV 
SUB 
SUB 
SUB 
STC 
JMP 



NEAR 
FAR 



OS: DUMMY 

AX* AX 

OS, AX 

BX,HF_TBL_VEC 

OS -.DATA 

AX, DATA 

OS, AX 

DL,80H 
DL,MAX_FILE 



5 GET DRIVE PARAMETERS 
; SAVE REGISTERS 



; ESTABLISH ADDRESSING 



I ESTABLISH SEGMENT 



; TEST WITHIN RANGE 



SETUP^A 
SW2_0FFS 



AX,ES:[BXI 
AX, 2 

CH,AL 

AX,0300H 

AX,1 

AX, I 

AL,011H 

CL,AL 

DH,ES:[BX][2] 
OH 

DL*HF_NUM 
AX, AX 



DISK_STATUS,INIT_FAIL 

AH,INIT_FAIL 

AL,AL 

DX,OX 

CX,CX 



i MAX NUMBER OF CYLINDERS 

{ ADJUST FOR 0-N 

J AND RESERVE LAST TRACK 

; HIGH TWO BITS OF CYL 



i HEADS 

{ 0-N RANGE 

; DRIVE COUNT 



; RESTORE REGISTERS 



! OPERATION FAILED 



5 SET ERROR FLAG 



; INITIALIZE DRIVE CHARACTERISTICS 



FIXED DISK PARAMETER TABLE 



THE TABLE IS COMPOSED OF A BLOCK DEFINED AS: 



(1 WORD) 
tl BYTE) 
(1 WORD) 
(1 WORD) 
(1 BYTE) 
(1 BYTE) 



(1 BYTE) 
(1 BYTE) 
(1 BYTE) 
(4 BYTES 



- MAXIMUM NUMBER OF CYLINDERS 

- MAXIMUM NUMBER OF HEADS 

- STARTING REDUCED WRITE CURRENT CYL 

- STARTING WRITE PRECOMPENSATION CYL 

- MAXIMUM ECC DATA BURST LENGTH 

- CONTROL BYTE (DRIVE STEP OPTION) 

BIT 7 DISABLE DISK-ACCESS RETRIES : 

BIT 6 DISABLE ECC RETRIES 

BITS 5-3 ZERO 

BITS 2-0 DRIVE OPTION 

- STANDARD TIME OUT VALUE (SEE BELOW) 

- TIME OUT VALUE FOR FORMAT DRIVE 

- TIME OUT VALUE FOR CHECK DRIVE 



36 Fixed Disk Adapter 



6^2 

&(*<* 

8<^7 
8^8 
649 
850 



- RESERVED FOR FUTURE USE 

■ TO DYNAMICALLY DEFINE A SET OF PARAMETERS 
BUILD A TABLE OF VALUES AND PLACE THE 
CORRESPONDING VECTOR INTO INTERRUPT 41. 



THE DEFAULT TABLE IS VECTORED IN FOR 
AN INTERRUPT 19H (BOOTSTRAP) 



03E7 3201 
03E9 02 
03EA 3201 
03EC 0000 
03EE OB 
03EF 00 
03F0 OC 
03F1 84 
03F2 28 
03F3 00000000 



852 
853 
854 
855 
656 
857 
858 
859 
860 
661 
862 
863 
864 
865 
866 
867 
668 
869 
870 
871 
872 
873 
874 
875 
876 
877 
878 
879 
880 
881 
882 
683 



887 
888 



ON THE CARD SWITCH SETTINGS 

DRIVE DRIVE 1 



TRANSLATION TABLE 

1/3 : 2/4 : TABLE ENTRY 



OFF 
OFF 



■ DRIVE TYPE 00 

DM 0306D 

DB 02D 

DM 0306D 

DM OOOOD 

DB OBH 

DB OOH 

DB OCH 

DB 0B4H 

DB 028H 

DB 0,0,0,0 

- DRIVE TYPE 01 



5 STANDARD 

! FORMAT DRIVE 

J CHECK DRIVE 



03F7 7701 
03F9 08 
03FA 7701 
03FC 0000 
03FE OB 
03FF 05 

0400 OC 

0401 B4 

0402 28 

0403 00000000 



892 
893 
894 
895 
896 
897 
898 
899 
900 



0375D 

08D 

0375D 

OOOOD 

OBH 

05H 

OCH 

0B4H 

026H 

0,0,0,0 



STANDARD 
FORMAT DRIVE 
CHECK DRIVE 



0407 3201 

0409 06 
040A 8000 
040C 0001 
040E OB 
040F 05 

0410 OC 

0411 B4 

0412 28 

0413 00000000 



0417 3201 
0419 04 



902 
903 
904 
905 
906 
907 
908 
909 
910 
911 
912 
913 
914 
915 
916 
917 
918 



• DRIVE TYPE 02 

DM 0306D 

DB 06D 

DM 01280 

DM 02560 

DB OBH 

DB 05H 

DB OCH 

DB 0B4H 

DB 028H 

DB 0,0,0,0 

• DRIVE TYPE 03 

DM 0306D 

DB 04D 



; STANDARD 

FORMAT DRIVE 
; CHECK DRIVE 



Fixed Disk Adapter 37 



O^IA 3201 

Oi^lC 0000 

OCtlE OB 

0<*1F 05 

0^20 OC 

0^21 Ba 

01^22 2fi 

0423 00000000 



919 
920 
921 
922 
923 
924 
925 
926 
927 
928 
929 
930 



0306D 

OOOOD 

OBH 

05H 

OCH 

0B4H 

028H 

0,0,0,0 



■ DO DRIVE ZERO 



} STANDARD 

; FORMAT DRIVE 

; CHECK DRIVE 



0427 C60642000C 
042C C606430000 
0431 E81000 
0434 720D 



0436 C60642000C 
043B C606430020 
0440 E80100 
0443 
0443 C3 



0444 2AC0 
0446 E81901 
0449 7301 
044B C3 
044C 
044C IE 

044D 2BC0 
044F 8ED8 
0451 C41E0401 

0455 IF 

0456 E83403 
0459 7257 
045B 03D8 



045D BFOIOO 
0460 E85F00 
0463 724D 

0465 BFOOOO 
0468 E85700 
046B 7245 

046D BF0200 
0470 E84F00 
0473 723D 

0475 BF0400 
0478 E84700 
047B 7235 



932 
933 
934 
935 
936 
937 
938 
939 
940 
941 
942 
943 
944 
945 
946 
947 
948 
949 
950 
951 
952 
953 
954 
955 
956 
957 
958 
959 
960 
961 
962 
963 
964 
965 
966 
967 
968 
969 
970 
971 
972 
973 
974 
975 
976 
977 
978 
979 
980 



MOV CMD_BLOCK+0,INIT_DRV_CMD 

MOV CMD_B LOCK +1,0 

CALL INIT_DRV_R 

JC INIT_DRV_OUT 

■ DO DRIVE ONE 



MOV 
MOV 
CALL 

INIT_DRV_OUT: 
RET 

INIT_DRV 

INIT_DRV_R 

ASSUME 

SUB 

CALL 

JNC 

RET 

Bl: 

PUSH 

ASSUME 

SUB 

MOV 

LES 

POP 

ASSUME 

CALL 

JC 



CMD_BLOCK+0 , INIT_DRV_CMD 
CMD_BL0CK+1 ,001000006 
INIT_DRV R 



PROC NEAR 
ES:CODE 
AL.AL 
COMMAND 



Bl 



DS 

DS:DUmr 

AX, AX 

DS.AX 

BX,HF_TBL_VEC 

DS 

DS:DATA 

SW2_0FFS 



ISSUE THE COMMAND 



; SAVE SEGMENT 



ESTABLISH SEGMENT 



; RESTORE SEGMENT 



■ SEND DRIVE PARAMETERS MOST SIGNIFICAffT BYTE FIRST 



MOV DI,1 

CALL INIT_DRV_S 



MOV 
CALL 



MOV 
CALL 



MOV 
CALL 



INIT_DRV_S 



DI,2 
INIT_DRV S 



DI,4 
1NIT_DRV_S 



047D BF0300 
0480 E83F00 
0483 722D 

0485 BF0600 
0488 E83700 
048B 7225 

048D BF0500 
0490 E82F00 
0493 721D 

0495 BF0700 
0498 E82700 



982 
983 



989 
990 
991 
992 
993 
994 
995 



MOV 
CALL 


DI,3 
INIT_DRV_S 


JC 


B3 


MOV 


DI,6 


CALL 


INIT_DRV_S 



MOV 


DI,5 


CALL 


INIT_DRV_S 


JC 


B3 


MOV 


DI,7 


CALL 


INIT_ORV_S 



38 Fixed Disk Adapter 



049B 7215 

0<i9D BF0800 
04A0 268A01 
04A3 A27600 

0^A6 2BC9 

0^A8 E8D302 

O^AB EC 

04AC A802 

04AE 7509 

O'+BO E2F6 

0'iB2 

0^B2 C6067^0007 

O'iB? F9 

0^B8 C3 

o-^Bg 

0^B9 E8B502 
O^BC EC 
0<^BD 2402 
O'tBF 75F1 
04C1 C3 



04C2 

04C2 E6C501 
04C5 7207 
04C7 E8A702 
04CA 268A01 
04CD EE 
0<^CE 
0<»CE C3 



O-iCF 

04CF E81900 

04D2 726B 

04D4 C6064200E5 

0'iD9 B0'+7 

0<iDB EB68 



0<^DD 

04DD E80B00 

04E0 725D 

04E2 C6064200E6 

04E7 B04B 

04E9 EB5A 



04EB 

04EB A04600 
04EE 3C80 
O'+FO F5 
04F1 C3 



04F2 

04F2 C60642000B 

O-^F? EB3D 



996 
997 
998 
999 

loco 

1001 
1002 
1003 
1004 
1005 
1006 
1007 
1008 
1009 
1010 
1011 
1012 
1013 
1014 
1015 
10i6 
1017 
1018 
1019 
1020 
1021 
1022 
1023 
1024 
1025 
1026 
1027 
1028 
1029 
1030 
1031 
1032 
1033 
1034 
1035 
1036 
1037 
1038 
1039 
1040 
1041 
1042 
1043 
1044 
1045 
1046 
1047 
1048 
1049 
1050 
1051 
1052 
1053 
1054 
1055 
1056 
1057 
1058 
1059 
1060 
1061 
1062 
1063 
1064 
1065 
1066 
1067 
1068 
1069 
1070 
1071 
1072 



MOV 


DI,8 


MdV 


AL,ES:[BX ♦ DI I 


MOV 


CONTR0L_BYTE,AL 



CALL 


PORT 1 


IN 


AL.DX 


TEST 


AL,R1_IOMOOE 


JNZ 


B6 


LOOP 


B5 


MOV 


DISK_STATUS, 


STC 




RET 





; DRIVE STEP OPTION 



; STATUS INPUT MODE 



IN 
AND 
JNZ 
RET 
ASSUME 
INIT_DRV_R 



PORT_0 
AL.DX 
AL,2 



ES: NOTHING 
ENDP 



; MASK ERROR BIT 



SEND THE BYTE OUT TO THE CONTROLLER 



INIT_DRV_S 

CALL 

JC 

CALL 

MOV 

OUT 

Dl: 

RET 

INIT_DRV_S 



PROC NEAR 

HO_WAIT_REq 

Dl 

PORT_0 

AL,ES:[BX + DI) 

DX.AL 



READ LONG (AH = OAH ) 



MOV 
MOV 
JMP 



PROC NEAR 

CHK_LONG 

G8 

CMD_BLOCK+0,RD_LONG_CMD 

AL,DMA_READ 

SHORT DMA_OPN 

ENDP 



WRITE LONG (AH : 



MOV 
MOV 
JMP 



MOV 
CMP 
CMC 
RET 



PROC NEAR 

CHK_LONG 

G8 

CMD_BLOCK+0 ,WR_LONG_CMD 

AL,DMA_ WRITE 

SHORT DMA_OPN 

ENDP 

PROC NEAR 

AL,CMD_BL0CK+4 

AL,080H 



SEEK (AH = OCH) 



DISK_SEEK 

MOV 
JMP 



PROC NEAR 
CMD_BLOCK,SEEK_CMD 
SHORT NDMA_OPN 



Fixed Disk Adapter 39 



0«iF9 

0<+FE C606^60001 
0503 BB<*7 
0505 EB3E 



1073 
107"^ 
1075 
1076 
1077 
1078 
1G79 
1080 
1081 
1082 
1083 
108^ 
1085 
1086 
1087 



READ SECTOR BUFFER (AH = OEH) 



RD_BUFF PROC NEAR 

MOV CMD^BLOCK+0,RD_BUFF_CMD 

MOV CMD_BL0CK+^,1 ( ONLY ONE BLOCK 

MOV AL,DMA_READ 

JMP SHORT DMA_OPN 
RO_BUFF ENDP 



WRITE SECTOR BUFFER (AH = OFH) 



0507 

0507 C60642OO0F 
O50C C606<^60001 
0511 B04B 
0513 E830 



0515 

0515 C606<»20O8O 

051A EBIA 



051C 

051C C606<»20001 

0521 EB13 



0523 

0523 C606f4200EO 

0528 EBOC 



052A 

052A C606<»200E3 

052F EB05 



0531 

0531 C6O6':»2O0E'i 



0536 

0536 B002 
0538 E82700 
053B 7221 
053D EB16 



1089 
1090 
1091 
1092 
1093 
1094 
1095 
1096 
1097 
1098 
1099 
1100 
1101 
1102 
1103 
1104 
1105 
1106 
1107 
1108 
1109 
1110 

nil 

1112 
1113 
1114 
1115 
1116 
1117 
1118 
1119 
1120 
1121 
1122 
1123 
1124 
1125 
1126 
1127 
1128 
1129 
1130 
1131 
1132 
1133 
1134 
1135 
1136 
1137 
1138 
1139 
1140 
1141 
1142 
1143 
1144 
1145 
1146 
1147 
1148 
1149 



WR_BUFF PROC NEAR 

MOV CMD_BL0CK+O,WR_BUFF_CMD 

MOV eMD_BL0CK+4,l j ONLY ONE BLOCK 

MOV AL,DMA_WRITE 

JMP SHORT DMA_OPN 
MR_BUFF ENDP 



TEST DISK READY (AH = OlOH) 



TST_RDY PROC NEAR 

MOV CMD_BLOCK+0,TST_RDY_CMD 

JMP SHORT NDMA_OPN 

TST_RDY ENDP 



RECALIBRATE (AH = 01 IH) 



HDISK_RECAL PROC NEAR 

MOV CMD_BLOCK,RECAL_CMD 

JMP SHORT NDMA_OPN 

HDISK_RECAL ENDP 



CONTROLLER RAM DIAGNOSTICS (AH = 012H) 



RAM_DIAG PROC NEAR 

MOV CMD_BLOCK+0,RAM_DIAG_CMD 

JMP SHORT NDMA_OPN 

RAM_DIAG ENDP 



DRIVE DIAGNOSTICS (AH = 013H) 



CHK_DRV PROC NEAR 

MOV CMD^BLOCK+0,CHK_DRV_CMD 

JMP SHORT NDMA_OPN 

CHK DRV ENDP 



CONTROLLER INTERNAL DIAGNOSTICS (AH = 014H) 



CNTLR_DIAG PROC NEAR 

MOV CMD_BLOCK+0,CNTLR_DIAG_CMD 

CNTLR DIAG ENDP 



SUPPORT ROUTINES 



MOV AL,02H 

CALL COMMAND 

JC GU 

JMP SHORT G3 



5 ISSUE THE COMMAND 



40 Fixed Disk Adapter 



053F 




053F 


C6067'i0009 


054^ 


C3 


05« 




05^5 


E85701 


05^8 


72F5 


05<^A 


B003 


OS-^C 


E81300 


05^F 


720D 


0551 


B003 


0553 


E60A 


0555 




0555 


E^21 


0557 


24DF 


0559 


E621 


055B 


E8AA01 


055E 




055E 


E83B00 


0561 


C3 



1150 

1151 
1152 
1153 
115^ 
1155 
1156 
1157 
1158 
1159 
1160 
1161 
1162 
1163 
116^ 
1165 
1166 
1167 
1168 
1169 
1170 
1171 
1172 
1173 
117^ 
1175 



MOV 
RET 



MOV 
CALL 



MOV 
OUT 



AUD 
OUT 
CALL 

CALL 
RET 



DISK_STATUS,DMA_BOUNDARY 



DMA_SETUP 

G8 

AL,03H 

COMMAND 

Gil 

AL,03H 

DMA+10,AL 

AL.OZIH 
AL.ODFH 
021H,AL 
WA1T_IMT 

ERROR_CHK 



SET UP FOR DMA OPERATION 



ISSUE THE COMMAND 



INITIALIZE THE DISK CHANNEL 



; COMMAND 

THIS ROUTINE OUTPUTS THE COMMAND BLOCK 
; INPUT 

AL = CONTROLLER DMA/INTERRUPT REGISTER MASK 



0562 


BE'»200 


0565 


E81B02 


0568 


EE 


0569 


E81C02 


056C 


EE 


056D 


2BC9 


056F 


E80C02 


0572 




0572 


EC 


0573 


2^0F 


0575 


3C0D 


0577 


7^09 


0579 


E2F7 


057B 


C6067^0080 


0580 


F9 


0581 


C3 


0582 




0582 


FC 


0583 


B90600 


0586 




0586 


E8E801 


0589 


AC 


058A 


EE 


056B 


E2F9 


058D 


E8EE01 


0590 


EC 


0591 


A801 


0593 


7^06 


0595 


C6067<+0020 


059A 


F9 


059B 




059B 


C3 



1177 
1178 
1179 
1180 
1181 
1182 
1183 
118"^ 
1185 
1186 
1187 
1188 
1189 
1190 
1191 
1192 
1193 
119^ 
1195 
1196 
1197 
1198 
1199 
1200 
1201 
1202 
1203 
1204 
1205 
1206 
1207 
1208 
1209 
1210 
1211 
1212 
1213 
1214 
1215 
1216 
1217 
1218 
1219 
1220 
1221 
1222 
1223 
1224 
1225 
1226 



COMMAf-ID PROC 
MOV 
CALL 
OUT 
CALL 
OUT 
SUB 
CALL 

WAIT_BUSY: 
IN 
AND 
CMP 
JE 

LOOP 
MOV 
STC 
RET 

Cl: 

CLD 
MOV 

CM3: 

CALL 
LODSB 
OUT 
LOOP 



JZ 
MOV 
STC 

CM7: 

RET 

COMMAND ENDP 



NEAR 

SI, OFFSET CMD_BLOCK 

P0RT_2 

DX.AL 

P0RT_3 

DX.AL 

CX.CX 

P0RT_1 



CONTROLLER SELECT PULSE 



WAIT COUNT 



AL.DX ; GET SI 

AL.OFH 

AL,R1_BUSY OR R1_BUS OR Rl_REq 

Cl 

WAIT_BUSY 

DISK_STATUS,TIME_OUT 



ERROR RETURN 



i BYTE COUNT 



DX.AL 
CM3 

P0RT_1 

AL.DX 

AL,Rl_REq 

CM7 

DISK_STATUS,BAD_CNTLR 



; GET THE NEXT COMMAND BYTE 
1 OUT IT GOES 
; DO MORE 



SENSE STATUS BYTES 



BIT 7 ADDRESS VALID, WHEN SET 

BIT 6 SPARE, SET TO ZERO 

BITS 5-4 ERROR TYPE 

BITS 3-0 ERROR CODE 



BITS 7-6 ZERO 

BIT 5 DRIVE (0-1) 

BITS 4-0 HEAD NUMBER 



Fixed Disk Adapter 41 



059C A07400 
059F OACO 
05A1 7501 
05A3 C3 



OSA-i 

05A4 B84000 

05A7 8EC0 

05A9 2BC0 

05AB 6BF8 

05AD C606^20003 

05B2 2AC0 

05B4 E8ABFF 

05B7 7223 

05B9 B90<«00 

05BC 

05BC E8CB00 

05BF 7220 

05C1 E6AD01 

OSCt EC 

05C5 2688^5^2 

05C9 ^7 

05CA E8B101 

05CD E2ED 

05CF E8B800 

05D2 720D 

050"^ E69A01 

05D7 EC 

05D8 A802 

05DA 7'40F 

05DC 

05DC C6067400FF 

05E1 

05E1 F9 

05E2 C3 



05E3 1A06 
05E5 2706 
05E7 6A06 
05E9 7706 

05EB 

05EB 268A1E^200 
05F0 8AC3 
05F2 240F 
05F<» 80E330 
05F7 2AFF 
05F9 B103 
05FB D3EB 
05FD 2EFFA7E305 



0602 

0602 0020^020800020 

0609 OOi+O 
0009 

060B 

060B 1010020004 

0610 'tOOOOOllOB 
OOOA 

0615 
0615 0102 



1227 
1228 
1229 
1230 
1231 
1232 
1233 
1234 
1235 
1236 
1237 
1238 
1239 
12'+0 
1241 
1242 
1243 
1244 
1245 
1246 
1247 
1248 
1249 
1250 
1251 
1252 
1253 
1254 
1255 
1256 
1257 
1258 
1259 
1260 
1261 
1262 
1263 
1264 
1265 
i266 
1267 
1268 
1269 
1270 
1271 
1272 
1273 
1274 
1275 
1276 
1277 
1278 
1279 
1280 
1281 
1282 
1283 
1284 
1285 
1286 
1287 
1288 
1289 
1290 
1291 
1292 
1293 
1294 
1295 
1296 
1297 
1298 
1299 
1300 
1301 
1302 
1303 



BITS 7-5 CYLINDER HIGH 
BITS 4-0 SECTOR NUMBER 



BITS 7-0 CYLINDER LOW 



ERROR_CHK 

ASSUME 

MOV 

OR 

JN2 

RET 



PROC NEAR 

ES:DATA 

AL,DISK_STATUS 

AL.AL 

G21 



; CHECK IF THERE WAS AN ERROR 



• PERFORM SENSE STATUS 



MOV 
MOV 
SUB 
MOV 
MOV 
SUB 
CALL 
JC 



CALL 
LOOP 
CALL 



JZ 



SENSE_ABORT: 
MOV 

G24: 

STC 
RET 

ERROR_CHK 



T_2 DW 

T_3 DW 

STAT_ERR : 

MOV 
MOV 
AND 
AND 
SUB 
MOV 
SHR 
JMP 



AX, DATA 

ES.AX 

AX, AX 

DI,AX 

CMD_B LOCK+ , SENSE_CMD 

AL.AL 

COMMAND 

SENSE_ABORT 

CX,4 

HD_WAIT_REq 

G24 

PORT_0 

AL.DX 

ES:HD_ERR0RIDI1,AL 

DI 

P0RT_1 

G22 

HD_WAIT_REq 

G24 

PORT_0 

AL,DX 

AL,2 

STAT_ERR 

DISK_STATUS,SENSE_FAIL 



TYPE_0 
TYPE_1 
TYPE_2 
TYPE_3 



; ESTABLISH SEGMENT 



ISSUE SENSE STATUS COMMAND 
CANNOT RECOVER 



; STORE AWAY SENSE BYTES 



BL,ES:HD_ERROR 

ALiBL 

AL.OFH 

BL.OOnOOOOB 

BH,BH 

CL,3 

BX.CL 

WORD PTR CS:IBX ■ 



GET ERROR BYTE 



ISOLATE TYPE 



; ADJUST 
OFFSET T_0 1 



ASSUME ES: NOTHING 



TYPEO_TABLE 



TYPEO_LEN 
TYPE1_TABLE 



TYPE1_LEN 
TYPE2_TABLE 



LABEL BYTE 

0,BAD_CNTLR,BAD_SEEK,BAD_CNTLR,TIME_OUT,0,BAD_CNTLR 

0,BAD_SEEK 

EQU $-TYPE0_TABLE 

LABEL BYTE 

BAD_ECC , BAD_ECC , BAD_ADDR_MARK , , RECORD_NOT_FND 

BAD_SEEK,0,0,DATA_CORRECTED,BAD_TRACK 

EQU $-TYPEl_TABLE 

LABEL BYTE 

BAD_CMD ,BAD_ADDR_MARK 



42 Fixed Disk Adapter 



LINE SOURCE 



0002 
0617 
0617 202010 

0003 



061A 

061A BB0206 
061D 3C09 
061F 7363 
0621 2ED7 
0623 A27'i00 
0626 C3 



0627 

0627 BB0B06 
062A 8BC8 
062C 3C0A 
062E 735^ 
0630 2ED7 
0632 A27400 
0635 60E108 
0638 80F908 
063B 752A 



06 3D 


C60642000D 


0642 


2AC0 


0644 


E81BFF 


0647 


721E 


0649 


E83E00 


064C 


7219 


064E 


E82001 


0651 


EC 


0652 


SACS 


0654 


E83300 


0657 


720E 


0659 


E81501 


065C 


EC 


065D 


A801 


065F 


7406 


0661 


C606740020 


0666 


F9 


0667 




0667 


8AC1 


0669 


C3 



066A 

066A BB1506 
066D 3C02 
066F 7313 
0671 2ED7 
0673 A27400 
0676 C3 



0677 




0677 


BB1706 


067A 


3C03 


067C 


7306 


067E 


2ED7 


0680 


A27400 


0683 


C3 


0684 




0684 


C6067400BB 


0689 


C3 


068A 




068A 


51 



1304 
1305 
1306 
1307 
1308 
1309 
1310 
1311 
1312 
1313 
1314 
1315 
1316 
1317 
1318 
1319 
1320 
1321 
1322 
1323 
1324 
1325 
1326 
1327 
1328 
1329 
1330 
1331 
1332 
1333 
1334 
1335 
1336 
1337 
1338 
1339 
1340 
1341 
1342 
1343 
1344 
1345 
1346 
1347 
1348 
1349 
1350 
1351 
1352 
1353 
1354 
1355 
1356 
1357 
1358 
1359 
1360 
1361 
1362 
1363 
1364 
1365 
1366 
1367 
1368 
1369 
1370 
1371 
1372 
1373 
1374 
1375 
1376 
1377 
1378 
1379 
1380 



TYPE2_LEN EQU $-TYPE2_TABLE 

TYPE3_TABLE LABEL BYTE 

DB BAD_CNT LR , B AD_CNT LR , BAD_ECC 

TYPE3_LEN EQU $-TYPE3 TABLE 



TYPE ERROR 



MOV 
CMP 
JAE 
XL AT 
MOV 
RET 



BX, OFFSET TYPEO_TABLE 

AL,TYPEO_LEN 

UNDEF_ERR_L 

C5:TYPE0_TABLE 

DISK_STATUS,AL 



• TYPE 1 ERROR 



MOV 
MOV 
CMP 
JAE 
XLAT 
MOV 
AND 
CMP 
JNZ 



BX, OFFSET TYPE1_TABLE 

CX.AX 

AL,TYPE1_LEN 

UNDEF_ERR_L 

CS:TYPE1_TABLE 

DISK_STATUS,AL 

CL,08H 

CL,08H 

G30 



; CHECK IF ERROR IS DEFINED 



; TABLE LOOKUP 
1 SET ERROR CODE 



CHECK IF ERROR IS DEFINED 

TABLE LOOKUP 
SET ERROR CODE 
CORRECTED ECC 



• OBTAIN ECC ERROR BURST LENGTH 



MOV 
SUB 
CALL 



MOV 
CALL 



MOV 
STC 



MOV 
RET 



CMD_BLOCK+0 ,RD_ECC_CMD 

AL.AL 

COMMAND 

G30 

HD_WAIT_REQ 

G30 

PORT 

AL.DX 

CL.AL 

HD_WAIT_REQ 

G30 

PORT_0 

AL.DX 

AL.OIH 

G30 

DISK_STATUS,BAD_CNTLR 



■ TYPE 2 ERROR 



MOV 
CMP 
JAE 
XLAT 
MOV 
RET 



BX, OFFSET TYPE2_TABLE 

AL,TYPE2_LEN 

UNDEF_ERR_L 

CS: TYPE 1_T ABLE 

DISK_STATUS,AL 



CHECK IF ERROR IS DEFINED 



! TABLE LOOKUP 
i SET ERROR CODE 



TYPE 3 ERROR 



MOV 
CMP 
JAE 
XLAT 
MOV 
RET 

UNDEF_ERR_L! 
MOV 
RET 

HD_WAIT_REQ 
PUSH 



BX, OFFSET TYPE3_TABLE 

AL,TYPE3_LEN 

UNDEF_ERR_L 

CS;TYPE3_TABLE 

DISK_STATUS,AL 



DISK STATUS, UNDEF ERR 



Fixed Disk Adapter 43 



0683 2BC9 
068D E8EE00 
0690 

0690 EC 

0691 A801 
0693 7508 
0695 E2F9 

0697 C606740080 
069C F9 
06 90 
069D 59 
069E C3 



069F 
069F 50 
06A0 A0<^600 
06A3 3C81 
06A5 58 
06A6 7202 
06 Ad F9 
06A9 C3 
06AA 
06AA 51 
06AB FA 
06AC E60C 
06AE 50 
06AF 58 
06B0 E60B 

06B2 ecco 

06B<» BIO^ 
06B6 D3C0 
06B8 8AE8 
06BA 24F0 
06BC 03C3 
06BE 7302 
06C0 FEC5 
06C2 
06C2 50 
06C3 E606 
06C5 8AC<f 
06C7 E606 
06C9 8AC5 
06CB 2^0F 
06CD E682 



06CF A04600 
06D2 DOEO 
06D<+ FEC8 
06D6 8AE0 
06D8 BOFF 



06DA 50 
06DB A0<i200 
06DE 3CE5 
06E0 7'>07 
06E2 3CE6 
06E'* 7'i03 
06E6 58 
06E7 EBll 
06E9 
06E9 58 
06EA B80^02 
06ED 53 



1381 
1382 
1383 
138"* 
1385 
1386 
1387 
1388 
1389 
1390 
1391 
1392 
1393 
139-* 
1395 
1396 
1397 
1398 
1399 
l^iOO 
1401 
1<*02 
1403 
1404 
1405 
1406 
1407 
1408 
1409 
1410 
1411 
1412 
1413 
1414 
1415 
1416 
1417 
1418 
1419 
1420 
1421 
1422 
1423 
1424 
1425 
1426 
1427 
1428 
1429 
1430 
1431 
1432 
1433 
1434 
1435 
1436 
1437 
1438 
1439 
1440 
1441 
1442 
1443 
1444 
1445 
1446 
1447 
1448 
1449 
1450 
1451 
1452 
1453 
1454 
1455 
1456 
1457 



CX.CX 
PORT_l 



AL,DX 
AL,R1_REQ 



DISK_STATUS,TIME OUT 



SUB 

CALL 
Ll: 

IN 

TEST 

JNZ 

LOOP 

MOV 

STC 
L2: 

POP CX 

RET 
HD_WAIT_REQ ENDP 

5 _ 

; DMA.SETUP 

; THIS ROUTINE SETS UP FOR DMA OPERATIONS. 

} INPUT 

; (AD = MODE BYTE FOR THE DMA 

; (ES:BX) = ADDRESS TO READ/WRITE THE DATA 

; OUTPUT 

J (AX) DESTROYED 



DMA^SETUP 

PUSH 

MOV 

CMP 

POP 

JB 

STC 

RET 

Jl: 

PUSH 
CLI 
OUT 
PUSH 
POP 
OUT 
MOV 
MOV 
ROL 
MOV 
AND 
ADD 
JNC 
INC 

J33: 

PUSH 
OUT 
MOV 
OUT 
MOV 
AND 
OUT 



AL,CMD_BL0CK+4 
AL,81H 



AX 

DMA+U.AL 

AX.ES 

CL,4 

AX,CL 

CH.AL 

AL.OFOH 

AX.BX 

J33 

CH 

AX 

DMA+6,AL 

AL>AH 

DMA+6.AL 

AL.CH 

AL,OFH 

DMA_HIGH,AL 



DETERMINE COUNT 



AL,CMD_BL0CK+4 
AL,1 



MOV 

SHL 

DEC AL 

MOV AH.AL 

MOV AL.OFFH 



• HANDLE READ AND WRITE LONG (516D BYTE BLOCKS) 



; BLOCK COUNT OUT OF RANGE 



; SAVE THE REGISTER 
; NO MORE INTERRUPTS 
! SET THE FIRST/LAST F/F 



i OUTPUT THE MODE BYTE 

i GET THE ES VALUE 

{ SHIFT COUNT 

; ROTATE LEFT 

; GET HIGHEST NYBBLE OF ES TO CH 

; ZERO THE LOW NYBBLE FROM SEGMENT 

; TEST FOR CARRY FROM ADDITION 

; CARRY MEANS HIGH 4 BITS MUST BE INC 

5 SAVE START ADDRESS 
{ OUTPUT LOW ADDRESS 

; OUTPUT HIGH ADDRESS 
i GET HIGH 4 BITS 

; OUTPUT THE HIGH 4 BITS TO PAGE REG 



; RECOVER BLOCK COUNT 

I MULTIPLY BY 512 BYTES PER SECTOR 

; AND DECREMENT VALUE BY ONE 



PUSH 
MOV 
CMP 



POP 
JMP 

POP 
MOV 
PUSH 



AX 

AL,CMD_BLOCK+0 

AL.RO_LONG_CMD 

ADD4 

AL,WR_LONG_CMD 

ADD4 

AX 

SHORT J20 



5 SAVE REGISTER 
} GET COMMAhffi 



; RESTORE REGISTER 



; RESTORE REGISTER 

J ONE BLOCK (512) PLUS 4 BYTES ECC 



44 Fixed Disk Adapter 



06EE 2AFF 
06F0 8AIE^600 
06F'^ 52 
06F5 F7E3 
06F7 5A 
06F8 5B 
06F9 <iQ 
06FA 

06FA 50 
06FB E607 
06FO 8AC^ 
06FF E607 

0701 FB 

0702 59 

0703 58 
070^ 03C1 

0706 59 

0707 C3 



0708 




0708 


FB 


0709 


53 


070A 


51 


070B 


06 


070C 


56 


070D 


IE 


070E 


2BC0 


0710 


8ED8 


0712 


C<i360<i01 


0716 


IF 



0717 2AFF 
0719 268A5C09 
071D 8A26«00 
0721 80FC0* 
072^ 7506 
0726 268A5C0A 
072A EB09 
072C 60FCE3 
072F 750<t 
0731 268A5C0B 
0735 
0735 2BC9 



0737 




0737 


E84400 


073A 


EC 


073B 


2420 


073D 


3C20 


073F 


7<iOA 


07^1 


EZf<* 


07^3 


4B 


074<:» 


75F1 


07<i6 


C6067<t0080 


074B 




07'+B 


E82300 


07<:>E 


EC 


07^F 


2402 


0751 


08067400 


0755 


E83000 


0758 


32C0 


075A 


EE 


075B 


5E 



1458 
1459 
1460 
1461 
1462 
1463 
1464 
1465 
1466 
1467 
1468 
1469 
1470 
1471 
1472 
1473 
1474 
1475 
1476 
1477 
1478 
1479 
1480 
1461 
1482 
1483 
1484 
1485 
1486 
1487 
1488 
1489 
1490 
1491 
1492 
1493 
1494 
1495 
1496 
1497 
1490 
1499 
1500 
1501 
1502 
1503 
1504 
1505 
1506 
1507 
1508 
1509 
1510 
1511 
1512 
1513 
1514 
1515 
1516 
1517 
1518 
1519 
1520 
1521 
1522 
1523 
1524 
1525 
1526 
1527 
1528 
1529 
1530 
1531 
1532 
1533 
1534 



SUB 


BH.BH 


MOV 


BL,CMD_BL0CK+4 


PUSH 


DX 


riUL 


BX 


POP 


DX 


POP 


BX 


DEC 


AX 



PUSH 
OUT 
MOV 
OUT 
STI 
POP 
POP 
ADD 
POP 
RET 
DMA_SETUP 



DMA+7,AL 

AL.AH 

DMA+7,AL 



5 BLOCK COUNT TIMES 516 



! SAVE COUNT VALUE 
5 LOW BYTE OF COUNT 

; HIGH BYTE OF COUNT 
i INTERRUPTS BACK ON 
! RECOVER COUNT VALUE 
; RECOVER ADDRESS VALUE 
; ADD, TEST FOR 64K OVERFLOW 
i RECOVER REGISTER 
i RETURN TO CALLER, CFL SET BY ABOVE IF ERROR 



WAIT_INT 

THIS ROUTINE WAITS FOR THE FIXED DISK 
CONTROLLER TO SIGNAL THAT AN INTERRUPT 
HAS OCCURRED. 



STI 

PUSH 

PUSH 

PUSH 

PUSH 

PUSH 

ASSUME 

SUB 

MOV 

LES 

ASSUME 

POP 



DS 

DS: DUMMY 

AX, AX 

DS.AX 

SI,HF_TBL_VEC 

DS:DATA 

DS 



TURN ON INTERRUPTS 
PRESERVE REGISTERS 



ESTABLISH SEGMENT 



SET TI 

SUB 


1E0UT VALUES 
BH,BH 


MOV 


BL,BYTE PTR ES:tSlH91 


MOV 


AH,CM0_BL0CK 


CMP 


AH,FMTDRV_CMD 


JNZ 


W5 


MOV 


BL.BYTE PTR ES:[SI][0AH1 


JMP 


SHORT W4 


45: CMP 


AH,CHK_DRV_CMD 


JNZ 


W4 


MOV 


BL.BYTE PTR ES;[SI]10BH] 


SUB 
WAIT F( 


CX.CX 
)R INTERRUPT 



STANDARD TIME OUT 



FORMAT DRIVE 



5 CHECK DRIVE 



CALL 


P0RT_1 






IN 


AL.DX 






AND 


AL,020H 






CMP 


AL,020H 




; DID INTERRUPT OCCUR 


JZ 


W2 






LOOP 


Wl 




; INNER LOOP 


DEC 


BX 






JNZ 


Wl 




; OUTER LOOP 


MOV 


DISK.STATUS 


TIME_OUT 




CALL 


PORT_0 






IN 


AL,DX 






AND 


AL,2 




; ERROR BIT 


OR 


DISK_STATUS 


AL 


; SAVE 


CALL 


P0RT_3 




; INTERRUPT MASK REGISTER 


XOR 


AL.AL 




; ZERO 


OUT 


DX.AL 




; RESET MASK 


POP 


SI 




; RESTORE REGISTERS 



Fixed Disk Adapter 45 



LINE SOURCE 



075C 07 
075D 59 
075E 5B 
075F C3 



0760 

0760 50 

0761 BOZO 
0763 E6E0 
0765 B007 
0767 E60A 

0769 E^21 
076B 0C20 
076D E621 
076F 58 

0770 CF 



0771 

0771 BA2003 
077^ 50 
0775 ZAE-^f 
0777 A07700 
077A 03D0 
077C 58 
077D C3 



077E 

077E E8F0FF 

0781 '♦2 

0782 C3 



0783 

0763 E8F8FF 

0786 42 

0787 C3 



0788 

0788 E8F8FF 
076B 42 
078C C3 



078D 

078D E8F3FF 

0790 EC 

0791 50 

0792 E8E9FF 

0795 EC 

0796 2402 

0798 58 

0799 7516 
079B 8A264300 
079F 80E420 
07A2 7504 
07A4 D0E8 
07A6 D0E8 
07A8 

07A8 2403 
07AA B104 



1535 
1536 
1537 
1538 
1539 
1540 
1541 
1542 
1543 
1544 
1545 
1546 
1547 
1548 
1549 
1550 
1551 
1552 
1553 
1554 
1555 
1556 
1557 
1558 
1559 
1560 
1561 
1562 
1563 
1564 
1565 
1566 
1567 
1568 
1569 
1570 
1571 
1572 
1573 
1574 
1575 
1576 
1577 
1578 
1579 
1580 
1581 
1582 
1583 
15S4 
1585 
1586 
1587 
1588 
1589 
1590 
1591 
1592 
1593 
1594 
1595 
1596 
1597 
1598 
1599 
1600 
1601 
1602 
1603 
1604 
1605 
1606 
1607 
1608 
1609 
1610 
1611 



POP 
POP 
POP 
RET 



PROC 

PUSH 

MOV 

OUT 

MOV 

OUT 

IN 

OR 

OUT 

POP 

IRET 

ENDP 



AX 

AL.EOI 

INT_CTL_PORT,AL 

AL,07H 

DMA+10,AL 

AL,021H 

AL,020H 

021H,AL 

AX 



} END OF INTERRUPT 



; SET DMA MODE TO DISABLE 



GENERATE PROPER PORT VALUE 
BASED ON THE PORT OFFSET 



PROC 
MOV 
PUSH 
SUB 
MOV 
ADD 
POP 
RET 
ENDP 

PROC 
CALL 
INC 
RET 
ENDP 

PROC 
CALL 



NEAR 

DX,HF_PORT 

AX 

AH, AH 

AL,PORT_OFF 

DX.AX 



NEAR 
PORT_0 



I BASE VALUE 



ADD IN THE OFFSET 



NEAR 
P0RT_1 



RET 
P0RT_2 ENDP 

P0RT_3 PROC NEAR 

CALL P0RT_2 
INC DX 
RET 

P0RT_3 ENDP 



INCREMENT TO PORT ONE 



INCREMENT TO PORT TWO 



INCREMENT TO PORT THREE 



SW2_0FFS 

DETERMINE PARAMETER TABLE OFFSET 
USING CONTROLLER PORT TWO AND 
DRIVE NUMBER SPECIFIER (0-1) 



PUSH 
CALL 
IN 
AND 
POP 
JNZ 
MOV 
AND 
JNZ 
SHR 
SHR 
): 
AND 
MOV 



PROC NEAR 

P0RT_2 

AL,DX 

AX 

P0RT_1 

AL.DX 

AL,2 

AX 

SW2_0FFS_ERR 

AH,CMD_BL0CK+1 

AH.OOIOOOOOB 

SW2_AND 

AL.l 

AL,1 

AL.OllB 
CL,4 



READ PORT 2 



1 CHECK FOR ERROR 



; DRIVE OR 1 
; ADJUST 



46 Fixed Disk Adapter 



07AC D2E0 

07AE 2AE^ 

07B0 C3 
07B1 

07B1 F9 

07B2 C3 



07B3 30382F31362F38 



LINE 


SOURCE 






1612 


SHL 


AL.CL 


; ADJUST 


1613 


SUB 


AH, AH 




161^ 


RET 






1615 


SW2_0FFS_ERR: 






1616 


STC 






1617 


RET 






1618 


SW2_0FFS 


ENOP 




1619 








1620 


DB 


•08/16/82' 


; RELEASE MARKER 


1621 








1622 


END_ADDRESS 


LABEL BYTE 




1623 


CODE ENDS 






162^ 


END 







Fixed Disk Adapter 47 



Notes: 



48 Fixed Disk Adapter 



Personal Computer 
Hardware Reference 
Library 



Fixed Disk and Diskette 
Drive Adapter 



Contents 



Description 1 

Fixed Disk Function 1 

Task File 2 

Task File Registers 2 

Miscellaneous Information 11 

Diskette Function 11 

Diskette Controller 14 

Diskette Controller Commands 16 

Controller Commands 20 

Command Status Registers 32 

Interfaces 36 

Interface Lines 37 

Logic Diagrams 41 



111 



Notes: 



IV 



Description 



The IBM Personal Computer AT Fixed Disk and Diskette Drive 
Adapter connects to the system board using one of the system 
expansion slots. The adapter controls the 5-1/4 inch diskette 
drives and fixed disk drives. Connectors on the adapter supply all 
the signals necessary to operate up to two fixed drives and one 
diskette drive or one fixed drive and two diskette drives. The 
adapter will allow concurrent data operations on one diskette and 
one fixed disk drive. 

The adapter operates when connected to a system board 
expansion slot. This channel is described in the "System Board" 
section of the IBM Personal Computer AT Technical Reference 
Manual. 



Fixed Disk Function 



The fixed disk function features 512-byte sectors; high-speed, 
programmed input/output (PIO) data transfers; error correction 
code (ECC) correction of up to five bits on data fields; multiple 
sector operations across track and cylinder boundaries; and 
on-board diagnostic tests. The adapter will support two fixed 
disks with up to 16 read/write heads and 1024 cylinders. 



August 31, 1984 

Personal Computer AT Fixed Disk and Diskette Drive Adapter 1 



Task File 

A task file, which contains eight registers, controls fixed-disk 
operations. The following figure shows the addresses and 
functions of these registers. 



I/O Address 


Read 


Write 


Primary 


Secondary 


1F0 


170 


Data Register 


Data Register 


1F1 


171 


Error Register 


Write Precomp 


1F2 


172 


Sector Count 


Sector Count 


1F3 


173 


Sector Number 


Sector Number 


1F4 


174 


Cylinder Low 


Cylinder Low 


1F5 


175 


Cylinder High 


Cylinder High 


1F6 


176 


Drive/Head 


Drive /Head 


1F7 


177 


Status Register 


Command Register 



Task File 



Task File Registers 

Data Register 

The data register provides access to the sector buffer for read and 
write operations in the PIO mode. This register must not be 
accessed unless a Read or Write command is being executed. The 
register provides a 16-bit path into the sector buffer for normal 
Read and Write commands. When a R/W Long is issued, the 4 
ECC bytes are transferred by byte with at least 2 microseconds 
between transfers. 'Data Request' (DRQ) must be active before 
the transferring of the ECC bytes. 

Error Register 

The error register is a read-only register that contains specific 
information related to the previous command. The data is vaUd 
only when the error bit in the status register is set, unless the 
adapter is in diagnostic mode. Diagnostic mode is the state 
immediately after power is switched on or after a Diagnose 
command. In these cases, the register must be checked regardless 
of the status register indicator. The following are bit values for 
the diagnostic mode. 



August 31, 1984 
2 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Diagnostic Mode 

01 No errors 

02 Controller error 

03 Sector buffer error 

04 ECC device error 

05 Control processor error 

The following are bit definitions for the operational mode. 

Operational Mode 

Bit Data Address Mark (DAM) Not Found — This bit 

indicates that DAM could not be found within 16 bytes 
of the ID field. 

Bit 1 TR 000 Error — This bit will be set if, during a Restore 
command, the track 000 line from the fixed disk is not 
true within 1023 step pulses to the drive. 

Bit 2 Aborted Command — A command is aborted based on 
the drive status (Write Fault, Not Seek Complete, Drive 
Not Ready, or an invalid command). The status and 
error registers may be decoded to determine the cause. 

Bit 3 Not used. 

Bit 4 ID Not Found — The ID field with the specified cylinder, 
head, and sector number could not be found. If retries 
are enabled, the controller attempts to read the ID 16 
times before indicating the error. If retries are disabled, 
the track is scanned a maximum of two times before 
setting this error bit. 

Bit 5 Not used 



August 31, 1984 

Personal Computer AT Fixed Disk and Diskette Drive Adapter 3 



Bit 6 Data ECC Error — This bit indicates that an 

uncorrectable ECC error occurred in the target's data 
field during a read command. 

Bit 7 Bad Block Detect — This bit indicates that the bad block 
mark was detected in the target's ID field. No Read or 
Write commands will be executed in any data fields 
marked bad. 



Write Precompensation Register 

The value in this register is the starting cylinder number divided 
by 4. The 'reduced write current ' signal to the drive is activated 
and the adapter's write precompensation logic is turned on when 
this number is entered into the register. 



Sector Count Register 

The sector count register defines the number of sectors to be 
transferred during a Verify, Read, Write, or Format command. 
During a multi-sector operation, the sector count is decremented 
and the sector number is incremented. When the disk is being 
formatted, the number of sectors per track must be loaded into 
the register prior to each Format command. The adapter supports 
multi-sector transfers across track and cyUnder boundaries. The 
drive characteristics must be set up by the Set Parameters 
command before initiating a multi-sector transfer. The sector 
count register must be loaded with the number of sectors to be 
transferred for any data-related command. 

Note: A in the sector count register specifies a 256-sector 
transfer. 



Sector Number Register 

The target's logical sector number for Read, Write, and Verify 
commands is loaded into this register. The starting sector number 
is loaded into this register for multi-sector operations. 



August 31, 1984 
4 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Cylinder Number Registers 

The target number for Read, Write, Seek, and Verify commands 
is loaded into these registers as shown in the following figure. The 
cylinder-number registers address up to 1024 cylinders. 





Cylinder High 


Cylinder Low 


Register Bits 
Cylinder Bits 


76543210 

98 


76543210 
76543210 



Cylinder Number Registers 

Drive/Head Register 

Bit 7 Set to 1 

Bit 6 Set to 

Bit 5 Set to 1 

Bit 4 Drive Select — This bit selects the drive. A 

indicates the first fixed disk drive, and a 1 
indicates the second. 

Bit 3-Bit Head Select Bits — Bits 3 through specify the 

desired read/write head. Bit is the 
least-significant (0101 selects head 5). The 
adapter supports up to 16 read/write heads. For 
access to heads 8 through 15, bit 3 of the fixed 
disk register (address hex 3F6) must be set to 1. 

Note: This register must be loaded with the maximum 
number of heads for each drive before a Set Parameters 
command is issued. 

Status Register 

The controller sets up the status register with the command status 
after execution. The program must look at this register to 
determine the result of any operation. If the busy bit is set, no 
other bits are vaUd. A read of the status register clears interrupt 



August 31, 1984 

Personal Computer AT Fixed Disk and Diskette Drive Adapter 5 



request 14. If ' -write fault ' or 'error' is active, or if '-seek 
complete ' or ' -ready ' is inactive, a multi-sector operation is 
aborted. 

The following defines the bits of the status register: 

Bit 7 Busy — This bit indicates the controller's status. 

A 1 indicates the controller is executing a 
command. If this bit is set, no other status 
register bit is vaUd, and the other registers reflect 
the status register's contents; therefore, the busy 
bit must be examined before any fixed disk 
register is read. 

Bit 6 Drive Ready — A 1 on this bit together with a 1 

on seek complete bit (bit 4) indicates that the 
fixed disk drive is ready to read, write, or seek. A 
indicates that read, write, and seek are 
inhibited. 

Bit 5 Write Fault — A 1 on this bit indicates improper 

operation of the drive; read, write, or seek is 
inhibited. 

Bit 4 Seek Complete — A 1 on this bit indicates that the 

read/ write heads have completed a seek 
operation. 

Bit 3 Data Request — This bit indicates that the sector 

buffer requires servicing during a Read or Write 
command. If either bit 7 (busy) or this bit is 
active, a command is being executed. Upon 
receipt of any command, this bit is reset. 

Bit 2 Corrected Data — A 1 on this bit indicates that 

the data read from the disk was successfully 
corrected by the ECC algorithm. Soft errors will 
not end multi-sector operations. 

Bit 1 Index — This bit is set to 1 each revolution of the 

disk. 



August 31, 1984 
6 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



BitO 



Error — A 1 on this bit indicates that the previous 
command ended in an error, and that one or more 
bits are set in the error register. The next 
command from the controller resets the error bit. 
This bit, when set, halts multi-sector operations. 



Command Register 

The command register accepts eight commands to perform fixed 
disk operations. Commands are executed by loading the task file 
and writing in the command register while the controller status is 
not busy. If ' -write fault ' is active or if ' -drive ready ' or ' -seek 
complete ' are inactive, the controller will not execute any 
command. Any code not defined in the following figure causes an 
Aborted Command error. Interrupt request 14 is reset when any 
command is written. The following are acceptable commands to 
the command register. 



Command 


Bits 








7 


6 


5 


4 3 2 10 


Restore 











1 R3 R2 R1 RO 


Seek 





1 


1 


1 R3 R2 R1 RO 


Read Sector 








1 


L T 


Write Sector 








1 


1 L T 


Format Track 





1 





10 


Read Verify 





1 





T 


Diagnose 


1 








10 


Set Parameters 


1 








10 1 



Valid Command-Register Commands 

Note: Stepping rate values and bit definitions for L and T 
are shown in the following figures. 



August 31, 1984 

Personal Computer AT Fixed Disk and Diskette Drive Adapter 



The following figure shows the stepping rate as defined by R3 
through RO. 



R3 


R2 


R1 


RO 


Stepping Rate 














35 us 













0.5 ms 













1.0 ms 












1.5 ms 





1 








2.0 ms 





1 







2.5 ms 





1 







3.0 ms 





1 






3.5 ms 













4.0 ms 












4.5 ms 












5.0 ms 











5.5 ms 




1 








6.0 ms 




1 







6.5 ms 




1 







7.0 ms 




1 






7=5 ms 



Stepping Rate 

Note: After a Diagnose or Reset Command, the stepping 
rate is set to 7.5 miUiseconds. 

The following figure shows the bit definitions for bits L and T. 



Bit 


Definition 





1 


L 

T 


Data Mode 
Retry Mode 


Data Only 
Retries Enabled 


Data Plus 4 Byte ECC 
Retries Disabled 



L and T Bit Definitions 

Note: When retries are disabled, ECC and ID field retries 
are limited to less than two complete revolutions. 

Following are descriptions of the vahd command-register 
commands. 

Restore: The controller issues step pulses to the drive until the 
Track 000 indicator from the drive is active. If Track 000 is not 
active within 1023 steps the error bit in the status register is set 
and a Track 000 error is posted in the error register. The implied 
seek step rate can be set up using the stepping rate figure on the 



August 31, 1984 
8 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



previous page. The restore step rate is established by the seek 
complete signal from the drive (each step pulse is issued after 
seek complete is asserted by the drive from the previous step). 

Seek: The Seek command moves the R/W heads to the cylinder 
specified in the task files. The adapter supports overlapped 
seeking on two drives or setup of the buffered seek stepping rate 
for the impUed seek during a Read/Write command. An interrupt 
is generated at the completion of the command. 

Read Sector: A number of sectors (1-256) may be read from 
the fixed disk with or without the ECC field appended in the 
Programmed I/O (PIO) mode. If the heads are not over the 
target track, the controller issues step pulses to the drive and 
checks for the proper ID field before reading any data. The 
stepping rate used during the imphed seek is the value specified 
during the previous Seek or Restore command. Data errors, up to 
5 bits in length, are automatically corrected on Read Short 
commands. If an uncorrectable error occurs, the data transfer 
still takes place; however, a multi-sector read ends after the 
system reads the sector in error. Interrupts occur as each sector is 
ready to be read by the system. No interrupt is generated at the 
end of the command, after the last sector is read by the system. 

Write Sector: A number of sectors (1-256) may be written to 
the fixed disk with or without the ECC field appended in the PIO 
mode. The Write Sector command also supports impUed seeks. 
Interrupts for the Write command occur before each sector is 
transferred to the buffer (except the first) and at the end of the 
command. The first sector may be written to the buffer 
immediately after the command has been sent, and ' -data 
request ' is active. 

Format Track: The track specified by the task file is formatted 
with ID and data fields according to the interleave table 
transferred to the buffer. The interleave table is composed of two 
bytes per sector as follows: 00, Physical Sector 1, 00, Physical 
Sector 2, ... 00, Physical Sector 17. The table for 2-to-l 
interleave is: 00, 01, 00, OA, 00, 02, 00, OB, 00, 03, 00, OC, 00, 
04, 00, OD, 00, 05, 00, OE, 00, 06, 00, OF, 00, 07, 00, 10, 00, 08, 
00, 1 1, 00, 09. The data transfer must be 512 bytes even though 
the table may be only 34 bytes. The sector count register must be 
loaded with the number of sectors per track before each Format 



August 31, 1984 

Personal Computer AT Fixed Disk and Diskette Drive Adapter 9 



Track command. An interrupt is generated at the completion of 
the command; the Format Track command supports no error 
reporting. A bad block may be specified by replacing a 00 table 
entry with an 80. 

When switching between drives, a restore command must be 
executed prior to attempting a format. 

Preform the following when formatting a drive with more than 8 
read/ write heads: 

1 . Restore 

2. Format all cylinders, heads 0-7 only 

3. Restore 

4. Format all cylinders, heads 8 and above. 

Read Verify: This command is similar to to a Read command 
except that no data is sent to the host. This allows the system to 
verify the integrity of the fixed disk drive. A single interrupt is 
generated upon completion of the command or in the event of an 
error. 

Diagnose: This command causes the adapter to execute its 
self -test code and return the results to the error register. An 
interrupt is generated at the completion of this command. 

Set Parameters: This command sets up the drive parameters 
(maximum number of heads and sectors per track). The 
drive/head register specifies the drive affected. The sector count 
and drive/head registers must be set up before this command is 
issued. The adapter uses the values specified for track and 
cyUnder crossing during multi-sector operations. An interrupt is 
generated at the completion of this command. This command 
must be issued before any multi-sector operations are attempted. 
The adapter supports two fixed disk drives with different 
characteristics, as defined by this command. 



August 31, 1984 
10 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Miscellaneous Information 

The following is miscellaneous information about the fixed disk 
drive function. 

• The adapter performs normal read/write operations on a 
data field only after a successful match of that sector's ID 
with the targeted ID. 

• ID fields are checked for errors when read from the disk. 

• The adapter supports only ECC on data fields and only CRC 
on ID fields. The CRC polynomial is X16 + X12 + X5 + 1; 
the ECC polynomial is X32 + X28 + X26 + X19 + X17 + 
XIO + X6 + X2 -f 1. All shift registers are preset to hex F 
before calculating the checksums, which begin with the 
respective address marks. 



Diskette Function 



The 5-1/4 inch diskette drive function is an integral part of the 
Fixed Disk and Diskette Drive Adapter. One or two diskette 
drives are attached to the adapter through an internal, 
daisy-chained, flat cable. The attachment will support 160K.-, 
320K.-, and 1.2M.-byte diskette drives. 

The address assignments for diskette functions are shown in the 
following figure. 



I/O Address 


Read 


Write 


Primary 


Secondary 


3F2 


372 


- 


Digital Output Register 


3F4 


374 


Main Status Register 


Main Status Register 


3F5 


375 


Diskette Data Register 


Diskette Data Register 


3F6 


376 


- 


Fixed Disk Register 


3F7 


377 


Digital Input Register 


Diskette Control Register 



Diskette Function 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 1 1 



The adapter is designed for a double-density, MFM-coded, 
diskette drive and uses write precompensation with an analog 
circuit for clock and data recovery. The diskette-drive parameters 
are programmable, and the diskette drive's write-protect feature is 
supported. The adapter is buffered on the I/O bus and uses the 
system board's direct memory access (DMA) for record data 
transfers. An interrupt level also is used to indicate when an 
operation is complete and that a status condition requires 
microprocessor attention. 



Digital Output Register (hex 3F2) 

The digital output register (DOR) is an output-only register used 
to control drive motors, drive selection, and feature enable. The 
bit definitions follow: 

Bit 7 Reserved 

Bit 6 Reserved 

Bit 5 Drive B Motor Enable 

Bit 4 Drive A Motor Enable 

Bit 3 Enable Diskette Interrupts and DMA 

Bit 2 Diskette Function Reset 

Bit 1 Set to a logical 

Bit Drive Select — A on this bit indicates that drive 

A is selected. 

Note: A channel reset clears all bits. 



Digital Input Register (hex 3F7) 

The digital input register is an 8-bit, read-only register used for 
diagnostic purposes. The following are bit definitions for this 
register: 



August 31, 1984 
12 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Bit? 


Diskette Change 


Bit 6 


Write Gate 


Bits 


Head Select 3 /Reduced Write Current 


Bit 4 


Head Select 2 


Bit 3 


Head Select 1 


Bit 2 


Head Select 


Bitl 


Drive Select 1 


BitO 


Drive Select 



Note: Bits through 6 apply to the currently 
selected fixed disk drive. These bits are valid 
for 50 microseconds after a write to the 
Drive Head Register. 



Data Rates 

The diskette function will support three data rates: 250,000, 
300,000 and 500,000 bits per second. 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 13 



Diskette Controller 

The diskette controller has two registers to which the system 
unit's microprocessor has access: a status register and a data 
register. The status register may only be read and is used to 
facilitate the transfer of data between the processor and diskette 
controller. The 8 -bit status register has the status information 
about the diskette and may be accessed at any time. The 8-bit 
data register (hex 3F5), which actually consists of several 
registers in a stack with only one register presented to the data 
bus at a time, stores data, commands, and parameters, and 
provides diskette-drive status information. Data bytes are read 
from or written to the data register in order to program or obtain 
results after a particular command. 

The bits in the status register (hex 34F) are defined as follows: 

Bit 7 Request for Master (RQM) — The data register 

is ready to send or receive data to or from the 
processor. 

Bit 6 Data Input/Output (DIO) — The direction of 

data transfer between the diskette controller and 
the processor. If this bit is a 1, transfer is from 
the diskette controller's data register to the 
processor; if it is a 0, the opposite is true. 

Bit 5 Non-DMA Mode (NDM)— -The diskette 

controller is in the non-DMA mode. 

Bit 4 Diskette Controller Busy (CB)— A Read or 

Write command is being executed. 

Bit 3 Reserved 

Bit 2 Reserved 

Bit 1 Diskette Drive B Busy (DBB) — Diskette drive 

B is in the seek mode. 

Bit Diskette Drive A Busy (DAB) — Diskette drive 

A is in the seek mode. 



August 31, 1984 
14 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Diskette Control Register (hex 3F7) 

This register is assigned two addresses, hex 3F7 (primary) and 
hex 377 (secondary). This is a four bit write only register. The 
bits are defined as follows: 

Bits 7-2 Reserved 

Bits 2 - Diskette Data Rate — These bits select the 

diskette data rate as shown in the following 
figure: 



BitO 


Bit1 


Diskette 
Data Rate 





1 
1 



1 


1 


500,000 bps 

300,000 bps 

250.000 bps 

Unused 



Diskette Data Rate 

Fixed Disk Register (hex 3F6) 

This register is assigned two addresses, 3F6 (primary) and 376 
(secondary). This is a four bit write only register. The bits are 
defined as follows: 

Bits 7-4 Reserved 

Bit 3 A logical enables reduced write current. A 

logical 1 enables head select 3. 

Bit 2 A logical 1 enables reset fixed disk function. 

Bit 1 A logical enables fixed disk interrupts. 

Bit Reserved 

Note: Bit 3 defines the function of the fixed disk control 
interface connector (pin 2). 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 15 



Diskette Controller Commands 

The diskette controller can perform 16 different commands. 
Each command is initiated by a multibyte transfer from the 
processor, and the result after execution of the command may 
also be a multibyte transfer back to the processor. Because of 
this multibyte interchange of information between the diskette 
controller and the processor, each command can be considered to 
consist of three phases: 

Command Phase: The processor issues a sequence of Write 
commands to the diskette controller that direct the controller to 
perform a specific operation. 

Execution Phase: The diskette controller performs the specified 
operation. 

Result Phase: After completion of the operation, status and 
other housekeeping information is made available to the processor 
through a sequence of Read commands to the processor. 

The following is a list of commands that may be issued to the 
diskette controller: 

Read Data 

Read Deleted Data 

Write Data 

Write Deleted Data 

Read a Track 

Read ID 

Format a Track 

Scan Equal 

Scan Low or Equal 

Scan High or Equal 



August 31, 1984 
16 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Recalibrate 

Sense Interrupt Status 

Specify 

Sense Drive Status 

Seek 

Invalid. 

Symbol Descriptions 

The following are descriptions of the symbols used in the 
"Command Definitions" later in this section. 

AO Address Line — A logical selects the main status 

register, and a 1 selects the data register. 

C Cylinder Number — Contains the current or selected 

cylinder number in binary notation. 

D Data — Contains the data pattern to be written to a 

sector. 

D7-D0 Data Bus — An 8-bit data bus in which D7 is the 

most-significant bit and DO is the least- significant. 

DTL Data Length — When N is 00, DTL is the data length to 
be read from or written to a sector. 

EOT End of Track — The final sector number on a cylinder. 

GPL Gap Length — The length of gap 3 (spacing between 
sectors excluding the VCO synchronous field). 

H Head Address- — The head number, either or 1 , as 

specified in the ID field. 

HD Head— The selected head number, or L (H = HD in 

all command words.) 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 17 



HLT Head Load Time — The head load time in the selected 

drive (2 to 256 milliseconds in 2- miUisecond increments 
for the 1.2M-byte drive and 4 to 512 milliseconds in 4 
miUisecond increments for the 320K-byte drive ). 

HUT Head Unload Time — The head unload time after a read 
or write operation (0 to 240 miUiseconds in 
16-minisecond increments for the 1.2M-byte drive and 
to 480 miUiseconds in 32- millisecond increments for the 
320K-byte drive. 

MF FM or MFM Mode — A selects FM mode and a 1 

selects MFM (MFM is selected only if it is 
implemented.) 

MT Multitrack^ — A 1 selects multitrack operation. (Both 

HDO and HDl wiU be read or written.) 

N Number — The number of data bytes written in a sector. 

NCN New CyUnder — The new cyUnder number for a seek 
operation 

ND Non-Data Mode — This indicates an operation in the 

non-data mode. 

PCN Present Cylinder Number — The cyUnder number at the 
completion of a Sense interrupt status command 
(present position of the head). 

R Record — The sector number to be read or written. 

R/W Read/ Write — This stands for either a ' read ' or ' write ' 
signal. 

SC Sector — The number of sectors per cyUnder. 

SK Skip — This stands for skip deleted-data address mark. 



August 31, 1984 
18 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



SRT This 4 bit byte indicates the stepping rate for the 
diskette drive as follows: 

1.2M-Byte Diskette Drive 

1111 1 millisecond 

1110 2 milliseconds 
1101 3 milliseconds 

320K-Byte Diskette Drive 

1111 2 milliseconds 
1110 4 milliseconds 
1101 6 milliseconds 

ST — ST 3 Status 0-Status 3 — One of the four registers that 
stores status information after a command is executed. 

STP Scan Test — If STP is 1 , the data in contiguous sectors is 
compared with the data sent by the processor during a 
scan operation. If STP is 2, then alternate sections are 
read and compared. 

USO-USl Unit Select — The selected driver number encoded the 
same as bits and 1 of the digital output register 
(DOR). 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 19 



Controller Commands 

The following are commands that may be issued to the controller. 

Note: An X is used to indicate a don't-care condition. 
Commands not shown in binary format are shown as bytes. 

Read Data 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 

MT MF SK 1 1 

X X X X X HD USl USO 

C 

H 

R 

N 

EOT 

GPL 

DTL 

Result Phase: The following bytes are issued by the controller in 
the result phase: 

STO 
STl 
ST2 

C 

H 

R 

N 



August 31, 1984 
20 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Read Deleted Data 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 

MT MF SK 1 1 

X X X X X HD USl USO 

C 

H 

R 

N 

EOT 

GPL 

DTL 

Result Phase: The following bytes are issued by the controller in 
the result phase: 

STO 
STl 

C 

H 

R 

N 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 21 



Write Data 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 

MT MF 1 1 

X X X X X HD USl USO 

C 

H 

R 

N 

EOT 

GPL 

DTL 

Result Phase: The following bytes are issued by the controller in 
the result phase: 

STO 
STl 
ST2 

C 

H 

R 

N 



August 31, 1984 
22 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Write Deleted Data 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 

MT MF 1 1 

X X X X X HD USl USO 

C 

H 

R 

N 

EOT 

GPL 

DTL 

Result Phase: The following bytes are issued by the controller in 
the result phase: 

STO 
STl 
ST2 

C 

H 

R 

N 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 23 



Read a Track 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 

MF SK 1 

X X X X X HD USl USO 

C 

H 

R 

N 

EOT 

GPL 

DTL 

Result Phase: The following bytes are issued by the controller in 
the result phase: 

STO 
STl 
ST2 

C 

H 

R 

N 



August 31, 1984 
24 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Read ID 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 






MF 








1 





1 





X 


X 


X 


X 


X 


HD 


USl 


USO 



Result Phase: The following bytes are issued by the processor in 
the command phase: 

STO 
STl 
ST2 

C 

H 

R 

N 



Format a Track 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 






MF 





1 1 








X 


X 


X 


X X HD 
N 

SC 
GPL 
D 


USl 


USO 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 25 



Result Phase: The following bytes are issued by the controUer in 
the result phase: 

STO 
STl 
ST2 

C 

H 

R 

N 



Scan Equal 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 

MT MF SK 1 1 

X X X X X HD USl USO 

C 

H 

R 

N 

EOT 

GPL 

STP 

Result Phase: The following bytes are issued by the controller in 
the result phase: 

STO 
STl 
ST2 

C 

H 

R 

N 



August 31, 1984 
26 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Scan Low or Equal 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 

MT MF SK 1 1 1 

X X X X X HD USl USO 

C 

H 

R 

N 

EOT 

GPL 

STP 

Result Phase: The following bytes are issued by the controller in 
the result phase: 

STO 
STl 
ST2 

C 

H 

R 

N 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 27 



Scan High or Equal 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 

MT MF SK 1 1 1 1 

X X X X X HD USl USO 

C 

H 

R 

N 

EOT 

GPL 

STP 

Result Phase: The following bytes are issued by the controller in 
the result phase: 

STO 
STl 
ST2 

C 

H 

R 

N 



Recalibrate 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 02 Dl DO 
11 1 
X X X X X USl USO 

Result Phase: This command has no result phase. 



August 31, 1984 
28 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Sense Interrupt Status 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 
10 

Result Phase: The following bytes are issued by the controller in 
the result phase: 

STO 
PCN 



Specify 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 

1 1 

( SRT ) ( HUT ) 
( HLT ) ( ND ) 

Result Phase: This command has no result phase. 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 29 



Sense Driver Status 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 





















1 





X 


X 


X 


X 


X 


HD 


USl 


uso 



Result Phase: The following bytes are issued by the controller in 
the result phase: 

ST3 



Seek 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 












1 


1 


1 


1 


X 


X 


X 


X X 
NCN 


HD 


USl 


USO 



Result Phase: This command has no result phase. 



August 31, 1984 
30 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Invalid 

Command Phase: The following bytes are issued by the 
processor in the command phase: 

D7 D6 D5 D4 D3 D2 Dl DO 

Invalid Codes 
X X X X X HD USl USO 

Result Phase: The following byte is issued by the controller in 
the result phase: 

STO 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 31 



Command Status Registers 

The following is information about the command status registers 
STO through ST3. 



Command Status Register (STO) 

The following are bit definitions for command status register 0. 
Bit 7-Bit 6 Interrupt Code (IC) 

00 Normal Termination of Command 

(NT) — The command was completed and 
properly executed. 

01 Abrupt Termination of Command 

(AT) — The execution of the command was 
started but not successfully completed. 

10 Invalid Command Issue (IC) — The issued 
command was never started. 

1 1 Abnormal termination because, during the 
execution of a command, the ' ready ' signal 
from the diskette drive changed state. 

Bit 5 Seek End (SE) — Set to 1 when the controller 

completes the Seek command. 

Bit 4 Equipment Check (EC) — Set if a 'fault' signal 

is received from the diskette drive, or if the 
' track-0 ' signal fails to occur after 77 step pulses 
(Recalibrate Command). 

Bit 3 Not Ready (NR) — This flag is set when the 

diskette drive is in the not-ready state and a Read 
or Write command is issued. It is also set if a 
Read or Write command is issued to side 1 of a 
single-sided diskette drive. 

Bit 2 Head Address (HD) — Indicates the state of the 

head at interrupt. 



August 31, 1984 
32 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Bit 1-Bit Unit select and 1 (US and 1) — Indicate a 
drive's unit number at interrupt. The following 
figure shows the binary values to select each 
drive: 



Biti 


BitO 


Drive 
Selected 








A 





1 


B 


1 





Unused 


1 


1 


Unused 



Unit Selection 



Command Status Register 1 (STl) 

The following are bit definitions for command status register 1 . 



Bit? 

Bit 6 
Bits 

Bit 4 

Bit 3 
Bit 2 



End of Cylinder (EC) — Set when the controller 
tries to gain access to a sector beyond the final 
sector of a cylinder. 

Not Used — Always 0. 

Data Error (DE) — Set when the controller 
detects a CRC error in either the ID field or the 
data field. 

Overrun (OR) — Set if the controller is not 
serviced by the main system within a certain time 
limit during data transfers. 

Not Used — This bit is always set to 0. 

No Data (ND) — Set if the controller cannot find 
the sector specified in the ID register during the 
execution of a Read Data, Write Deleted Data, or 
Scan Command. This flag is also set if the 
controller cannot read the ID field without an 
error during the execution of a Read ID 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 33 



command or if the starting sector cannot be 
found during the execution of a Read Cylinder 
command. 

Bit 1 Not Writable (NW) — Set if the controller detects 

a ' write-protect * signal from the diskette drive 
during execution of a Write Data, Write Deleted 
Data, or Format Cylinder command. 

Bit Missing Address Mark (MA) — Set if the 

controller cannot detect the ID address mark. At 
the same time, the MD of status register 2 is set. 



Command Status Register 2 (ST2) 

Bit 7 Not Used — Always 0. 

Bit 6 Control Mark (CM)— This flag is set if the 

controller encounters a sector that has a deleted 
data-address mark during execution of a Read 
Data or Scan command. 

Bit 5 Data Error in Data Field (DD) — Set if the 

controller detects an error in the data. 

Bit 4 Wrong Cylinder (WC)— This flag is related to 

ND (no data) and when the contents of C on the 
medium are different from that stored in the ID 
register, this flag is set. 

Bit 3 Scan Equal Hit (SH) — Set if the contiguous 

sector data equals the processor data during the 
execution of a Scan command. 

Bit 2 Scan Not Satisfied (SN)— Set if the controller 

cannot find a sector on the cylinder that meets 
the condition during a Scan command. 

Bit 1 Bad Cylinder (EC)— Related to ND; when the 

contents of C on the medium are different from 
that stored in the ID register, and the contents of 
C is FF, this flag is set. 



August 31, 1984 
34 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Bit Missing Address Mark in Data Field (MD) — Set 

if the controller cannot find a data address mark 
or a deleted data address mark when data is read 
from the medium. 



Command Status Register 3 (ST3) 

The following are bit definitions for command status register 3. 

Bit 7 Fault (FT) — Status of the ' fault ' signal from the 

diskette drive. 

Bit 6 Write Protect (WP) — Status of the 

' write-protect ' signal from the diskette drive. 

Bit 5 Ready (RY) — Status of the ' ready ' signal from 

the diskette drive. 

Bit 4 Track (TO)— Status of the ' track ' signal 

from the diskette drive. 

Bit 3 Two Side (TS) — Status of the ' two side ' signal 

from the diskette drive. 

Bit 2 Head Address (HD) — Status of the ' side-select ' 

signal from the diskette drive. 

Bit 1 Unit Select 1 (US 1)— Status of the 

' unit-select- 1 ' signal from the diskette drive. 

Bit Unit Select (US 0)— Status of the ' unit select 

' signal from the diskette drive. 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 35 



Interfaces 



The system interface is through the I/O channel. The address, 
DMA, and interrupt assignments are shown in the following 
figures. 



I/O Address 


Read 


Write 


Primary 


Secondary 


3F2 


372 




Digital Output Register 


3F4 


374 


Main Status Register 


Main Status Register 


3F5 


375 


Diskette Data Register 


Diskette Data Register 


3F6 


376 




Fixed Disk Register 


3F7 


377 


Digital Input Register 


Diskette Control Register 



Diskette Function 

Note: DMA request is level 2 and interrupt request is level 6. 



I/O Address 


Read 


Write 


Primary 


Secondary 


1F0 


170 


Data Register 


Data Register 


1F1 


171 


Error Register 


Write Precomp 


1F2 


172 


Sector Count 


Sector Count 


1F3 


173 


Sector Number 


Sector Number 


1F4 


174 


Cylinder Low 


Cylinder Low 


1F5 


175 


Cylinder High 


Cylinder High 


1F6 


176 


Drive/Head Register 


Drive/ Head Register 


1F7 


177 


Status Register 


Command Register 



Fixed Disk Function 

Note: Interrupt request is level 14. 
The following operations are supported by this adapter: 

• 16 bit programmed I/O (PIO), data transfers to the fixed 
disk. AH other transfers are 8 bits wide. 

• The I/O addresses, recognized by the adapter for either the 
fixed disk or the diskette function, are independently selected 
by jumpers. 



August 31, 1984 
36 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Interface Lines 

The interface to the fixed disk drive consists of the Control cable 
and the Data cable. The following figures show signals and pin 
assignments for these cables. 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 37 




Fixed Disk 
Drive 



Ground - Odd Numbers 



— Reduced Write Current/— Head Select 3 



Head Select 2 



- Write Gate 



- Seek Complete 



- Track 000 



- Write Fault 



- Head Select 



Reserved 



- Head Select 1 



- Index 



- Ready 



Step 



- Drive Select 1 



- Drive Select 2 



Reserved 



Reserved 



— Direction In 



33 34 



1-33 



8 

10 
12 
14 



16 



18 



20 
22 
24 



26 



28 



30 



32 



34 



Fixed Disl( 
And Dislcette 
Adapter 



Note: Connection is through a 2-by-17 Berg connector. Pin 
15 is reserved to polarize the connector. 

August 31, 1984 
38 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



1 2 




19 20 



Fixed Disk 
Drive 



+ MFM Write Data 



- MFM Write Data 



+ MFM Read Data 



- MFM Read Data 



13 



14 



17 



18 



Ground-Pins 2.4,6,11,12,15,16,19,20 



All Other Pins Unused 



Fixed Disl( 
And Dislcette 
Adapter 



Note: Connection is through a 2-by- 10 Berg connector. Pin 8 
is reserved to polarize the connector. 



August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 39 



The interface to the diskette drives is a single cable that carries 
both data and control signals. The signals and pin assignments are 
as follows. 

1 2 



Diskette 
Drive 




33 34 





Ground - Odd Numbers 


1-33 




Reduced Write 


2 




Reserved 


4 




Drive Select 3 


6 




Index 


8 




Drive Select 


10 




Drive Select 1 


12 




Drive Select 2 


14 




Motor On 


16 




Direction Select 


18 




Step 


20 




Write Data 


22 




Write Gate 


24 




Track 00 


26 




Write Protect 


28 




Read Data 


30 




Side 1 Select 


32 




Diskette Change 


34 









Fixed Disl( 
And Dislcette 
Adapter 



Note: Connection is through a 2-by- 17 Berg connector. Pin 5 
is reserved to polarize the connector. 

August 31, 1984 
40 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



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Fixed Disk and Diskette Drive Adapter (Sheet 3 of 9) 



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- MOEN I (SHT 4) 

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- N/C 



- HDMAEN (SHT 5) 

- N/C 



(SHT 2) DSO - 
(SHT 2) DSI - 
(SHT 2) HSO - 
(SHT 2) HSI - 
(SHT 2) HS2 - 
(SHT 2) HS3 -/RWC - 
(SHT 2) WG- 
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Fixed Disk and Diskette Drive Adapter (Sheet 6 of 9) 



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- SDB7 (SHT 5) 




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August 31, 1984 
Personal Computer AT Fixed Disk and Diskette Drive Adapter 47 



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(CLOSE) TO NEAREST DIGITAL GROUND USING. luF CAP (S 
(D DECOUPLE LFml CLOSE TO DEVICE TO NEAREST GROUND 
DECOUPLE VCO CLOSE USING .luF BETWEEN PINS lb AND 9. PIN 9 
MUST BE CONNECTED TO CLOSEST DIGITAL GROUND 



Fixed Disk and Diskette Drive Adapter (Sheet 8 of 9) 



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PIN 9 TO CLOSEST DIGITAL GROUND. CONNECT PIN 8 TO ANALOG GND "C" 



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Fixed Disk and Diskette Drive Adapter (Sheet 9 of 9) 



Notes: 



August 31, 1984 
50 Personal Computer AT Fixed Disk and Diskette Drive Adapter 



Personal Computer 
Hardware Reference 
Library 



IBM Personal Computer 
20MB Fixed Disk 
Drive Adapter 



6139790 March 17, 1986 



Notes: 



Contents 



Description 1 

Fixed Disk Controller 1 

Programming Considerations 3 

Types of Drives 3 

Status Register 4 

Sense Bytes 4 

Data Register 7 

Programming Summary 14 

Interface 15 

Connectors 17 

Logic Diagrams 19 

BIOS Listing 23 

Index Index-1 



March 17, 1986 



Notes: 



vi March 17, 1986 



Description 



The 20MB Fixed Disk Drive Adapter attaches to one or two fixed 
disk drive units through an internal, daisy-chained, flat cable 
(data/control cable). 

The adapter is buffered on the I/O bus and uses the system 
board's direct memory access (DMA) for fixed-disk-drive data 
transfers. When the adapter is enabled, an interrupt request 
occurs on the IRQ-5 line to the 8259A Interrupt Controller. The 
8259A then causes an interrupt hex OD. 

The Fixed Disk Drive Adapter provides automatic 1 1-bit burst 
error detection and correction in the form of 32-bit error 
checking and correction (ECC). 

The device level control for the Fixed Disk Adapter is contained 
on a ROM module on the adapter. A listing of this device level 
control can be found in "BIOS Listing" of this section. 

Warning: The last cylinder on the fixed disk drive is reserved for 
diagnostic use. The diagnostic write test will destroy any data on 
this cylinder. 

Fixed Disk Controller 

The disk controller has three registers that may be accessed by the 
system unit's microprocessor: a status register, a data register, and 
a read-option- jumpers register. The 8 -bit status register contains 
the status information of the disk controller, and can be accessed 
at any time. This register is read-only and is used to help the 
transfer of data between the system unit's microprocessor and the 
disk controller. The 8-bit data register (actually consisting of 
several registers in a stack with only one register presented to the 
data bus) stores data, commands, and parameters, and provides 
the disk controller's status information. Data bytes are read from, 
or written to the data register in order to program or obtain the 
results after a particular command. The controller-select pulse is 
generated by writing to port address hex 322. 



March 17, 1986 20MB Fixed Disk Drive Adapter 1 



The following is a block diagram of the IBM 20MB Fixed Disk 
Drive Adapter. 



Adapter Control 



Edge 
M — 



Connector 



I/O 

I nterface 



Ser lal Izer/ 
Deser ial izer 



SERDES 
ECC 









I/O 

I nterface 



J2 



To 

Dr i ves 

► 

J3 



Data Bus 



DB7-DB0 



8-Bit 
Processor 



Sector Buffer 



2 20MB Fixed Disk Drive Adapter 



March 17, 1986 



Programming Considerations 



Types of Drives 

The fixed disk drive adapter will accommodate any two of four 
different types of drives. The figure below shows the 
configuration of the different type drives. 



Type 


Cy 1 inders 


Heads 


Start of 
Write Pre-Comp 


Landing 
Zone 


1 


306 


k 





306 


2 


615 


k 


300 


615 


13 


306 


8 


128 


336 


16 


612 


k 





663 



Fixed Disk Types 

The figure below shows the switch settings for the above 
mentioned drive types. Switches 1 and 2 set the parameters of 
Drive 0, and switches 3 and 4 set Drive 1. 





Drive 


Drive 1 




Swi tch 


Switch 




1 


2 


3 


k 


Type 1 


On 


On 


On 


On 


Type 2 


Off 


On 


Off 


On 


Type 13 


Off 


Off 


Off 


Off 


Type 16 


On 


Off 


On 


Off 



March 17, 1986 



20MB Fixed Disk Drive Adapter 3 



Status Register 

At the end of all commands from the system board, the disk 
controller sends a completion status byte to the system board. 
This byte informs the system unit's microprocessor if an error 
occurred during the execution of the command. The following 
shows the format of this byte. 



Bit 


7 


6 


5 


k 


3 


2 


1 













d 











e 






Bits 



This bit shows the logical unit number 
of the drive. 



Bitl 



When set, this bit shows an error has 
occurred during command execution. 



Bits 7, 6, 4, 3, 2, 



These bits are set to zero. 



If the interrupts are enabled, the controller sends an interrupt 
when it is ready to transfer the status byte. Busy from the disk 
controller is unasserted when the byte is transferred to complete 
the command. 



Sense Bytes 

If the status register receives an error (bit 1 set), the disk 
controller requests four bytes of sense data. The format for the 
four bytes is as follows: 



Bits 


7 


6 


5 4 3 2 10 


Byte 


Address 
Valid 





Error Type 


Error Code 


Byte 1 








d 


Head Number 


Byte 2 


Cy 1 inder 


High 




Sector Number 


Byte 3 




Cyl 


nder Low 



Remarks : 



d = dr i ve 



4 20MB Fixed Disk Drive Adapter 



March 17, 1986 



Disk Controller Error Tables 

The following disk controller error tables list the error types and 
error codes found in byte 0. 

The address- valid bit (bit 7) is only set when the previous 
command required a disk address. Bit 6 is set to (spare). 





Error 
Type 


Error Code 




Bits 


5 h 


3 2 10 


Descr ipt Ion 










The controller did not detect any error 
during the execution of the previous 
operation. 







1 


The controller did not detect an index signal 
from the drive. 







10 


The controller did not get a seek-comp lete 
signal from the drive after a seek operation 
(for all non-buffered step seeks). 







11 


The controller detected a write fault from 
the drive during the last operation. 







10 


After the controller selected the drive, the 
drive did not respond with a ready signal. 







10 1 


Not Used. 







110 


After stepping the maximum number of cylinders, 
the controller did not receive the track 00 
signal from the drive. 







111 


Not Used. 







10 


The drive is still seeking. This status is 
reported by the test Drive Ready command for 
an overlap seek condition when the drive had 
not completed the seek. No time-out Is measured 
by the controller for the seek to complete. 



March 17, 1986 



20MB Fixed Disk Drive Adapter 5 





Error 
Type 


Error Code 




Bits 


5 k 


3 2 10 


Descr ipt ion 




1 





ID Read Error: The controller detected an 
ECC error in the target ID field on the disk. 




1 


1 


Data Error: The controller detected an 
uncorrectable ECC error in the target sector 
during a read operation. 




1 


10 


Address Mark: The controller did not detect 
the target address mark (AM) on the disk. 




1 


11 


Not Used. 




1 


10 


Sector Not Found: The controller found the 
correct cylinder and head, but not the 
target sector. 




1 


10 1 


Seek Error: The cylinder or head address 
(either or both) did not compare with the 
expected target address as a result 
of a seek. 




1 


110 


Not Used. 




1 


111 


Not Used. 




1 


10 


Correctable Data Error: The controller 
detected a correctable ECC error in the 
target field. 




1 


10 1 


Bad Track: The controller detected a bad 
track flag during the last operation. No 
retries are attempted on this error. 





Error 
Type 


Error Code 




Bits 


5 4 


3 2 10 


Descr ipt ion 




1 





Invalid Command: The controller had 
received an invalid command from the 
system unit. 




1 


1 


Illegal Disk Address: The controller detected 
an address that is beyond the 
maximum range. 



6 20MB Fixed Disk Drive Adapter 



March 17, 1986 





Error 
Type 


Error Code 




Bits 


5 4 


3 2 10 


Descr ipt ion 




1 1 





RAM Error: the controller detected a data 
error during the RAM sector-buffer 
diagnostic test. 




1 1 


1 


Program Memory Checksum Error: During 

this internal diagnostic test, the controller 

detected a program-memory checksum error. 




1 1 


10 


ECC Polynomial Error: During the 
controller's internal diagnostic tests, the 
hardware ECC generator failed its test. 



Data Register 

The system unit's microprocessor specifies the operation by 
sending the 6-byte device control block (DCB) to the controller. 
The figure below shows the format of the DCB, and defines the 
bytes that make up the DCB. 



Bits 


7 6 5^3210 


Byte 5 


Control Field 


Byte k 


Interleave or Block Count 


Byte 3 


Cy 1 inder Low 


Byte 2 


Cy 1 i nder H i gh 


Sector Number 


Byte 1 


d 


Head Number 


Byte 


Command 
Class 


Opcode 



Byte 5 Bits 7 through contain the control field. 

Byte 4 Bits 7 through specify the interleave or block 

count. 

Byte 3 Bits 7 through are the eight least-significant bits 

of the cyhnder number. 



March 17, 1986 



20MB Fixed Disk Drive Adapter 7 



Byte 2 Bits 7 and 6 are the two most significant bits of the 

cylinder number. Bits through 5 define the sector 
number. 

Byte 1 Bit 5 identifies the drive number. Bits 4 through 

contain the disk head number to be selected. Bits 6 
and 7 are not used. 

Byte Bits 7,6, and 5 identify the class of the command. 

Bits 4 through contain the Opcode (see command 
byte on page 10 



Control Byte 

Byte 5 is the control field of the DCB and allows the user to 
select options for several types of disk drives. The format of this 
byte is as follows: 



Bit 


7 


6 


5 


k 


3 


2 


1 







r 


a 











s 


s 


s 



Bit 7 



Bit 6 



Disables the four retries by the controller on all 
disk-access commands. Set this bit only during the 
evaluation of the performance of a disk drive. 

If set to during read commands, a reread is 
attempted when an ECC error occurs. If no error 
occurs during reread, the command will finish 
without an error status. If this bit is set to 1, no 
reread is attempted. 



Bits 5, 4, 3 Set to 0. 



8 20MB Fixed Disk Drive Adapter 



March 17, 1986 



Bits 2, 1, These bits define the type of drive and select the 
step option. See the following figure. 



B 


ts 2, 


1, 


















This drive is not specified and defaults 
to 3 milliseconds per step. 










1 


N/A 







1 





N/A 


1 1 


N/A 




1 








200 microseconds per step. 


1 1 


70 microseconds per step (specified by BIOS). 


1 1 


3 milliseconds per step. 


1 1 1 


3 milliseconds per step. 



March 17, 1986 



20MB Fixed Disk Drive Adapter 9 



Command Byte 



Command 



Data Control Block 



Remarks 



Test Drive 

Ready 

(Class 0, 
Opcode 00) 

Recal ibrate 

(Class 0, 
Opcode 00) 



Reserved 
(Class 0, 
Opcode 02) 

Request Sense 

Status 
(Class 0, 
Opcode 03) 



Format Drive 

(Class 0, 
Opcode Ok) 



Ready Verify 

(Class 0, 
Opcode 05) 



Bit 


7 6 5^3210 


Byte 








Byte 1 


d 


X X X X X 



Bit 


7 6 5 4 3 2 10 


Byte 





1 


Byte 1 


d 


X X X X X 


Byte 5 


rOOOOsss 



Bit 


7 6 5^3210 


Byte 





11 


Byte 1 


d 


X X X X X 



Bit 


7 6 5^3210 


Byte 





10 


Byte 1 


d 


Head No. 


Byte 2 


ch 





Byte 3 


Cylinder Low 


Byte k 





1 nter leave 


Byte 5 


rOOOOsss 



Bit 


7 6 5 4 3 2 10 


Byte 





10 1 


Byte 1 


d 


Head No. 


Byte 2 


ch 


Sector No. 


Byte 3 


Cyl inder Low 


Byte k 


Block Count 


Byte 5 


raOOOsss 



d = dr i ve (0 or 1 ) 

X = don't care 

Bytes 2, 3, 4, 

5, = don ' t care. 

d = dr i ve (O or 1 ) 

X = don ' t care 

r = retries 

s = Step Option 

Bytes 2, 3, 4, = don't care 

ch = cyl inder h igh 

This Opcode is not used. 

d = dr i ve (0 or 1 ) 

X = don ' t care 

Bytes 2, 3,^4, 

5, = don't care. 

d = dr i ve (0 or 1 ) 

r = retries 

s = Step Option 

ch = cy 1 i nder h igh 

Interleave 1 to 16 
for 512-byte sectors. 

d = dr i ve (0 or 1 ) 

r = retries 

s = Step Option 

a = retry option on 
data ECC 

ch = cyl inder h igh 
for 512-byte sectors. 



1 20MB Fixed Disk Drive Adapter 



March 17, 1986 



Command 



Data Control Block 



Remarks 



Format Track 

(Class 0, 
Opcode 06) 



Format Bad 

Track 
(Class 0, 
Opcode 07) 



Read 
(Class 0, 
Opcode 08) 



Reserved 
(Class 0, 
Opcode 09 1 

Write 
(Class 0, 
Opcode OA) 



Bit 


7 6 5^3210 


Byte 





110 


Byte 1 


d 


Head No. 


Byte 2 


ch 





Byte 3 


Cyl Inder Low 


Byte k 





1 nter leave 


Byte 5 


r s s s 




Bit 


7 6 5^3210 


Byte 


C 


111 


Byte 1 


d 


Head No. 


Byte 2 


ch C 





Byte 3 


Cyl inder Low 


Byte k 





Inter leave 


Byte 5 


rOOOOsss 




Bit 


7 6 5^3210 


Byte 





10 


Byte 1 


d 


Head No. 


Byte 2 


ch S 


ector No. 


Byte 3 


Cyl inder Low 


Byte 5 


raOOOsss 




Bit 


7 6 5-^3210 


Byte 





10 10 


Byte 1 


d 


Head No. 


Byte 2 


ch S 


ector No. 


Byte 3 


Cyl inder Low 


Byte k 


Block Count 


Byte 5 


rOOOOsss 



d = dr i ve (O or 1 ) 
r = retries 
s = step option 
ch = cyl inder h igh 

Interleave 1 to 16 
for 512-byte sectors. 

d = drive (O or 1 ) 
X = don't care 
s = Step Option 
ch = cyl Inder high 

Interleave 1 to 16 
for 512-byte sectors. 

d = drive (O or 1 ) 

r = retries 

a = retry option on 
data ECC error 

s = step option 
ch = cyl inder h igh 

This Opcode is not used. 

d = dr i ve (O or 1 ) 
r = retries 
s = step option 
ch = cyl inder high 



March 17, 1986 



20MB Fixed Disk Drive Adapter 1 1 



Command 



Data Control Block 



Remarks 



Seek 

(Class 0, 
Opcode OB) 



Initial ize 
Dr i ve 
Character- 

i St ics" 
(Class 0, 
Opcode OC) 

Read ECC 
Burst Length 
(Class 0, 
Opcode OD) 

Read Data 
from Sector 

Buffer 
(Class 0, 

Opcode OE) 

Write Data to 
Sector Buffer 
(Class 0, 
Opcode OF) 



RAM 

Diagnost ic 
(Class 7, 
Opcode 00) 



Reserved 
(Class 7, 
Opcode 01 ) 

Reserved 
(Class 7, 
Opcode 02) 



Bit 


7 6 5^3210 


Byte 





10 11 


Byte 1 


d 


Head No. 


Byte 2 


ch 





Byte 3 


Cyl inder Low 


Byte k 


xxxxxxxx 


Byte 5 


rOOOOsss 




Bit 


7 6 5^3210 


Byte 





110 




Bit 


7 6 5^3210 


Byte 





110 1 




Bit 


7 6 5 4 3 2 10 


Byte 





1110 




Bit 


7 6 5^3210 


Byte 





1111 




Bit 


7 6 5^3210 


Byte 


1 1 1 






d = dr Ive (0 or 1 ) 
r = retries 
s = Step Option 
X = don ' t care 



Bytes 1, 2, 3, 4, 5, 
don't care. 



Bytes 1, 2, 3, 4, 5, = 
don't care. 

Bytes 1, 2, 3, 4, 5, = 
don't care. 

Bytes 1, 2, 3, 4, 5, = 
don't care. 

Bytes 1, 2, 3, 4, 5, = 
don't care. 

This Opcode is not used. 

This Opcode is not used. 



"Initialize Drive Characteristics: The DBC must be followed by eight 
additional bytes. 

Maximum number of cylinders (2 bytes) 

Maximum number of heads (l byte) 

Start reduced write current cylinder (2 bytes) 

Start write precompensat ion cylinder (2 bytes) 

Maximum ECC data burst length (1 byte) 



1 2 20MB Fixed Disk Drive Adapter 



March 17, 1986 



Command 



Data Control Block 



Remarks 



Dr i ve 

D lagnost ic 
(Class 7, 
Opcode 03) 



Control ler 
I nternal 
D iagnost ics 
(Class 7, 
Opcode Ok) 



Read Long " 

Track 
(Class 7, 
Opcode 05) 



Write Long "" 
(Class 7, 
Opcode 06) 



Bit 


765^3210 


Byte 


1 1 1 


11 


Byte 1 


d 


X X X X X 


Byte 2 


xxxxxxxx 


Byte 3 


xxxxxxxx 


Byte k 


xxxxxxxx 


Byte 5 


rOOOOsss 




Bit 


7 6 5^3210 


Byte 


1 1 1 


10 




Bit 


765^3210 


Byte 


1 1 1 


10 1 


Byte 1 


d 


Head No. 


Byte 2 


ch 


Sector No. 


Byte 3 


Cyl inder Low 


Byte k 


Block Count 


Byte 5 


rOOOOsss 




Bit 


765^3210 


Byte 


1 1 1 


110 


Byte 1 


d 


Head No. 


Byte 2 


ch 


Sector No. 


Byte 3 


Cylinder Low 


Byte k 


Block Count 


Byte 5 


rOOOOsss 



d = dr i ve (0 or 1 ) 
r = retries 
s = step option 
X = don't care 



Bytes 1, 2, 3, ^, 5, 
don't care. 



d = dr i ve (O or 1 ) 
r = retries 
s = step option 
ch = cyl inder h igh 



d = dr i ve (O or 1 ) 
s = step option 
s = step option 
ch = cyl inder h igh 
s = step option 



'^ Returns 512 bytes plus k bytes of ECC data per sector. 
^^^^ Requires 512 bytes plus k bytes of ECC data per sector. 



March 17, 1986 



20MB Fixed Disk Drive Adapter 1 3 



Programming Summary 

The two least-significant bits of the address bus are sent to the 
system board's I/O port decoder, which has two sections. One 
section is enabled by the I/O read signal (-IOR) and the other by 
the I/O write signal (-IOW). The result is a total of four 
read/write ports assigned to the disk controller board. 

The address enable signal (AEN) is asserted by the system board 
when DMA is controlling data transfer. When AEN is active, the 
I/O port decoder is disabled. 

The following figure is a table of the read/ write ports. 



R/W 


Port Address 


Funct ion 


Read 
Write 


320 
320 


Read data (from controller to system unit) 
Write data (from system unit to controller) 


Read 
Write 


321 
321 


Read controller hardware status. 
Control ler reset. 


Read 
Write 


322 
322 


Read option jumpers 

Generate controller-select-pulse 


Read 
Write 


323 
323 


Not used. 

Write pattern to DMA and interrupt 
mask register. 



14 20MB Fixed Disk Drive Adapter 



March 17, 1986 



Interface 



The following lines are used by the disk controller: 

A0-A19 Positive true 20-bit address. The least-significant 10 
bits contain the I/O address within the range of hex 
320 to hex 323 when an I/O read or write is executed 
by the system unit. The full 20 bits are decoded to 
address the read-only memory (ROM) between the 
addresses of hex C8000 and hex C9FFF. 

DO-D7 Positive 8 -bit data bus over which data and status 

information is passed between the system board and 
the controller. 

-lOR This signal is active when the system board reads 

status or data from the controller under either 
programmed I/O or DMA control. 

-lOW This signal is active when the system board sends a 

command or data to the controller under either 
programmed I/O or DMA control. 

AEN This signal is active when the DMA in the system 

board is generating the I/O Read (-IOR) or I/O 
Write (-IOW) signals and has control of the address 
and data buses. 

RESET This signal forces the disk controller to its initial 
power-up condition. 

IRQ 5 This signal is active by the controller when enabled to 

interrupt the system board on the return ending status 
byte from the controller. 

DRQ 3 This signal is activated by the controller when data is 
available for transfer to or from the controller under 
DMA control. This signal remains active until the 
system board's DMA channel activates the 
DMA-acknowledge signal (-DACK 3) in response. 



March 17, 1986 



20MB Fixed Disk Drive Adapter 1 5 



-DACK 3 This signal is active when negative, and is generated 
by the system board DMA channel in response to a 
DMA request (DRQ 3). 



1 6 20MB Fixed Disk Drive Adapter March 1 7, 1 986 



Connectors 



The 20MB Fixed Disk Drive Adapter connector and interface 
specifications follow. 



Disk 

Dr I ve 

J1 



Pin 34 



Pin 20 



Pin 2 



At Standard TTL Levels 




Pin 1 



Pin 1 



Land 
Number 



Ground-Odd Numbers 


1-33 




-Reserved 


2, 16, 30, 32 




-Head Select 2 


k 




-Write Gate 


6 




-Seek Complete 


8 




-Track 000 


10 




-Write Fault 


12 




-Head Select 


]h 




-Head Select 1 


18 




- 1 ndex 


20 




-Ready 


22 




-Step 


24 




-Drive Select 1 


26 




-Drive Select 2 


28 




-Drive Select 3 


30 




-Drive Select h 


32 




-Direction In 

M 


34 





Disk 
Adapter 
J1 



March 17, 1986 



20MB Fixed Disk Drive Adapter 17 



F ixed 
Disk 
Dr i ve 
J2 or J3 



-Drive Selected 



Reserved 



3,5,7,9 



Key 



5 



+MFM Write Data 



13 



-MFM Write Data 



14 



+MFM Read Data 



-MFM Read Data 



Ground Pins 2,4,6,8,10,11,12,15, 
16,19,20 



Al 1 Other Pins Unused 



F Ixed 
Disk 
Adapter 
J2 or J3 



1 8 20MB Fixed Disk Drive Adapter 



March 17, 1986 



2 



00 
ON 



o 

i 



a 

I 




o 
cro 



A3 
A2 


&5 




ore 




I-* 




^ 




5 




C/5 


BUSY (SH.3) 




ACKNOWLEDGE (SH.3) 




RE5CT (SH.2,3) 





vo 



20MB Fixed Disk Drive Adapter (Sheet 1 of 4) 



to 

o 



o 



X 
(t 
o. 



O 

2. 

a 



sr 




(SH. 3) LATE 



IN OTHER HALF 



OS 



20MB Fixed Disk Drive Adapter (Sheet 2 of 4) 



i 



VCC CLOCK - 

ACK NOWLEDGE - 

Rb (SATE - 



l^^ 



00 

ON 



(SH. 1) BUSY- 



© 






^ 






tH 



lR12iRI 




K) 



20MB Fixed Disk Drive Adapter (Sheet 3 of 4) 



to 



O 






o 

> 






(SH. 3) hEG PUMP 




(SH.3) POS PUMP 



(SH. 3) VCO CLAMP 



(SH.3) NRZ RD DATA- 



(SH.3) NRZ CLOCK - 



(SH. 1,3) 10 MHZ CLOCK - 
(SH.3) AM DETECT - 



(SH.3) AM RESET - 
(SH.3) RD GATE - 



(SH. 3) DEABLE AM - 



(SH. 2) TEST ENABLE - 



.o^ 






pk*3.3uF I^.OIuF 



I POINT AG TO DG C 



+ T "-^ 1/2 IC 



-VCC CLOCK (SH.3 



00 



20MB Fixed Disk Drive Adapter (Sheet 4 of 4) 



BIOS Listing 



The BIOS Listing for the IBM 20MB Fixed Disk Drive Adapter 
follows. 



March 17, 1986 20MB Fixed Disk Drive Adapter BIOS 23 



-- 10/28/85 FIXED DISK BIOS 
-- INT I3H 

FIXED DISK I/O INTERFACE 



THE BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH 
SOFTWARE INTERRUPTS ONLY. ANY ADDRESSES PRESENT IN 
THE LISTINGS ARE INCLUDED ONLY FOR COMPLETENESS, 
NOT FOR REFERENCE. APPLICATIONS WHICH REFERENCE 
ABSOLUTE ADDRESSES WITHIN THE CODE SEGMENT 
VIOLATE THE STRUCTURE AND DESIGN OF BIOS. 



HEX VALUE) 



(AH) = 


02H 


(AH) = 


03H 


(AH) = 


04H 


(AH) = 


05H 


(AH) = 


06H 



RESET DISK (DL = 80H,8IH) / DISKETTE 

READ THE STATUS OF THE LAST DISK OPERATION INTO ( Al 

NOTE: DL < 80H - DISKETTE 

DL > 80H - DISK 
READ THE DESIRED SECTORS INTO MEMORY 
WRITE THE DESIRED SECTORS FROM MEMORY 
VERIFY THE DESIRED SECTORS 
FORMAT THE DESIRED TRACK 

FORMAT THE DESIRED TRACK AND SET BAD SECTOR FLAGS 
FORMAT THE DRIVE STARTING AT THE DESIRED TRACK 
RETURN THE CURRENT DRIVE PARAMETERS 



09H INITIALIZE DRIVE PAIR CHARACTERISTICS 

INTERRUPT 41 H POINTS TO DATA BLOCK 
OAH READ LONG 
OBH WRITE LONG 

NOTE: READ AND WRITE LONG ENCOMPASS 

512 BYTES + 4 BYTES OF ECC 
OCH SEEK 

ODH ALTERNATE DISK RESET (SEE DL) 
OEH READ SECTOR BUFFER 
OFH WRITE SECTOR BUFFER, 

(RECOMMENDED PRACTICE BEFORE FORMATTING) 
10H TEST DRIVE READY 
11H RECALIBRATE 
12H CONTROLLER RAM DIAGNOSTIC 
13H DRIVE DIAGNOSTIC 
14H CONTROLLER INTERNAL DIAGNOSTIC 

REGISTERS USED FOR FIXED DISK OPERATIONS 



DRIVE NUMBER 
HEAD NUMBER 
CYLINDER NUMBER 
SECTOR NUMBER 



(80H-87H FOR DISK, VALUE CHECKED) 
(0-7D ALLOWED, NOT VALUE CHECKED) 
(0-1023D, NOT VALUE CHECKED) (SEE CD 
(1-17D, NOT VALUE CHECKED) 



NOTE: HIGH 2 BITS OF CYLINDER NUMBER ARE PLACED 
IN THE HIGH 2 BITS OF THE CL REGISTER 
(10 BITS TOTAL) 

NUMBER OF SECTORS (MAXIMUM POSSIBLE RANGE 1-80H, 
FOR READ/WRITE LONG 1-79H) 

(INTERLEAVE VALUE FOR FORMAT 1-I6D) 

ADDRESS OF BUFFER FOR READS AND WRITES, 

(NOT REQUIRED FOR VERIFY) 



AH = STATUS OF CURRENT OPERATION 

STATUS BITS ARE DEFINED IN THE EQUATES BELOW 
CY = SUCCESSFUL OPERATION (AH= OOH ON RETURN) 
CY = 1 FAILED OPERATION (AH HAS ERROR REASON) 

NOTE: ERROR 11H INDICATES THAT THE DATA READ HAD A RECOVERABLE 
ERROR WHICH WAS CORRECTED BY THE ECC ALGORITHM. THE DATA 
IS PROBABLY GOOD, HOWEVER THE BIOS ROUTINE INDICATES AN 
ERROR TO ALLOW THE CONTROLLING PROGRAM A CHANCE TO DECIDE 
FOR ITSELF. THE ERROR MAY NOT RECUR IF THE DATA IS 
REWRITTEN. (AL) CONTAINS THE BURST LENGTH. 

IF DRIVE PARAMETERS WERE REQUESTED, 

DL = NUMBER OF CONSECUTIVE ACKNOWLEDGING DRIVES 

ATTACHED (0-2) (CONTROLLER CARD ZERO TALLY ONLY) 
DH = MAXIMUM USEABLE VALUE FOR HEAD NUMBER 
CH = MAXIMUM USEABLE VALUE FOR CYLINDER NUMBER 
CL = MAXIMUM USEABLE VALUE FOR SECTOR NUMBER 
AND CYLINDER NUMBER HIGH BITS 

IF AN ERROR OCCURS ON READ DRIVE PARAMETERS, 

AH = ERROR CODE (INIT_FAIL) 



24 20MB Fixed Disk Drive Adapter BIOS 



March 17, 1986 



105 




106 




107 




108 


= OOFF 


109 


= OOCC 


1 10 


= OOBB 


1 1 1 


= 0080 


1 12 


= 0040 


1 13 


= 0020 


1 14 


= 001 1 


1 15 


= 0010 


1 16 


= OOOB 


1 17 


= 0009 


1 18 


= 0007 


1 19 


= 0005 


120 


= 0004 


121 


= 0002 


122 


= 0001 



ERROR RETURN STATUS ( AH ) = 



0000 
0034 
0034 
004C 
004C 
0064 
0064 
0078 
0078 
0100 
0100 
104 
0104 
7C00 
7C00 
7C00 

0000 
006C 
006C 
0072 
0072 
0074 
0074 
0075 
0076 
0077 
0078 



SENSE FAIL 


EQU 


OFFH ; 


WRITE FAULT 


EQU 


OCCH ; 


UNDEF ERR 


EQU 


OBBH ; 


TIME OUT 


EQU 


080H ; 


BAD SEEK 


EQU 


040H 5 


BAD CNTLR 


EQU 


020H ; 


DATA CORRECTED 


EQU 


01 IH ; 


BAD ECC 


EQU 


01 OH ; 


BAD TRACK 


EQU 


OOBH ; 


DMA BOUNDARY 


EQU 


009H ; 


INIT FAIL 


EQU 


007H ; 


BAD RESET 


EQU 


005H ; 


RECORD NOT FND 


EQU 


004H ; 


BAD ADDR MARK 


EQU 


002H ; 


BAD_CMD 


EQU 


001H ; 


. 

; INTERRUPT AND 


STATUS AREAS : 


ABSO SEGMENT 


AT OH 






ORG 


OODHM ; 


HDISK_INT 


LABEL 


DWORD 




ORG 


13H»4 ; 


ORG_VECTOR 


LABEL 


DWORD 




ORG 


019H*4 ; 


BOOT_VEC 


LABEL 


DWORD 




ORG 


01EH'4 ; 


DISKETTE_PARM 


LABEL 


DWORD 




ORG 


040H'4 ; 


DISK_VECTOR 


LABEL 


DWORD 




ORG 


041H*4 ; 


HF_TBL_VEC 


LABEL 


DWORD 




ORG 


7C00H ; 


BOOT LOCN 


LABEL 


FAR 


ABSO ENDS 






DATA SEGMENT 


AT 40H 






ORG 


06CH 


T1MER_L0W 


DW 


? ; 




ORG 


072H 


RESET_FLAG 


DW 


? 




ORG 


074H 


DISK STATUS 


DB 


? ; 


HF NUM 


DB 


? ; 


CONTROL BYTE 


DB 


? ; 


PORT OFF 


DB 


? ; 


DATA ENDS 







SENSE OPERATION FAILED 
WRITE FAULT ON SELECTED DRIVE 
UNDEFINED ERROR OCCURRED 
ATTACHMENT FAILED TO RESPOND 
SEEK OPERATION FAILED 
CONTROLLER HAS FAILED 
ECC CORRECTED DATA ERROR 
BAD ECC ON DISK READ 
BAD TRACK FLAG DETECTED 
ATTEMPT TO DMA ACROSS 64K BOUNDARY 
DRIVE PARAMETER ACTIVITY FAILED 
; RESET FAILED 

REQUESTED SECTOR NOT FOUND 

ADDRESS MARK NOT FOUND 

BAD COMMAND PASSED TO D I SK I/O 



FIXED DISK INTERRUPT VECTOR 
DISK INTERRUPT VECTOR 
BOOTSTRAP INTERRUPT VECTOR 
DISKETTE PARAMETERS 
NEW DISKETTE INTERRUPT VECTOR 
FIXED DISK PARAMETER VECTOR 
BOOTSTRAP LOADER VECTOR 



TIMER LOW WORD 

1234H IF KEYBOARD RESET UNDERWAY 

FIXED DISK STATUS BYTE 
COUNT OF FIXED DISK DRIVES 
CONTROL BYTE DRIVE OPTIONS 
PORT OFFSET 



1 74 






175 






176 












1 78 






1 79 




0320 


180 




0020 


181 




0021 


182 




0020 


183 




0008 


184 




0004 


185 




0002 


186 




0001 


187 






188 




0047 


189 




004B 


190 




0000 


191 




0082 


192 






193 


= 


0000 


194 




0001 


195 




0003 


196 




0004 


197 




0005 


198 




0006 


199 




0007 


200 




0008 


201 




OOOA 


202 




OOOB 


203 




OOOC 


204 




OOOD 


205 




OOOE 


206 




OOOF 


207 




OOEO 


208 




00E3 


209 




00E4 


210 




00E5 


21 1 




00E6 


212 






213 




0008 


214 


= 


0002 



HARDWARE SPECIFIC VALUES 

- CONTROLLER I/O PORT 

> WHEN READ FROM: 

HF_PORT+0 - READ DATA (FROM CONTROLLER TO CPU) 
HF_P0RT+1 - READ CONTROLLER HARDWARE STATUS 

(CONTROLLER TO CPU) 
HF_P0RT+2 - READ CONFIGURATION SWITCHES 
HF_P0RT+3 - NOT USED 

> WHEN WRITTEN TO: 

HF_PORT+0 - WRITE DATA (FROM CPU TO CONTROLLER) 
HF_P0RT+1 - CONTROLLER RESET 

HF_P0RT+2 - GENERATE CONTROLLER SELECT PULSE 
HF_P0RT+3 - WRITE PATTERN TO DMA AND INTERRUPT 
MASK REGISTER 



. 

CMD BLOCK 


EQU 


BYTE PTR [BP]-8 


CMD BLOCK HEAD 


HF PORT 


EQU 


0320H 


DISK PORT 




INTAOO 


EQU 


020H 


8259 PORT 




INTA0 1 


EQU 


021H 


8259 PORT 




EOI 


EQU 


020H 


END OF INTERRUPT COMMAND 


R1 BUSY 


EQU 


00001000B 


DISK PORT 1 


BUSY BIT 


Rl BUS 


EQU 


00000100B 




COMMAND/DATA BIT 


R1 lOMODE 


EQU 


00000010B 




MODE BIT 


R1_REQ 


EQU 


OOOOOOOIB 




REQUEST BIT 


DMA READ 


EQU 


010001 1 IB 


CHANNEL 3 (047H) 


DMA WRITE 


EQU 


010010I1B 


CHANNEL 3 (04BH) 


DMA 


EQU 


OOOH 


DMA ADDRESS 




DMA_H1GH 


EQU 


082H 


PORT FOR HIGH 4 BITS OF DMA 


TST RDY CMD 


EQU 


OOOOOOOOB 


CNTLR READY 


(OOH) 


RECAL CMD 


EQU 


OOOOOOOIB 


RECAL 


(01H) 


SENSE CMD 


EQU 


0000001 IB 


SENSE 


(03H) 


FMTDRV CMD 


EQU 


OOOOOIOOB 


DRIVE 


(04H) 


CHK TRK CMD 


EQU 


00000101B 


T CHK 


(05H) 


FMTTRK CMD 


EQU 


000001 10B 


TRACK 


(06H) 


FMTBAD CMD 


EQU 


000001 1 IB 


BAD 


(07H) 


READ CMD 


EQU 


000010008 


READ 


(08H) 


WRITE CMD 


EQU 


OOOOIOIOB 


WRITE 


(OAH) 


SEEK CMD 


EQU 


0000101 IB 


SEEK 


(OBH) 


INIT DRV CMD 


EQU 


00001 100B 


INIT 


(OCH) 


RD ECC CMD 


EQU 


00001 101B 


BURST 


(ODH) 


RD BUFF CMD 


EQU 


OOOOI 1 10B 


BUFFR 


(OEH) 


WR BUFF CMD 


EQU 


00001 1 1 IB 


BUFFR 


(OFH) 


RAM DIAG CMD 


EQU 


1 1 100000B 


RAM 


(EOH) 


CHK DRV CMD 


EQU 


1 1 10001 IB 


DRV 


(E3H) 


CNTLR DIAG CMD 


EQU 


1 1 tOOIOOB 


CNTLR 


(E4H) 


RD LONG CMD 


EQU 


1 1 lOOIOIB 


RLONG 


(E5H) 


WR_LONG_CMD 


EQU 


1 1 1 001 lOB 


WLONG 


(E6H) 


MAX FILE 


EQU 


8 






S_MAX_FILE 


EQU 


2 







March 17, 1986 



20MB Fixed Disk Drive Adapter BIOS 25 



10/28/85 FI 



217 


0000 






2)8 


0000 


55 




219 


0001 


AA 




220 


0002 


08 




221 








222 








223 








224 








225 








226 








227 








228 








229 








230 








231 


0003 






232 


0003 


EB 


35 


233 


0005 


35 


39 58 37 32 39 


234 




31 


20 28 43 29 20 


235 




43 


4F 50 59 52 49 


236 




47 


48 54 20 49 42 


237 




4D 


20 20 43 4F 52 


238 




50 


2E 


239 


0025 


2C 


31 39 38 32 20 


240 




2C 


3 1 39 38 35 2E 


24 1 


0031 


20 


31 30 2F 32 38 


242 




2F 


38 35 


243 


003A 






244 


003A 


2B 


CO 


245 


003C 


8E 


D8 


246 


00 3E 


FA 




247 


003F 




004C R 


246 


0042 


A3 


0100 R 


249 


0045 




004E R 


250 


0048 


A3 


102 R 


251 


004B 


C7 


06 004C R 0251 R 


252 


0051 


8C 


OE 004E R 


253 


0055 


B8 


755 R 


254 


0058 


A3 


0034 R 


255 


005B 


8C 


OE 0036 R 


256 


005F 


C7 


06 0064 R 0192 R 


257 


0065 


8C 


OE 0066 R 


258 


0069 


C7 


06 0104 R 03FF R 


259 


006F 


8C 


OE 106 R 


260 


0073 


FB 




26 1 








262 








263 


0074 


B8 


R 


264 


0077 


8E 


D8 


265 


0079 


C6 


06 0074 R 00 


266 


007E 


C6 


06 0075 R 00 


267 


0083 


C6 


06 0077 R 00 


268 


0088 


B9 


0025 


269 


008B 






270 


008B 


E8 


01 77 R 


271 


008E 


73 


05 


272 


0090 


E2 


F9 


273 


0092 


E9 


154 R 


274 


0095 






275 


0095 


B9 


0001 


276 


0098 


BA 


0080 


277 


009B 


B8 


1200 


278 


009E 


CD 


13 


279 


OOAO 


73 


03 


280 


00A2 


E9 


154 R 


28 1 


00A5 






282 


00A5 


B8 


1400 


283 


00A8 


CD 


13 


284 


OOAA 


73 


03 


285 


OOAC 


E9 


154 R 


286 


OOAF 






287 


OOAF 


C7 


06 006C R 0000 


288 


00B5 


81 


3E 0072 R 1234 


289 


OOBB 


75 


06 


290 


OOBD 


C7 


06 006C R 019A 


29 1 


00C3 






292 


00C3 


FA 




293 


00C4 


E4 


21 


294 


00C6 


24 


FE 


295 


00C8 


E6 


21 


296 


OOCA 


FB 




297 


OOCB 






298 


OOCB 


E8 


177 R- 


299 


OOCE 


72 


07 


300 


OODO 


B8 


1000 


301 


00D3 


CD 


13 


302 


00D5 


73 


OA 


303 


00D7 






304 


00D7 




006C R 


305 


OODA 


3D 


01 BE 


306 


OODD 


72 


EC 


307 


OODF 


EB 


73 


308 


00E1 






309 


00E1 


B8 


1 too 


310 


00E4 


CD 


13 


31 1 


00E6 


72 


6C 


312 








313 


00E8 


B8 


0900 


314 


OOEB 


CD 


13 


315 


00 ED 


72 


65 


316 








317 


OOEF 


B8 


C800 


318 


00F2 


8E 


CO 


319 


00F4 


2B 


DB 


320 


00F6 


B8 


OFOO 


321 


00F9 


CD 


13 


322 


OOFB 


72 


57 


323 








324 


OOFD 


FE 


06 0075 R 


325 


0101 


BA 


0213 


326 


104 


BO 


00 


327 


106 


EE 




328 


0107 


BA 


0321 



CS:CODE,DS:ABS0 

OH 

055H 

OAAH 

08D 



; GENERIC BIOS HEADER 
; 4K MODULE 



XED DISK I/O SETUP 

ESTABLISH TRANSFER VECTORS FOR THE FIXED DISK 
■ PERFORM POWER ON DIAGNOSTICS 

SHOULD AN ERROR OCCUR A "1701" MESSAGE IS DISPLAYED 



DISK SETUP 



PROC 
SHORT 
•59X7291 



MOV 
MOV 
MOV 
MOV 



MOV 
MOV 
MOV 
MOV 



MOV 
MOV 
MOV 
MOV 

CALL 
JNC 
LOOP 
JMP 

MOV 
MOV 

MOV 



(C) COPYRIGHT IBM CORP. 



• , 1982 , 1985. ' 
• 10/28/85' 



AX, WORD PTR ORG_VECTOR 

WORD PTR DISK_VECTOR,AX 

AX, WORD PTR 0RG_VECT0R+2 

WORD PTR DISK_VECT0R+2,AX 

WORD PTR ORG_VECTOR, OFFSET DISK_IO 

WORD PTR 0RG_VECT0R+2,CS 

AX, OFFSET HD_1NT 

WORD PTR HDISK_INT,AX 

WORD PTR HDISK_INT+2,CS 

WORD PTR BOOT_VEC, OFFSET BOOT_STRAP 

WORD PTR B00T_VEC+2,CS 

WORD PTR HF_TBL_VEC,OFFSET FD_TBL 

WORD PTR HF_TBL_VEC+2,CS 



COPYRIGHT NOTICE 



; RELEASE MARKER 



ADDRESS LOW RAM 



LOAD DISKETTE IP 
STORE AT INT 40H 
LOAD DISKETTE CS 
STORE AT INT 40H 
FIXED DISK HANDLER 
AT INT I3H 



BOOTSTRAP ROUTINE , 



DS:DATA 

AX, DATA 

DS,AX 

DISK_STATUS,0 

HF_NUM , 

PORT_OFF,0 

CX,25H 

HD_RESET_1 



JMP 


ERROR_EX 


MOV 


TIMER LOW.O 


CMP 


RESET FLAG, 1 234H 


JNE 


P8 


MOV 


TIMER_LOW,4IOD 


CLI 




IN 


AL, INTA01 


AND 


AL,OFEH 


OUT 


INTAOI ,AL 


STI 




CALL 


HD RESET 1 


JC 


P10 


MOV 


AX, lOOOH 


INT 


13H 


JNC 


P2 


MOV 


AX, TIMER LOW 


CMP 


AX,446D 


JB 


P4 


JMP 


SHORT ERROR_EX 


MOV 


AX, 1 100H 


INT 


I3H 


JC 


ERROR_EX 


MOV 


AX,0900H 


INT 


13H 


JC 


ERROR_EX 


MOV 


AX,0C800H 


MOV 


ES.AX 


SUB 


BX,BX 


MOV 


AX.OFOOH 


INT 


13H 


JC 


ERROR_£X 


INC 


HF NUM 


MOV 


DX,213H 


MOV 


AL,0 


OUT 


DX,AL 


MOV 


DX,321H 



ESTABLISH SEGMENT 

RESET THE STATUS INDICATOR 
ZERO COUNT OF DRIVES 
, ZERO CARD OFFSET 
RETRY COUNT 

RESET CONTROLLER 

; TRY RESET AGAIN 



CONTROLLER DIAGNOSTICS 
CHECK THE INTERNAL RAM 
BUFFERS 



CONTROLLER DIAGNOSTICS 
INTERNAL CHECKSUM AND 
ECC CIRCUITRY TEST. 



SKIP WAIT ON RESET 

DISABLE INTERRUPTS 
TIMER 

ENABLE TIMER 
START TIMER 
INTERRUPTS ON 

RESET CONTROLLER 



25 SECONDS 



RECALIBRATE THE DRIVE 



WRITE SECTOR BUFFER 



26 20MB Fixed Disk Drive Adapter BIOS 



March 17, 1986 



332 
333 
334 
335 
336 
337 
338 
339 
340 
341 
342 
343 
344 
345 
346 
347 
348 
349 
350 
351 
352 
353 
354 
355 
356 
357 
358 
359 
360 
361 
362 
363 
364 
365 
366 
367 
368 
369 
370 
371 
372 
373 
374 
375 
376 
377 
378 
379 
380 
38 1 
382 
383 
384 
385 
386 
387 
388 
389 
390 
391 
392 
393 
394 
395 
396 
397 
398 
399 
400 



I 24 OF 
I 3C OF 

74 06 

C7 06 006C I 



123 2B CO 
125 CD 13 
0127 72 42 



too 

; CD 13 

: 73 OA 

I Al 006C R 

1 3D 1 BE 

. 72 EB 

i EB 31 

I 88 0900 

I CD 13 

■ 72 2A 

FE 06 0075 R 

< 81 FA 0081 

I 73 20 



MOV 
MOV 
OUT 



MOV 
INT 
JNC 
MOV 
CMP 



AL.DX 
AL.OFH 
AL.OFH 
BOX_ON 
TIMER_LOW,420D 

DX,2I3H 



POD_DONE 
AX, 01 100H 
13H 



SHORT POD_DONE 



0I4C EB D5 



154 

154 BD OOOF 

157 2B F6 

0159 B9 0006 

0I5C B7 00 

0I5E 

15E 

163 

165 

0167 

168 

0I6A 

0I6B 

0I6B 

0I6C I 

16E I 

01 70 I 
0172 f 
173 E8 0232 R 
176 CB 



JC 


POD DONE 


INC 


HF NUM 


CMP 


DX, (80H + S MAX FILE 


JAE 


POD DONE 


INC 


DX 


JMP 


P3 


DB 


• 1 701 • ,ODH,OAH 



ERROR_EX! 

MOV 
SUB 
MOV 
MOV 

OUT_CH: 

MOV 
MOV 
INT 
INC 
LOOP 
STC 



: E4 21 

: OC 1 

E6 2 1 



0177 

0177 51 

0178 52 

179 B9 100 

17C 

017C E8 076D R 

17F 42 

180 EE 

181 EB 00 

183 EB 00 

185 EB 00 

187 EC 

188 24 3F 

0I8A 74 03 



AL,CS!F17[SI ] 



AL, INTAOI 
AL,OIH 
INTAOI ,AL 



CX,OIOOH 



403 018F 

404 18F 

405 0190 

406 0191 I 

407 0192 

408 192 



OUT 


DX.AL 


JMP 


S + 2 


JMP 


$ + 2 


JMP 


$ + 2 


IN 


AL,DX 


AND 


AL.OO 


JZ 


R3 


LOOP 


L6 


STC 




R3: 




POP 


DX 


POP 


CX 


RET 




HD RESET 1 


ENDP 


DISK SETUP 


ENDP 



IS IN THE SYSTEM UNIT 



; CONTROLLER IS IN SYSTEM UNIT 
; EXPANSION BOX 



RESET THE CONTROLLER 



; RECALIBRATE THE DRIVE 



25 SECONDS 



; TALLY ANOTHER DRIVE 



POST MESSAGE 



POD ERROR FLAG 



GET BYTE 
VIDEO OUT 
DISPLAY CHARACTER 
NEXT CHAR 
DO MORE 



; NO INTERRUPTS 

; READ THE INTERRUPT MASK 

; DISABLE THE TIMER 



SAVE REGISTER 
RETRY COUNT 



; ADDRESS P0RT_1 

; RESET CARD 

; I/O DELAY AT LEAST +5us 

; ALLOW TIME TO CLEAR THE 

; HARDWARE STATUS REGISTER 

; READ THE HARDWARE STATUS 

; MASK OFF UPPER 2 BITS AND CLEAR CY 

: EXIT IF REGISTER IS CLEARED WITH CY= 

; TRY AGAIN 

; SET ERROR CONDITION CY=1 

; RESTORE REGISTER 



March 17, 1986 



20MB Fixed Disk Drive Adapter BIOS 27 



INT 19 H 

INTERRUPT 19 BOOT STRAP LOADER 

- THE FIXED DISK BIOS REPLACES THE INTERRUPT I 9H BOOT 

STRAP VECTOR WITH A POINTER TO THIS BOOT ROUTINE AND 
RESETS THE DEFAULT DISK AND DISKETTE PARAMETER VECTORS 



422 










423 










424 










425 










426 










427 










428 










429 










430 










43 1 










432 


192 








433 










434 


0192 


2B 


CO 




435 


194 


8E 


D8 




436 


196 


B4 


CO 




437 


198 


CD 


15 




438 










439 










440 










441 


0I9A 


FA 






442 


198 


07 


06 104 R 03FF 


R 


443 


01A1 


8C 


OE 106 R 




444 


0IA5 


73 


OA 




445 










446 


01A7 


C7 


06 0078 R 0227 


R 


44 7 


1 AD 


8C 


OE 007A R 




448 


OIBI 








449 


01B1 


FB 






450 










451 










452 










453 


0IB2 


2B 


D2 




454 










455 










456 










457 


0IB4 


8E 


C2 




458 


0IB6 


BB 


7C00 R 




459 










460 










46 1 










462 


0IB9 


FC 






463 


OIBA 


33 


CO 




464 


OIBC 


B9 


0100 




465 


OIBF 


8B 


FB 




466 


oict 


F3 


AB 




467 










468 


0IC3 


B9 


0004 




469 


0IC6 








470 


0tC6 


51 






471 


01C7 


2B 


CO 




472 


01C9 


CD 


13 




473 


1CB 


72 


08 




474 










475 


1 CD 


B8 


0201 




476 


01D0 


B9 


0001 




477 


0ID3 


CD 


13 




478 


01D5 


59 






479 


0ID6 


73 


09 




480 










48 t 


0ID8 


80 


FC 80 




482 


OIDB 


74 


22 




483 










484 


OtDD 


E2 


E7 




485 


OIDF 


EB 


IE 




486 










487 


01E1 


80 


3E 7C00 R 06 




488 


01E6 


72 


3D 




489 










490 










49 1 










492 


01E8 


BF 


7C00 R 




493 


1EB 


B9 


0008 




494 


OIEE 


Al 


7C00 R 




495 










496 


01F1 


83 


C7 02 




497 


0IF4 


3B 


05 




498 


0IF6 


El 


F9 




499 


0IF8 


74 


2B 




500 


OIFA 








501 


OIFA 


EA 


7C00 R 




502 










503 










504 










505 


1FF 








506 


1FF 


2B 


CO 




507 


0201 


CD 


13 




508 


0203 


B9 


0003 




509 


0206 


BA 


0080 




510 


0209 








51 1 


0209 


51 






512 


020A 


2B 


CO 




513 


020C 


CD 


13 




514 


020E 


72 


08 




515 










516 










51 7 










518 


0210 


B8 


0201 




519 


0213 


B9 


0001 




520 


0216 


CD 


13 




52 1 


0218 


59 






522 


0219 


72 


08 





THE BOOTSTRAP SEQUENCE IS: 

ATTEMPT TO LOAD FROM THE DISKETTE INTO THE BOOT 
LOCATION (000O:7CO0H) WHERE CONTROL IS TRANSFERRED. 

IF THE DISKETTE FAILS THE FIXED DISK IS TRIED FOR A 
VALID BOOTSTRAP BLOCK. A VALID BOOT BLOCK ON THE 
FIXED DISK CONSISTS OF THE BYTES 055H OAAH AS THE 
LAST TWO BYTES OF THE BLOCK. 

IF THE ABOVE FAILS CONTROL IS PASSED TO RESIDENT BASIC 



BOOT_STRAP: 

ASSUME DS:ABS0,ES:ABS0 

SUB AX, AX 

MOV DS.AX 

MOV AH.OCOH 



INT 



I5H 



RESET PARAMETER VECTORS 



STI 

ATTEMPT BOOTSTRAP FROM DISKETTE 

SUB DX.DX 

ESTABLISH ES:BX POINTER 



ESTABLISH SEGMENT 

READ CONFIGURATION PARAMETERS 
IF XT OR PC, INTERRUPTS ARE DISABLED 
AT THIS POINT. 



INT 15 FUNCTION IMPLEMENTED 



MOV 


ES.DX 


MOV 


BX, OFFSET BOOT_LOCN 


CLEAR 


BOOT_LOCN 


OLD 




XOR 


AX, AX 


MOV 


CX,256 


MOV 


DI ,BX 


REP 


STOSW 


MOV 


CX,4 


PUSH 


CX 


SUB 


AX, AX 


INT 


13H 


JC 


H2 


MOV 


AX,020IH 


MOV 


CX, 1 


INT 


I3H 


2: POP 


CX 


JNC 


H3 



DRIVE ZERO 



DIRECTION FORWARD 

CLEAR 256 WORDS 

POINT TO BOOT LOCATION BUFFER 

ZERO THE BOOT LOCATION BUFFER 

SET RETRY COUNT 

IPL_SYSTEM 

SAVE RETRY COUNT 

RESET THE DISKETTE 

FILE 10 CALL 

IF ERROR, TRY AGAIN 

READ IN THE SINGLE SECTOR 

SECTOR I , TRACK 

FILE 10 CALL 

RECOVER RETRY COUNT 

CARRY FLAG SET BY UNSUCCESSFUL READ 



MP SHORT H6 

MP BYTE PTR BOOT_LOCN , 061 
B H10 

NSURE DATA PATTERN FIRST 8 WORDS NOT ALL EQUAL 



MOV 
MOV 
MOV 

ADD 
CMP 
LOOPZ 



D I, OFFSET BOOT_LOCN 

CX,8 

AX, WORD PTR BOOT_LOCN 



CHECK DATA PATTERN 
CHECK THE NEXT 8 WORDS 
LOAD THE FIRST WORD 



BOOT NOT VALID, GO TO BASIC 



JMP BOOT_LOCN 

ATTEMPT BOOTSTRAP FROM FIXED DISK 



MOV 


CX,3 


MOV 


DX,0080H 


PUSH 


CX 


SUB 


AX, AX 


INT 


I3H 


JC 


H8 


ES AND 


BX ALREAD 


MOV 


AX,0201H 


MOV 


CX, 1 


INT 


13H 


8: POP 


CX 



RESET DISKETTE 

SET RETRY COUNT 

FIXED DISK ZERO 

IPL_SYSTEM 

SAVE RETRY COUNT 

RESET THE FIXED DISK 

FILE 10 CALL 

IF ERROR, TRY AGAIN 



READ IN THE SINGLE SECTOR 
SECTOR I , TRACK 
FILE 10 CALL 
RECOVER RETRY COUNT 



28 20MB Fixed Disk Drive Adapter BIOS 



March 17, 1986 



IBM 




Computer 


DISK2 --- 


- 10/28/85 F 


523 


02IB 


A1 


7DFE R 


524 


02IE 


3D 


AA55 


525 


022 1 


74 


D7 




526 


0223 








527 


0223 


E2 


E4 




528 










529 










530 










531 


0225 








532 


0225 


CD 


18 




533 










534 


0227 








535 










536 


0227 


CF 






537 


0228 


02 






538 


0229 


25 






539 


022A 


02 






540 


022B 


08 






541 


022C 


2A 






542 


022D 


FF 






543 


022E 


50 






544 


022F 


F6 






545 


0230 


19 






546 


0231 


04 






547 










548 










549 










550 


0232 








551 


0232 


2A 


CO 




552 


0234 


BA 


0323 


553 


0237 


FA 






554 


0238 


EE 






555 


0239 


83 


C2 


04 


556 


023C 


EE 






557 


023D 


83 


C2 


04 


558 


0240 


EE 






559 


024 1 


83 


C2 


04 


560 


0244 


EE 






56 1 










562 


0245 


BO 


07 




563 


0247 


E6 


OA 




564 


0249 


E4 


21 




565 


024B 


OC 


20 




566 


024D 


E6 


21 




567 


024F 


FB 






568 


0250 


C3 






569 


0251 








570 










571 










572 










573 










574 










575 










576 










577 


0251 








578 










579 


0251 


80 


FA 


80 


580 


0254 


73 


05 




58 1 


0256 


CD 


40 




582 


0258 








583 


0258 


CA 


0002 


584 










585 


025B 








586 


025B 


FB 






587 


025C 


OA 


E4 




588 


025E 


75 


09 




589 


0260 


CD 


40 




590 


0262 


2A 


E4 




591 


0264 


80 


FA 


81 


592 


0267 


77 


EF 




593 


0269 








594 


0269 


80 


FC 


08 


595 


026C 


75 


03 




596 


026E 


E9 


0380 R 


597 


0271 








598 


0271 


55 






599 


0272 


8B 


EC 




600 


0274 


83 


EC 


08 


601 










602 


0277 


53 






603 


0278 


51 






604 


0279 


52 






605 


027A 


IE 






606 


027B 


06 






607 


027C 


56 






608 


027D 


57 






609 


027E 


BE 




- R 


610 


028 1 


8E 


DE 




61 1 










612 


0283 


E8 


0200 R 


613 










614 


0286 


50 






615 


0287 


E8 


0232 R 


616 


028A 


B8 




- R 


617 


028D 


8E 


08 




618 


028F 


58 






619 


0290 


8A 


26 


0074 R 


620 


0294 


5F 






621 


0295 


5E 






622 


0296 


07 






623 


0297 


IF 






624 


0298 


5A 






625 


0299 


59 






626 


029A 


5B 






627 










628 


029B 


83 


C4 


08 


629 


029E 


50 






630 


029F 


80 


FC 


01 


631 


02A2 


F5 






632 


02A3 


CA 


0002 


633 


02A6 









MOV AX, WORD PTR B00T_L0CN + 5 I 00 
CMP AX,0AA55H 
JZ H5 

LOOP H7 ; DO IT FOR RETRY TIMES 

UNABLE TO I PL FROM THE DISKETTE OR FIXED DISK 

INT I8H ; RESIDENT BASIC 



DISKETTE TBL! 



1 1001 

2 

25H 



02AH 
OFFH 
050H 
0F6H 



SRT=D, HD UNLOAD=OF - 1ST SPEC BYTE 

HD L0A0=1, MODE=OMA - 2ND SPEC BYTE 

MOTOR TIMEOUT AFTER OPERATION 

512 BYTES PER SECTOR 

EOT (LAST SECTOR ON TRACK) 

GAP LENGTH 

DTL 

GAP LENGTH FOR FORMAT 

FILL BYTE FOR FORMAT 

HEAD SETTLE TIME (M ILL I SECONDS 1 

MOTOR START TIME (1/8 SECOND) 



MAKE SURE THAT ALL HOUSEKEEPING IS DONE BEFORE EXIT 



PROC 

SUB 

MOV 

CLI 

OUT 

ADD 

OUT 

ADD 

OUT 

ADD 

OUT 



ENDP 
DISK_IO 



NEAR 

AL.AL 

DX,HF_PORT+ 

DX.AL 
OX, 4 
DX.AL 
OX, 4 
DX.AL 
OX, 4 
DX.AL 

AL,07H 
DMA+I0,AL 
AL, INTAOI 
AL,020H 
INTAOI ,AL 



XED DISK BIOS ENTRY POINT 



; RESET INT/DMA MASK 

; LOAD FOR PORT_ADDRESS 3 

: DISABLE INTERRUPTS 

; RESET INT/DMA MASK CARD 

; RESET INT/DMA MASK CARD 1 

; RESET INT/DMA MASK CARD 2 

; RESET INT/DMA MASK CARD 3 

; SET DMA MODE TO DISABLE 



DISK 10 PROC 


FAR 


ASSUME 


OS : DATA, ES: NOTHING 


CMP 


DL,080H 


JAE 


HARD DISK 


INT 


40H 


RET 2: 




RET 


2 


HARD DISK: 




ST I 




OR 


AH, AH 


JNZ 


A3 


INT 


40H 


SUB 


AH, AH 


CMP 


DL, (80H+S MAX FILE 


JA 


RET_2 


A3: 




CMP 


AH, 8 


JNZ 


A2 


JMP 


GET_PARM_N 


A2: 




PUSH 


BP 


MOV 


BP,SP 


SUB 


SP,8 


PUSH 


BX 


PUSH 


CX 


PUSH 


OX 


PUSH 


OS 


PUSH 


ES 


PUSH 


SI 


PUSH 


Dl 


MOV 


SI .DATA 


MOV 


OS, SI 


CALL 


DISK_IO_CONT 


PUSH 


AX 


CALL 


DSBL 


MOV 


AX, DATA 


MOV 


OS, AX 


POP 


AX 


MOV 


AH, DISK STATUS 


POP 


DI 


POP 


SI 


POP 


ES 


POP 


OS 


POP 


DX 


POP 


CX 


POP 


BX 


ADD 


SP,8 


POP 


BP 


CMP 


AH, 1 


CMC 




RET 


2 


DISK 10 ENDP 





; TEST FOR FIXED DISK OR I V 

; YES, HANDLE HERE 

; DISKETTE HANDLER 

; BACK TO CALLER 



ENABLE INTERRUPTS 



RESET NEC WHEN AH=0 



DL IN LIMITS? 



GET PARAMETERS 



SPECIAL CASE 



SAVE THE BASE POINTER 

LOAD THE CMD_BLOCK POINTER 

ALLOCATE SPACE FOR THE COMMAND BLOCK 

ON THE STACK. 
SAVE REGISTERS DURING OPERATION 



ESTABLISH DATA SEGMENT 
PERFORM THE OPERATION 



BE SURE DISABLES OCCURRED 

ESTABLISH SEGMENT 
RESTORE THE REGISTERS 
GET STATUS FROM OPERATION 



ADJUST FOR THE COMMAND BLOCK. 

RESTORE BASE POINTER 

SET THE CARRY FLAG TO INDICATE 

SUCCESS OR FAILURE 
THROW AWAY SAVED FLAGS 



March 17, 1986 



20MB Fixed Disk Drive Adapter BIOS 29 



IBM 


Personal Comput 


sr MACRO Assembl 


DISK2 --- 


- 10/28/85 


FIXED DISK BIOS 


634 








PAGE 


635 


02A6 








636 


02A6 


032E 


R 




637 


02A8 


0347 


R 




638 


02AA 


0350 


R 




639 


02AC 


0359 


R 




640 


02AE 


0362 


R 




641 


02B0 


0369 


R 




642 


0282 


036F 


R 




643 


0284 


0375 


R 




644 


0286 


0326 


R 




645 


02B8 


043F 


R 




646 


02BA 


04F4 


R 




647 


028C 


0501 


R 




648 


028E 


0515 


R 




649 


02C0 


032E 


R 




650 


02C2 


05IB 


R 




651 


02C4 


0527 


R 




652 


02C6 


0533 


R 




653 


02C8 


0539 


R 




654 


02CA 


053F 


R 




655 


02CC 


0545 


R 




656 


02CE 


054B 


R 




657 


= 002A 




MIL 


658 










659 


02D0 






DISK_I 


660 


02D0 


80 FC 01 




661 


02D3 


74 72 




662 










663 


02D5 


80 EA 80 




664 


02D8 


80 FA 08 




665 


02DB 


73 49 




666 










667 


02DD 


C6 06 0074 


R 00 



SUB 
CMP 
JAE 



WORD 

DISK_RESET 

RETURN_STATUS 

DISK_READ 

DISK_WRITE 

DISK_VERF 

FMT_TRK 

FMT_8AD 

FMT_DRV 

BAD_COMMAND 

INIT_DRV 

RD_LONG 

WR_LONG 

DISK_SEEK 

DISK_RESET 

RD_BUFF 

WR_8UFF 

TST_RDY 

HDISK_RECAL 

RAM_D I AG 

CHK_DRV 

CNTLR DIAG 



RETURN_STATUS 

DL.OSOH 

DL,MAX_FILE 

BAD_COMMAND 

DISK_STATUS,0 



001H 
002H 
003H 
004H 
005H 
006H 
007H 
008H 
009H 
OOAH 
OOBH 
OOCH 
OODH 
OOEH 
OOFH 

1 OH 

01 IH 
12H 
13H 
14H 



; RETURN STATUS 



669 
670 




; SET 


671 


02E2 FE C9 


DEC 


672 


02E4 C6 46 F8 00 


MOV 


673 


02E8 88 4E FA 


MOV 


674 


02EB 88 6E FB 


MOV 


675 


02EE 88 46 FC 


MOV 


676 


02F1 AO 0076 R 


MOV 


677 


02F4 88 46 FD 


MOV 


678 
679 




: CALC 



680 
681 
682 
683 
684 
685 
686 
687 
688 
689 



692 
693 
694 
695 
696 
697 
698 
699 
700 
701 
702 
703 
704 
705 
706 
707 
708 
709 



SET UP COMMAND BLOCK 

CL 

CMD_BLOCK+0,0 

CMD_BL0CK+2,CL 

CMD_BL0CK+3,CH 

CMD_BL0CK+4,AL 

AL,CONTROL_BYTE 

CMD BL0CK+5,AL 



CALCULATE THE PORT OFFSET 



02F7 8A EA 

02F9 80 CA 1 

02FC FE CA 

02FE DO E2 

0300 88 16 0077 R 

0304 8A D5 

0306 80 E2 01 

0309 B1 05 

030B D2 E2 

030D OA D6 

030F 88 56 F9 



0312 
0314 
0316 
0318 
031A 
031C 
031F 
0321 
0326 
0326 
032B 
032D 
032E 



BB C8 

8A CD 

32 ED 

D1 El 

8B Fl 

83 F9 2A 

73 05 

2E: FF A4 02A6 R 



DEC 
SHL 
MOV 
MOV 
AND 
MOV 
SHL 



MOV 
MOV 
XOR 
SAL 
MOV 
CMP 
JNB 
JMP 

BAD_COMMAND: 
MOV 
MOV 
RET 

DISK 10 CONT 



DL, 1 

PORT_OFF,DL 

DL.CH 



DL.CL 
DL.DH 
CMD_BLOCK+ 

CX.AX 
CL.CH 
CH.CH 
CX, 1 
SI ,CX 

BAD COMMAND 



WORD PTR CS:[SI+OFFSET Ml] 
DISK_STATUS,BAD_CMD 



RESET THE STATUS INDICATOR 



; SECTORS 0-16 FOR CONTROLLER 

; SET TO ZERO THE OP CODE 

i SECTOR AND HIGH 2 BITS CYLINDER 

; CYLINDER LOW 

; INTERLEAVE / BLOCK COUNT 

; CONTROL BYTE (STEP OPTION) 

; SET THE CONTROL FIELD 



GENERATE OFFSET 

STORE OFFSET 

RESTORE DL 

MAKE DRIVE OR 1 

SHIFT COUNT 

DRIVE NUMBER (0,1) 

HEAD NUMBER 

SET THE DRIVE AND HEAD 

CALCULATE JUMP ADDRESS 
GET INTO LOW BYTE 
ZERO HIGH BYTE 
•2 FOR TABLE LOOKUP 
PUT INTO SI FOR BRANCH 
TEST WITHIN RANGE 

GO DO THE COMMAND 



; SET BAD COMMAND ERROR 
; EXIT 



RESET THE DISK SYSTEM 



716 
71 7 
718 



722 
723 
724 
725 
726 
727 
728 
729 
730 
731 
732 
733 
734 
735 
736 
737 
738 
739 
740 
741 
742 
743 
744 
745 
746 
747 



032E 

032E E8 076D R 

0331 42 

0332 EE 

0333 EB 00 
0335 EB 00 
0337 EB 00 
0339 EC 
033A 24 3F 
033C 74 06 

033E C6 06 0074 R 05 

0343 C3 
0344 

0344 E9 043F R 

0347 



0347 

0347 AO 0074 R 

034A C6 06 0074 R 00 

034F C3 

0350 



0350 

0350 BO 47 

0352 C6 46 F8 08 

0356 E9 055E R 

0359 



OUT 
JMP 
JMP 
JMP 



DISK_RESET 



DX 

DX.AL 
$ + 2 
$ + 2 
$ + 2 
AL.DX 
AL.OOI 



DR1 

D I SK_STATUS , BAD_RESET 



RESET PORT 

P0RT_1 ADDRESS 

RESET CARD 

I /O DELAY AT LEAST +5us 

ALLOW TIME TO CLEAR THE 

HARDWARE STATUS REGISTER 
READ THE HARDWARE STATUS 
MASK OFF UPPER 2 BITS AND CLEAR CY 
EXIT IF REGISTER IS CLEARED WITH CY=0 
SET THE ERROR CONDITION 
EXIT 

SET THE DRIVE PARAMETERS 



DISK STATUS ROUTINE 



. 

RETURN_STATUS 
MOV 
MOV 
RET 

RETURN_STATUS 



PROC NEAR 
AL,DISK_STATUS 
DISK STATUS, 



;- 



DISK READ ROUTINE 



(AH = 002H) 



DISK READ 


PROC NEAR 


MOV 


AL.DMA READ 


MOV 


CMD BLOCK+O.READ CMD 


JMP 


DMA OPN 


DISK READ 


ENDP 



MODE BYTE FOR DMA READ 



30 20MB Fixed Disk Drive Adapter BIOS 



March 17, 1986 



IBM 


Persona 


Computer MAC 


D1SK2 


10/28/85 FIXEC 


748 








750 
751 
752 


0359 






753 


0359 


BO 


4B 


754 


035B 


C6 


46 F8 OA 


755 


035F 


E9 


055E R 


756 
757 


0362 






758 
759 








760 








761 
762 


0362 






763 


0362 


C6 


46 F8 05 


764 


0366 


E9 


054F R 


765 


0369 






766 








767 








768 








769 








770 








771 


0369 






772 


0369 


C6 


46 F8 06 


773 


036D 


EB 


OA 


774 


036F 






775 








776 


036F 






777 


036F 


C6 


46 F8 07 


778 


0373 


EB 


04 


779 


0375 






780 








781 


0375 






782 


0375 


C6 


46 F8 04 


783 


0379 






784 








785 


0379 






786 


0379 


80 


66 FA CO 


787 


037D 


E9 


054F R 


788 








789 








790 








791 








792 








793 


0380 






794 


0380 






795 


0380 


IE 




796 


0381 


06 




797 


0382 


53 




798 








799 








800 


0383 


2B 


CO 


801 


0385 


8E 


D8 


802 


0387 


C4 


IE 0104 R 


803 








804 








805 


038B 


B8 


R 


806 


038E 


8E 


08 


807 


0390 


80 


EA 80 


808 


0393 


80 


FA 08 


809 


0396 


73 


57 


810 


0398 


C6 


06 0074 R 00 


81 1 


039D 


8A 


EA 


812 


039F 


80 


CA 1 


813 


03A2 


FE 


CA 


814 


03A4 


DO 


E2 


815 


03A6 


88 


16 0077 R 


816 


03AA 


8A 


05 


817 


03AC 


80 


E2 1 


818 


03AF 


8A 


E2 


819 


03B1 


E8 


0760 R 


820 


03B4 


42 




821 


03B5 


42 




822 


03B6 


EC 




823 


03B7 


80 


FC 00 


824 


03BA 


75 


04 


825 


3BC 


DO 


E8 


826 


3BE 


DO 


E8 


827 


03C0 






828 


03C0 


24 


03 


829 


03C2 


Bl 


04 


830 


03C4 


D2 


EO 


831 


03C6 


2A 


E4 


832 


03C8 


03 


08 


833 


03CA 


26 


8B 07 


834 


3CD 


2D 


0002 


835 








836 


03DO 


8A 


E8 


837 


03D2 


25 


0300 


838 


03D5 


Dl 


E8 


839 


03D7 


Dl 


E8 


840 


03D9 


OC 


1 1 


841 


03DB 


8A 


C8 


842 


03DD 


26 


8A 77 02 


843 


03E1 


FE 


CE 


844 


03E:3 


8A 


16 0075 R 


845 


03E7 


2B 


CO 


846 


03E9 






847 


03E9 


5B 




848 


3EA 


07 




849 


3EB 


IF 




850 


3EC 


CA 


0002 


851 


3EF 






852 


03EF 


C6 


06 0074 R 07 


853 


03F4 


B4 


07 


854 


03F6 


2A 


CO 


855 


03F8 


2B 


D2 


856 


03FA 


28 


C9 


857 


03FC 


F9 




858 


03FD 


EB 


EA 


859 


3FF 







MACRO Assemb 



DISK WRITE ROUTINE 



OISK_WRITE 
MOV 
MOV 
JMP 

DISK WRITE 



PROC NEAR 

AL,DMA_WRITE 

CMD_BLOCK + , WR I TE_CMD 

OMA_OPN 

ENDP 



MODE BYTE FOR DMA WRITE 



DISK VERIFY 



DISK VERF 



PROC NEAR 

CMD_BLOCK+0,CHK_TRK_CMD 

NDMA_OPN 

ENDP 



FORMATTING 



FMT_TRK ENDP 

FMT_BAD PROC 
MOV 
JMP 

FMT_BAD ENDP 

FMT_DRV PROC 

MOV 
FMT DRV ENDP 



NEAR 

CMD_BLOCK + , FMTTRK_CMD 

SHORT FMT CONT 



005H 006H 007H) : 

; FORMAT TRACK (AH = 005H) 



NEAR 

CMD_BLOCK+0 , FMTBAD_CMD 

SHORT FMT_CONT 



GET PARAMETERS 



PUSH 
PUSH 
PUSH 



ASSUME 
SUB 
MOV 
LES 

ASSUME 

MOV 

MOV 

SUB 

CMP 

JAE 

MOV 

MOV 

OR 

DEC 

SHL 

MOV 

MOV 

AND 

MOV 

CALL 

INC 

INC 

IN 

CMP 

JNZ 

SHR 

SHR 

AND 
MOV 
SHL 
SUB 
ADD 
MOV 
SUB 

MOV 

AND 

SHR 

SHR 

OR 

MOV 

MOV 

DEC 

MOV 

SUB 

POP 
POP 
POP 
RET 

MOV 
MOV 
SUB 
SUB 
SUB 
STC 



DS:ABSO 

AX, AX 

DS.AX 

BX,HF_TBL_VEC 

DS:DATA 

AX, DATA 

DS.AX 

DL,80H 

DL,MAX_FILE 

G4 

DISK_STATUS,0 

CH,DL 

DL, I 

DL 

DL, 1 

PORT_OFF,DL 

DL,CH 

DL,0000000IB 

AH,DL 

PORT 



OX 
OX 



AL, 0000001 
CL,4 
AL,CL 
AH, AH 



CH,AL 
AX,0300H 
AX, 1 
AX, I 



D I SK_STATUS , I N I T_FA I L 

AH, INIT_FAIL 

AL.AL 

DX.DX 

CX.CX 

G5 



FORMAT BAD TRACK (AH = 006H) 



FORMAT DRIVE ( AH = 007H) 



ZERO OUT SECTOR FIELD 



ESTABLISH ADDRESSING 



; ESTABLISH SEGMENT 
; TEST WITHIN RANGE 



GENERATE OFFSET 
STORE OFFSET 
RESTORE DL 
DRIVE OR DRIVE 1 



PORT 2 ADDRESS 



RIGHT JUSTIFY THE SWITCH BITS 



ISOLATE THE TABLE BITS 
TABLE LENGTH IS 16 BYTES 
ADJUST 



MAX NUMBER OF CYLINDERS 

ADJUST FOR 0-N 

AND RESERVE LAST TRACK 

HIGH TWO BITS OF CYLINDER 



; HEADS 

; 0-N RANGE 

; DRIVE COUNT 



; RESTORE REGISTERS 

; EXIT 

; OPERATION FAILED 



March 17, 1986 



20MB Fixed Disk Drive Adapter BIOS 3 1 



862 






863 






864 






865 






866 






867 






868 






869 






870 






871 






872 






873 






874 






875 






876 






877 






878 






879 






880 






881 






882 






883 






884 






885 






886 






887 






888 






889 






890 






891 






892 






893 






894 






895 






896 






897 






898 






899 






900 






901 






902 






903 






904 






905 






906 






907 






908 






909 






910 






91 1 






912 






913 


03FF 




914 






915 






916 






91 7 


03FF 


132 


918 


0401 


04 


919 


0402 


132 


920 


0404 


0000 


921 


0406 


OB 


922 


0407 


05 


923 


0408 


10 


924 


0409 


CO 


925 


040A 


28 


926 


040B 


132 


927 


040D 




928 


040E 


00 


929 






930 






931 






932 


040F 


0264 


933 


041 1 


04 


934 


04 12 


0264 


935 


0414 


0000 


936 


04 16 


OB 


937 


04 17 


05 


938 


0418 


28 


939 


0419 


EO 


940 


041A 


42 


941 


041B 


0297 


942 


041D 


1 1 


943 


041E 


00 


944 






945 






946 






947 


041F 


0267 


948 


0421 


04 


949 


0422 


0267 


950 


0424 


12C 


951 


0426 


OB 


952 


0427 


05 


953 


0428 


28 


954 


0429 


EO 


955 


042A 


42 


956 


042B 


0267 


957 


042D 


1 1 


958 


042E 


00 


959 






960 






96 1 






962 


042F 


0132 


963 


0431 


08 


964 


0432 


0132 


965 


0434 


0080 


966 


0436 


OB 


967 


0437 


05 


968 


0438 


28 


969 


0439 


EO 


970 


043A 


42 


971 


043B 


0150 


972 


043D 




973 


043E 


00 



INITIALIZE DRIVE CHARACTERISTICS 
FIXED DISK PARAMETER TABLE 
- THE TABLE IS COMPOSED OF A BLOCK DEFINED AS: 



(1 WORD) 

(1 BYTE) 

(1 WORD) 

(I WORD) 

( 1 BYTE) 

(I BYTE) 



(I BYTE) 

(1 BYTE) 

(1 BYTE) 

(1 WORD) 

( 1 BYTE) 

(1 BYTE) 



MAXIMUM NUMBER OF CYLINDERS 

MAXIMUM NUMBER OF HEADS 

STARTING REDUCED WRITE CURRENT CYL 

STARTING WRITE PRECOMPENSAT ION CYL 

MAXIMUM ECC DATA BURST LENGTH 

CONTROL BYTE (DRIVE STEP OPTION) 

BIT 7 DISABLE DISK-ACCESS RETRIES 

BIT 6 DISABLE ECC RETRIES 

BITS 5-3 ZERO 

BITS 2-0 DRIVE OPTION 

STANDARD TIME OUT VALUE (SEE BELOW) 

TIME OUT VALUE FOR FORMAT DRIVE 

TIME OUT VALUE FOR CHECK DRIVE 

LANDING ZONE 

SECTORS/TRACK 

RESERVED FOR FUTURE USE 



TO DYNAMICALLY DEFINE A SET OF PARAMETERS 
BUILD A TABLE OF VALUES AND PLACE THE 
CORRESPONDING VECTOR INTO INTERRUPT 41. 



ON THE CARD SWITCH SETTINGS 

DRIVE DRIV 



TRANSLATION TABLE 



TABLE ENTRY 



ON ON 
ON OFF 
OFF ON 
OFF OFF 



ON ON 
ON OFF 
OFF ON 
OFF OFF 



DRIVE TABLE 

DW 0306D 

DB 04D 

DW 0306D 

DW 

DB OBH 

DB OOOOOK 

DB 01 OH 

DB OCOH 

DB 028H 

DW 0306D 

DB 1 7D 



DRIVE TABLE I 

DW 06 1 2D 

DB 04D 

DW 06 1 2D 

DW 

DB OBH 

DB 00000101B 

DB 028H 

DB OEOH 

DB 042H 

DW 0663D 

DB 01 70 



DRIVE TABLE 2 

DW 06 15D 

DB 04D 

DW 0615D 

DW 0300D 

DB OBH 

DB OOOOOK 

DB 028H 

DB OEOH 

DB 042H 
15D 



017D 



DRIVE TABLE 3 

DW 0306D 

DB 08D 

DW 0306D 

DW 0128D 

DB OBH 

DB 00000I01B 

DB 028H 

DB OEOH 

DB 042H 

DW 03360 



17D 



MAX CYLINDERS 

MAX HEADS 

START REDUCED WRITE CURRENT CYL 

START WRITE PRECOMPENSAT I ON CYL 

MAX ECC BURST DATA LENGTH 

CONTROL BYTE 

STANDARD TIME OUT 

TIME OUT FOR FORMAT DRIVE 

TIME FOR CHECK DRIVE 

LANDING ZONE 

SECTORS/TRACK 

RESERVED 



MAX CYLINDERS 

MAX HEADS 

START REDUCED WRITE CURRENT CYL 

START WRITE PRECOMPENSAT I ON CYL 

MAX ECC BURST DATA LENGTH 

CONTROL BYTE 

STANDARD TIME OUT 

TIME OUT FOR FORMAT DRIVE 

TIME FOR CHECK DRIVE 

LANDING ZONE 

SECTORS /TRACK 

RESERVED 



MAX CYLINDERS 

MAX HEADS 

START REDUCED WRITE CURRENT CYL 

START WRITE PRECOMPENSAT I ON CYL 

MAX ECC BURST DATA LENGTH 

CONTROL BYTE 

STANDARD TIME OUT 

TIME OUT FOR FORMAT DRIVE 

TIME FOR CHECK DRIVE 

LANDING ZONE 

SECTORS/TRACK 

RESERVED 



MAX CYLINDERS 

MAX HEADS 

START REDUCED WRITE CURRENT CYL 

START WRITE PRECOMPENSAT I ON CYL 

MAX ECC BURST DATA LENGTH 

CONTROL BYTE 

STANDARD TIME OUT 

TIME OUT FOR FORMAT DRIVE 

TIME FOR CHECK DRIVE 

LANDING ZONE 

SECTORS/TRACK 

RESERVED 



32 20MB Fixed Disk Drive Adapter BIOS 



March 17, 1986 



974 








975 








976 








977 








978 








979 


043F 






980 








981 








982 








983 


043F 


C6 


46 F8 OC 


984 


0443 


C6 


46 F9 00 


985 


0447 


E8 


0458 R 


986 


044A 


72 


OB 


987 








988 








989 








990 


044C 


C6 


46 F8 OC 


991 


0450 


C6 


46 F9 20 


992 


0454 


E8 


0458 R 


993 


0457 






994 


0457 


C3 




995 


0458 






996 








997 


0458 






998 


0458 


2A 


CO 


999 


045A 


E8 


057C R 


1000 


045D 


73 


01 


tool 


045F 


C3 




t002 


0460 






1003 


0460 


8C 


D9 


1004 








1005 








1006 


0462 


2B 


CO 


1007 


0464 


8E 


D8 


1008 


0466 


C4 


IE 104 R 


1009 


046A 


8E 


D9 



INITIALIZE DRIVE ( AH = 09H) 

:V PROC NEAR 
DO DRIVE ZERO 



SET FOR DRIVE 
SEND THE PARAMETERS 
ERROR? 



MOV 


CMD BLOCK+O.INIT DRV CMD 


MOV 


CMD BLOCK +1 ,0 


CALL 


INIT DRV R 


JC 


INIT_DRV_OUT 


DO DRIV 


E ONE 


MOV 


CMD BLOCK+O.INIT DRV CMD 


MOV 


CMD BLOCK+1 ,00 1000006 


CALL 


IN1T_DRV_R 


NIT DRV OUT: 




~ RET 




NIT_DRV 


ENDP 


NIT DRV R 


PROC NEAR 


- SUB 


AL.AL 


CALL 


COMMAND 


JNC 


Bl 


RET 




MOV 


CX.DS 


ASSUME 


DS:ABSO 


SUB 


AX, AX 


MOV 


DS.AX 


LES 


BX.HF TBL VEC 


MOV 


DS.CX 


ASSUME 


DS:DATA 



SAVE SEGMENT 



ESTABLISH SEGMENT 
LOAD THE TABLE VECTOR 
RESTORE SEGMENT 



DETERMINE PARAMETER TABLE OFFSET 
USING CONTROLLER PORT TWO AND 
DRIVE NUMBER SPECIFIER (0-1) 



1017 


046C 


42 








1018 


046D 


42 








1019 


046E 


EC 








1020 


046F 


8A 


66 F9 




1021 


0472 


80 


E4 20 




1022 


0475 


75 


04 






1023 


0477 


DO 


E8 






1024 


0479 


DO 


E8 






1025 


047B 










1026 


047B 


24 


03 






1027 


047D 


Bl 


04 






1028 


047F 


D2 


EO 






1029 


048 1 


2A 


E4 






1030 


0483 


03 


D8 






1031 


0485 


B4 


09 






1032 












1033 












1034 












1035 


0487 


BF 


0001 






1036 


048A 


E8 


04E9 


R 




1037 


048D 


72 


4C 






1038 












1039 


048F 


BF 


0000 






1040 


0492 


E8 


04E9 


R 




1041 


0495 


72 


44 






1042 












1043 


0497 


BF 


0002 






1044 


049A 


E8 


04E9 


R 




1045 


049D 


72 


3C 






1046 












1047 


049F 


BF 


0004 






1048 


04A2 


E8 


04E9 


R 




1049 


04A5 


72 


34 






1050 












1051 


04A7 


BF 


0003 






1052 


04AA 


E8 


04E9 


R 




1053 


04AD 


72 


2C 






1054 












1055 


04AF 


BF 


0006 






1056 


04B2 


E8 


04E9 


R 




1057 


04B5 


72 


24 






1058 












1059 


04B7 


BF 


0005 






1060 


04BA 


E8 


04E9 


R 




1061 


04BD 


72 


IC 






1062 












1063 


04BF 


BF 


0007 






1064 


04C2 


E8 


04E9 


R 




1065 


04C5 


72 








1066 












1067 


04C7 


BF 


0008 






1068 


04CA 


26 


8A 01 




1069 


04CD 


A2 


0076 


R 




1070 












1071 


04D0 


2B 


C9 






1072 


04D2 


B4 


OF 






1073 


04D4 










1074 


04D4 


E8 


068D 


R 




1075 


04D7 


73 


09 






1076 


04D9 


E2 


F9 






1077 


04DB 










1078 


04DB 


C6 


06 0074 R 07 


1079 


04E0 


F9 








1080 


04EI 


C3 








1081 


04E2 










1082 


04E2 


4A 








1083 


04E3 


EC 








1084 


04E4 


24 


02 






1085 


04E6 


75 


F3 






1086 


04E8 


C3 








1087 


04E9 











MOV 
AND 
JNZ 
SHR 
SHR 


AL.DX 

AH, CMD BLOCK+1 

AH,00100000B 

B2 

AL.I 

AL, 1 


AND 
MOV 
SHL 
SUB 
ADD 
MOV 


AL,OI IB 

CL,4 

AL,CL 

AH, AH 

BX,AX 

AH.OOOOIOOIB 


SEND DRIVE PARAMETERS M 


MOV 
CALL 
JC 


DI , 1 

INIT DRV S 

B3 


MOV 
CALL 
JC 


DI ,0 

INIT DRV S 

B3 


MOV 
CALL 
JC 


DI ,2 

INIT DRV S 

B3 


MOV 

CALL 
JC 


DI ,4 

INIT DRV S 

B3 


MOV 

CALL 
JC 


DI,3 

INIT DRV S 

B3 


MOV 
CALL 
JC 


DI ,6 

INIT DRV S 

B3 


MOV 

CALL 
JC 


DI ,5 

INIT DRV S 

B3 


MOV 

CALL 
JC 


Dl,7 

INIT DRV S 

B3 


MOV 
MOV 
MOV 


DI ,8 

AL,ES: [BX+DI ] 

CONTROL_BYTE,AL 


SUB 
MOV 


CX.CX 

AH, 00001 1 1 IB 


CALL 
JNC 
LOOP 


HD WAIT 

B6 

B5 


MOV 
STC 
RET 


DISK_STATUS, INI 


DEC 

AND 
JNZ 
RET 


DX 

AL.DX 
AL,2 
B3 



DRIVE OR 1 
ADJUST 

ISOLATE 
ADJUST 

SET MASK FOR DATA MODE CPU TO CARD 
ICANT BYTE FIRST 
SEND MSB OF MAX CYLINDER 

SEND LSB OF MAX CYLINDER 

SEND THE MAXIMUM HEADS 



SEND MSB OF WRITE PRECOMP CYLINDER 



SEND LSB OF WRITE PRECOMP CYLINDER 



SEND ECC BURST LENGTH 



SET THE MASK FOR STATU3 MODE 

GO WAIT FOR THE STATE TO HAPPEN 
JMP TO READ THE STATUS BYTE 
TRY AGAIN 



ADDRESS PORT 

READ STATUS BYTE OF THE OPERATION 

MASK ERROR BIT 

ERROR BIT SET? 



March 17, 1986 



20MB Fixed Disk Drive Adapter BIOS 33 



1088 
1089 
1090 

1091 04E9 

1092 04E9 E8 ( 

1093 04EC 72 ( 

1094 04EE 4A 

1095 04EF 26: 

1096 04F2 EE 

1097 04F3 

1098 04F3 C3 

1099 04F4 

1 too 

1101 
1 102 
1 103 
1 104 

1 105 04F4 

1 106 04F4 E8 ( 

1 107 04F7 72 ! 

1 108 04F9 C6 - 

1 109 04FD BO ' 

1110 04FF EB ! 

1111 0501 
1112 
1113 

1 1 14 
1115 
1116 

1117 0501 

1118 0501 E8 ( 

1119 0504 72 ! 

1 120 0506 C6 ■ 

1 121 050A 80 ' 

1 122 050C EB I 

1 123 050E 
1 124 

1 125 050E 

1 126 050E 8A ■ 

1 127 051 1 3C I 

1 128 0513 F5 

1 129 0514 C3 

1 130 0515 
1131 

1 132 
1 133 
I 134 
1 135 

1 136 0515 

1 137 0515 C6 ■ 

1 138 0519 EB : 

1 139 051B 
1 140 

1 141 



SEND THE BYTE OUT TO THE CONTROLLER 



INIT DRV S 

- CALL 


PROC NEAR 
HD WAIT 


JC 


D1 


DEC 


DX 


MOV 


AL,ES:[BX+DI 


OUT 


DX.AL 


RET 




INIT DRV S 


ENDP 



GO WAIT FOR REQUEST 

AFTER CALL DX = PORT 1 
ADDRESS PORT 

WRITE THE DATA TO THE CARD 



READ LONG 



(AH = OAH) 



MOV CMD_BLOCK + , RD_LONG_CMD 

MOV AL,DMA_READ 

JMP SHORT DMA_OPN 

RD LONG ENDP 



WRITE LONG 



CHECK LIMITS 



(AH = OBH) 



WR LONG 


PROC NEAR 


CALL 


CHK LONG 


JC 


G8 


MOV 
MOV 


CMD BLOCK +0,WR LONG CMD 
AL.DMA WRITE 


JMP 


SHORT DMA OPN 


WR_LONG 


ENDP 


CHK LONG 


PROC NEAR 


MOV 


AL.CMD BLOCK+4 


CMP 


AL,080H 


CMC 




RET 





; CHECK LIMITS 



; LOAD THE NUMBER OF SECTORS 
; COMPARE WITH LIMITS 
; SET THE CONDITION 



DISK_5EEK PROC NEAR 

MOV CMD_BLOCK+0,SEEK_CMD 

JMP SHORT NDMA_OPN 

DISK SEEK ENDP 



READ SECTOR BUFFER 



1 144 
1 145 


051B 












051B 


C6 


46 


F8 


OE 




051F 


C6 


46 


FC 


01 




0523 


BO 


47 






1 149 


0525 


EB 


37 






1 150 


0527 










1151 












1 152 












1 153 












1 154 












1 155 












1 156 


0527 










1 157 


0527 


C6 


46 


F8 


OF 


1 158 


052B 


C6 


46 


FC 


01 


1 159 


052F 


BO 


4B 






1 160 


0531 


EB 


?.B 






1 161 


0533 










1 162 












1 163 












1 164 












1 165 












1 166 












1 167 


0533 










1 168 


0533 


C6 


46 


F8 


CO 


1 169 


0537 


EB 


16 






1 170 


0539 










1171 












1 172 












1 173 












1 174 












1 175 












1 176 


0539 










1 177 


0539 


C6 


46 


F8 


01 


1 1 78 


053D 


EB 


10 






1 179 


053F 











RD_BUFF PROC NEAR 

MOV CMD_BLOCK+0,RD_BUFF_CMD 

MOV CMD_BL0CK+4, 1 

MOV AL,DMA_READ 

JMP SHORT DMA_OPN 
RD BUFF ENDP 



ONLY ONE BLOCK 



WRITE SECTOR BUFFER 



WR_BUFF PROC NEAR 

MOV CMD_BLOCK + , WR_BUFF_CMD 

MOV CMD_BL0CK+4, 1 ; ONLY ONE BLOCK 

MOV AL,DMA_WRITE 

JMP SHORT DMA OPN 
WR BUFF ENDP 



TEST DISK READY 



(AH = 1 OH) 



TST RDY ENDP 



NEAR 

CMD_BLOCK + , T ST_RDY_CMD 

SHORT NOMA OPN 



RECALIBRATE 



PROC NEAR 
CMD_BLOCK+0,RECAL_CMD 



HD I SK_RECAL 



34 20MB Fixed Disk Drive Adapter BIOS 



March 17, 1986 



1 182 

I 183 

1 184 

1 185 053F 

I 186 053F C6 46 F8 EO 

I 187 0543 EB OA 

1 188 0545 

1 189 

I 190 

1 191 

I 192 

1 193 

I 194 0545 

I 195 0545 C6 46 F8 E3 

1 196 0549 EB 04 

I 197 054B 

1 198 

I 199 

1200 

1201 

1202 

1203 054B 

1204 054B C6 46 F8 E4 

1205 054F 
1206 
1207 
1208 
1209 
1210 

1211 054F 

1212 054F BO 02 

1213 0551 E8 057C R 

1214 0554 72 22 

1215 0556 EB 16 
12 16 0558 

1217 0558 C6 06 0074 R 09 

1218 055D C3 

1219 055E 

1220 055E E8 06A5 R 

1221 0561 72 F5 

1222 0563 BO 03 

1223 0565 E8 057C R 

1224 0568 72 OE 

1225 056A BO 03 

1226 056C E6 OA 

1227 056E 

1228 056E FA 

1229 056F E4 21 

1230 057 1 24 DF 

1231 0573 E6 21 

1232 0575 E8 0700 R 

1233 0578 

1234 0578 E8 05AD R 

1235 057B C3 
1236 

1237 
1238 
1239 
1240 
1241 
1242 
1243 
1244 

1245 057C 

1246 057C E8 076D R 

1247 057F 42 

1248 0580 42 

1249 0581 EE 

1250 0582 42 

1251 0583 2B C9 

1252 0585 EE 

1253 0586 4A 

1254 0587 4A 

1255 0588 

1256 0588 EC 

1257 0589 24 OF 

1258 058B 3C OD 

1259 058D 74 09 

1260 058F E2 F7 

1261 0591 C6 06 0074 R 80 

1262 0596 F9 

1263 0597 C3 

1264 0598 

1265 0598 B9 0006 

1266 059B 4A 

1267 059C 8B F5 

1268 059E 83 ED 08 

1269 05A1 FA 

1270 05A2 

127 1 05A2 8A 46 00 

1272 05A5 EE 

1273 05A6 45 

1274 05A7 E2 F9 

1275 05A9 8B EE 

1276 05AB FB 

1277 05AC C3 

1278 05AD 



CHK_DRV ENDP 



CONTROLLER RAM DIAGNOSTICS 



PROC NEAR 

CMD_BLOCK + , RAM_D I AG_CMD 

SHORT NDMA_OPN 

ENDP 



DRIVE DIAGNOSTICS 



NEAR 

CMD_BLOCK+0 , CHK_DRV_CMD 

SHORT NDMA_OPN 



CONTROLLER INTERNAL DIAGNOSTICS 



(AH = 14H) 



CNTLR_D1AG 

MOV 
CNTLR_DIAG 



NDMA_OPN: 

MOV 
CALL 



PROC NEAR 

CMD_BLOCK+0 , CNTLR_D I AG_CMD 



SUPPORT ROUTINES 



ISSUE THE COMMAND 



SHORT G3 

DISK STATUS, DMA BOUNDARY 



AND 
OUT 
CALL 



AL, INTAOl 
AL.ODFH 
INTAOl ,AL 
WAIT_INT 

ERROR CHK 



SET UP FOR DMA OPERATION 



ISSUE THE COMMAND 



; INITIALIZE THE DISK CHANNEL 

; NO INTERRUPTS 

; READ THE MASK 

; ENABLE lRQ-5 

; WRITE THE MASK OUT 

; PROCEDURE DOES ST I 



COMMAND 

THIS ROUTINE OUTPUTS THE COMMAND BLOCK 
INPUT 

AL r CONTROLLER DMA/ I NTERRUPT REGISTER MASK 



COMMAND 


PROC 


NEAR 






CALL 


PORT 






INC 


DX 






INC 


DX 






OUT 


DX.AL 






INC 


DX 






SUB 


CX.CX 






OUT 


DX.AL 






DEC 


DX 






DEC 


DX 


WAIT 


BUSY: 








IN 


AL.DX 






AND 


AL.OFH 






CMP 


AL.Rl BUSY OR Rl BUS 






JE 


CI 






LOOP 


WAIT BUSY 






MOV 


DISK STATUS, TIME OUT 






STC 








RET 




CI : 












MOV 


CX,6 






DEC 


DX 






MOV 


SI,BP 






SUB 


BP,8 






CLI 




CMS: 












MOV 


AL,[BP] 






OUT 


DX,AL 






INC 


BP 






LOOP 


CM3 






MOV 


BP.SI 






ST I 








RET 




COMMAND 


ENDP 





GET THE BASE ADDRESS 

ADDRESS P0RT_2 

ISSUE CONTROLLER SELECT PULSE 

ADDRESS PORT 3 

WAIT COUNT 

WRITE DMA MASK REGISTER 

ADDRESS PORT 1 

READ THE HARDWARE STATUS 

!1_REQ ; CHECK FOR BUSY, COMMAND 
; AND REQUEST BITS 
KEEP TRYING 



SET FOR 6 BYTES OF COMMAND 

ADDRESS PORT 

SAVE THE BASE POINTER 

SET FIRST BYTE OF COMMAND BLOCK 

NO INTERRUPTS IN COMMAND SEQUENCE 

GET A COMMAND BYTE 

ALLOW AT LEAST 2us BETWEEN EACH BYTE 

ON SENDING THE COMMAND SEQUENCE. 
DO MORE 

RESTORE THE BASE POINTER 
INTERRUPTS BACK ON 



March 17, 1986 



20MB Fixed Disk Drive Adapter BIOS 35 



t28l 








5 


1282 






SENSE STATUS BYTES : 


1283 


BYTE 









1284 




BIT 


7 


ADDRESS VALID, WHEN SET : 


1285 




BIT 


6 


SPARE, SET TO ZERO : 


1286 




BITS 


5-4 


ERROR TYPE : 


1287 




BITS 


3-0 


ERROR CODE : 


1288 










1289 


BYTE 


1 






1290 




BITS 


7-6 


ZERO : 


129 1 




BIT 


5 


DR I VE ( 0- 1 ) : 


1292 




BITS 


4-0 


HEAD NUMBER : 


1293 










1294 


BYTE 


2 






1295 




BITS 


7-5 


CYLINDER HIGH : 


1296 




BITS 


4-0 


SECTOR NUMBER : 


1297 










1298 


BYTE 


3 






1299 




BITS 


7-0 


CYLINDER LOW : 


1300 











05AD 

05AD AO 0074 R 
05B0 OA CO 
05B2 75 1 
05B4 C3 



05B5 

05B5 C6 46 F8 03 
05B9 2A CO 
05BB E8 057C R 
05BE 72 26 



2B FF 
B9 0004 
B4 OB 

E8 068D R 



E2 F3 
84 OF 
E8 068D R 
72 OB 



1302 
1303 
1304 
1305 
1306 
1307 
1308 
1309 
1310 
131 1 
1312 
1313 
1314 
1315 
1316 
1317 
1318 
1319 
1320 
1321 
1322 
1323 
1324 
1325 
1326 
1327 
1328 
1329 
1330 
133 1 
1332 
1333 
1334 
1335 
1336 
1337 
1338 
1339 
1340 
1341 
1342 
1343 
1344 
1345 
1346 
1347 
1348 
1349 
1350 
1351 
1352 
1353 
1354 
1355 
1356 
1357 
1358 
1359 
1360 
1361 
1362 
1363 
1364 
1365 
1366 
1367 
1368 
1369 
1370 



1372 0618 01 02 

1373 = 0003 
1374 

1375 
1376 
1377 



ERROR CHK 


PROC NEAR 


MOV 


AL.DISK STATUS 


OR 


AL.AL 


JNZ 


G21 


RET 





PERFORM SENSE STATUS 



05C0 
05C2 
05C5 
05C7 
05C7 
05CA 
05CC 
05CD 
05CE 
05D1 
05D2 
05D4 
05D6 
05D9 
05DB 
05DC 
5DD 
05DF 



05E1 C6 06 0074 R FF 

05E6 

05E6 F9 

05E7 C3 

05E8 

05E8 061E R 
05EA 062B R 
05EC 066D R 
05EE 067A R 

05F0 

05F0 8A 5E F8 

05F3 8A C3 

05F5 24 OF 

05F7 80 E3 30 

05FA 2A FF 

05FC Bl 03 

05FE D3 EB 

0600 2E: FF A7 05E8 R 



060E 04 10 02 00 04 
0613 40 00 00 11 OB 
= OOOA 



06 IB 

061B 20 20 10 

= 0003 



MOV 
SUB 
CALL 



SUB 
MOV 
MOV 



DEC 

IN 

MOV 

INC 

LOOP 

MOV 

CALL 

JC 

DEC 



G24: 

STC 
RET 

ERRORCHK 



DW 

STAT_ERR : 

MOV 
MOV 
AND 
AND 
SUB 
MOV 
SHR 
JMP 

TYPEO TABLE 



TYPEO_LEN 

TYPE1_TABLE 
DB 
DB 

TYPE1_LEN 

TYPE2_TABLE 

DB 
TYPE2_LEN 

TYPE3_TABLE 

DB 
TYPE3_LEN 



CMD_BLOCK+0 , SENSE_CMD 

AL,AL 

COMMAND 

G24 



G22 

AH, 00001 
HD_WA I T 
G24 



AL.DX 
AL,2 
STAT_ERR 



; WRITE ZERO IN INT/DMA MASK 

; ISSUE SENSE STATUS COMMAND 

; CANNOT RECOVER-EXIT WITH COMMAND 

; ERROR 

; SET INDEX POINTER TO ZERO 

; READ FOUR BYTES 

; SET MASK FOR DATA MODE CARD TO CPU 

; GO WAIT FOR DATA INPUT STATE 

J ADDRESS PORT 

: READ THE DATA BYTE 

; STORE AWAY SENSE BYTES 

i NEXT DATA LOCATION 

; LOOP TILL ALL FOUR READ. 

; SET THE MASK FOR STATUS MODE 

; GO WAIT FOR STATUS STATE 

; ADDRESS PORT 

; READ THE STATUS BYTE 

; SENSE OPERATION FAIL? 

; GO GET THE ERROR. 



DISK_STATUS.SENSE_FA1L j SET SENSE OPERATION FAIL 



TYPE_0 
TYPE_1 
TYPE_2 
TYPE 3 



BL,CMD_BLOCK+0 



ERROR TYPE JUMP TABLE 



GET ERROR BYTE 



AL,0FH 

BL,001 lOOOOB 

BH.BH 

CL,3 

BX,CL ; ADJUST 

WORD PTR CS![BX + OFFSET T_0] 



ISOLATE THE TYPE OF ERROR 



R I TE_F AULT , T I ME_OUT , , BAD_CNTLR 



LABEL BYTE 

RECORD_NOT_FND , BAD_ECC , BAD_ADDR_MARK , , RECORD_NOT_FND 

BAD_SEEK ,0,0 ,DATA_CORRECTED , BAD_TRACK 

EQU $-TYPEl_TABLE 

LABEL BYTE 

BAD_CMD , BAD_ADDR_MARK , BAD_CMD 

EQU «-TYPE2_TABLE 

LABEL BYTE 

BAD_CNTLR ,BAD_CNTLR ,BAD_ECC 

EQU $-TYPE3_TABLE 



36 20MB Fixed Disk Drive Adapter BIOS 



Marcli 17, 1986 



lal Computer MACRO Assemble 
10/28/85 FIXED DISK BIOS 



10-28-85 



1378 
1379 
1380 
1381 
1382 
1383 
1384 
1385 
1386 
1387 
1388 
1389 
1390 
1391 
1392 
1393 
1394 
1395 
1396 
1397 
1398 
1399 
1400 
140 1 
1402 
1403 
1404 
1405 
1406 
1407 
1408 
1409 



1418 
1419 
1420 
1421 
1422 
1423 
1424 
1425 
1426 
1427 
1428 
1429 
1430 
1431 
1432 
1433 
1434 
1435 
1436 
1437 
1438 
1439 
1440 
1441 
1442 
1443 
1444 
1445 
1446 
1447 
1448 
1449 
1450 
1451 
1452 
1453 
1454 
1455 
1456 
1457 
1458 
1459 
1460 
1461 
1462 
1463 
1464 
1465 
1466 
1467 
1468 
1469 
1470 
1471 



061E 

061E BB 0605 R 
0621 3C 09 
0623 73 62 
0625 2E: D7 
0627 A2 0074 R 
062A 03 



062B 

062B BB 060E R 
062E 8B 08 
0630 30 DA 
0632 73 53 
0634 2E: D7 
0636 A2 0074 R 
0639 80 El 08 
0630 80 F9 08 
063F 75 29 



0641 06 46 F8 OD 
0645 2A 00 
0647 E8 0570 R 
064A 72 IE 
0640 B4 OB 
064E E8 068D R 
0651 72 17 

0653 4A 

0654 EC 

0655 8A 08 
0657 B4 OF 

0659 E8 068D R 
0650 72 00 
065E 4A 

065F EC 

0660 A8 02 
0662 74 06 

0664 06 06 0074 R 20 

0669 F9 

066A 

066A 8A 01 

066C 03 



TYPE ERROR 



MOV 

CMP 

JAE 

XLAT 

MOV 

RET 

TYPE 



MOV 

MOV 

CMP 

JAE 

XLAT 

MOV 

AND 

CMP 

JNZ 



BX, OFFSET TYPEO_TABLE 

AL,TYPEO_LEN 

UNDEF_ERR_L 

OS:TYPEO_TABLE 

D1SK_STATUS.AL 



BX, OFFSET TYPE I 

OX, AX 

AL,TYPE1_LEN 

UNDEF_ERR_L 

0S:TYPE1_TABLE 

DISK_STATUS,AL 

OL,08H 

CL,08H 

G30 



; CHECK IF ERROR IS DEFINED 



; CHECK IF ERROR IS DEFINED 

; TABLE LOOKUP 

; SET ERROR CODE 

; CORRECTED ECO 



OBTAIN ECO ERROR BURST LENGTH 



MOV 
SUB 
CALL 



OMD_BLOOK+0 ,RD_ECC_OMD 

AL,AL 

COMMAND 

G30 

AH, 0000101 IB 

HD_WA I T 

G30 

DX 



AL.DX 

OL,AL 

AH, 00001 1 1 IB 

HD_WA I T 

G30 

DX 

AL,DX 

AL,2 

G30 

DISK STATUS, BAD ONTLR 



066D 

066D BB 0618 R 
0670 30 03 
0672 73 13 
0674 2E: D7 
0676 A2 0074 R 
0679 C3 



067A 

067A BB 06 IB R 
067D 30 03 
067F 73 06 
0681 2E: D7 
0683 A2 0074 R 

0686 03 

0687 

0687 06 06 0074 R I 
0680 03 



068D 

068D 

068E 

0690 

0690 E8 076D R 

0693 

0694 

0695 

0697 

0699 

069B 

069D 

06A2 

06A3 

06A3 

06A4 

06A5 



TYPE 2 ERROR 



MOV 

CMP 

JAE 

XLAT 

MOV 

RET 



TYPE 3 ERROR 



BX, OFFSET TYPE2_TABLE 

AL,TYPE2_LEN 

UNDEF_ERR_L 

0S:TYPE2_TABLE 

DISK_STATUS,AL 



MOV 


BX, OFFSET TYPE3 TABLE 


CMP 


AL,TYPE3 LEN 


JAE 


UNDEF ERR L 


XLAT 


0S:TYPE3 TABLE 


MOV 


DISK STATUS, AL 


RET 




UNDEF ERR L: 




MOV 


DISK STATUS, UNDEF ERR 


RET 





ISSUE THE COMMAND 



; ADDRESS PORT 

; READ THE LENGTH OF THE ERROR 
: CORRECTED AND SAVE IN OL 

; SET MASK FOR STATUS STATE 

; GO WAIT FOR STATUS STATE 

; ADDRESS PORT 

; READ THE STATUS BYTE 

; ERROR BIT SET? 



CHECK IF ERROR IS DEFINED 



CHECK IF ERROR IS DEFINED 



42 
• EC 

24 OF 

3A 04 

74 08 

E2 F3 

06 06 0074 I 
: F9 



PUSH 


OX 


SUB 


OX,CX 


CALL 


PORT 


INC 


DX 


IN 


AL,DX 


AND 


AL, 00001 1 


CMP 


AL,AH 


JZ 


L2 


LOOP 


LI 


MOV 


DISK STAT 


STO 




POP 


CX 


RET 





P0RT_1 ADDRESS 

READ THE HARDWARE STATUS 

CLEAR UPPER NIBBLE OF HARDWARE STATUS 

CHECK THE STATE WITH THE MASK 

JMP IF O.K WITH CARRY CLEARED 

TRY AGAIN 

SET ERROR CONDITION 

RESTORE CX 



March 17, 1986 



20MB Fixed Disk Drive Adapter BIOS 37 



1472 
1473 
1474 
1475 
1476 
1477 
1478 
1479 
1480 
1481 
1482 
1483 
1484 
1485 
1486 
1487 
1488 
1489 
1490 
1491 
1492 
1493 
1494 
1495 
1496 
1497 
1498 
1499 
1500 
1501 
1502 
1503 
1504 
1505 
1506 
1507 
1508 
1509 
1510 
151 1 
1512 
1513 
1514 
1515 
1516 
1517 
1518 
1519 
1520 
1521 
1522 
1523 
1524 
1525 
1526 
1527 
1528 
1529 
1530 
1531 
1532 
1533 
1534 
1535 
1536 
1537 
1538 
1539 
1540 
1541 



06A5 

06A5 80 7E FC 

06A9 72 02 



06AD 
06AD FA 

06AE E6 OC 

06B0 Bl 04 

06B2 E6 OB 

06B4 8C CO 

06B6 D3 CO 

06B8 8A E8 

06BA 24 FO 

06BC 03 C3 

06BE 80 D5 00 

06C1 8B FO 
06C3 E6 06 
06C5 8A C4 
06C7 E6 06 
06C9 8A C5 
06CB 24 OF 
06CD E6 82 



06CF 8A 66 FC 

06D2 DO E4 

06D4 32 CO 

06D6 48 



DMA_SETUP 

THIS ROUTINE SETS UP FOR DMA OPERATIONS. 
INPUT 

(AL) = MODE BYTE FOR THE DMA 

(ESrBX) = ADDRESS TO READ/WRITE THE DATA 
OUTPUT 

(AX) DESTROYED 



CLI 
OUT 
MOV 
OUT 
MOV 
ROL 
MOV 
AND 
ADD 
ADC 

MOV 
OUT 
MOV 
OUT 
MOV 
AND 
OUT 



MOV 
SHL 
XOR 
DEC 



DMA+12,AL 

CL,4 

DMA+1 1 ,AL 

AX.ES 

AX.CL 

CH.AL 

AL.OFOH 

AX.BX 

CH.O 

SI ,AX 



DMA+6,AL 
AL.CH 
AL.OFH 
DMA_HIGH,AL 

MINE COUNT 

AH,CMD_BL0CK+4 

AH, 1 

AL.AL 



AX 



HANDLE READ AND WRITE LONG 



1542 
1543 
1544 0700 



06DD 80 7E F8 E6 

06EI 75 OF 

06E3 

06E3 B8 0204 

06E6 53 

06E7 2A FF 

06E9 8A 5E FC 

06EC 52 

06ED F7 E3 

06EF 5A 

06F0 5B 

06FI 48 

06F2 

06F2 8B C8 

06F4 E6 07 

06F6 8A C4 

06F8 E6 07 

06FA FB 

06FB 8B C6 

06FD 03 CI 

06FF C3 





CMP 


CMD BLOCK+0, 




JNE 


J20 


ADD4 








MOV 


AX, 5 160 




PUSH 


BX 




SUB 


BH,BH 




MOV 


BL.CMD BLOCK 




PUSH 


DX 




MUL 


BX 




POP 


DX 




POP 


BX 




DEC 


AX 


J20: 








MOV 


ex. AX 




OUT 


DMA+7,AL 




MOV 


AL,AH 




OUT 


DMA+7,AL 




ST I 






MOV 


AX, SI 




ADD 


AX.CX 




RET 




DMA_ 


SETUP 


ENDP 



BLOCK COUNT OUT OF RANGE 



SET THE ERROR CONDITION 



; NO MORE INTERRUPTS 

; SET THE FIRST/LAST F/F 

; SHIFT COUNT 

; OUTPUT THE MODE BYTE 

; GET THE ES VALUE 

; ROTATE LEFT 

; GET HIGHEST NIBBLE OF ES TO CH 

; ZERO THE LOW NIBBLE FROM SEGMENT 

; TEST FOR CARRY FROM ADDITION 

; CARRY MEANS HIGH 4 BITS MUST BE 11 



OUTPUT THE HIGH 4 BITS TO PAGE REG 



; RECOVER BLOCK COUNT 

; MULTIPLY BY 5 1 2 BYTES PER SECTOR 

5 CLEAR LOW BYTE 

; AND DECREMENT VALUE BY ONE 

(51 6D BYTE BLOCKS) 

CMD 



ONE BLOCK (512) PLUS 4 BYTES ECC 



S BLOCK COUNT TIMES 516 



; HIGH BYTE OF COUNT 

; INTERRUPTS BACK ON 

; RECOVER ADDRESS VALUE 

; ADD, TEST FOR 64K OVERFLOW 

; RETURN TO CALLER, 

; CY SET BY ABOVE IF ERROR 



38 20MB Fixed Disk Drive Adapter BIOS 



March 17, 1986 



IBM 


Persona 


Computer 


DISKS --- 


10/28/85 F 


1545 








1546 








1547 








1548 








1549 








1550 








1551 








1552 








1553 


0700 






1554 








1555 


0700 


FB 




1556 


0701 


8C 


DB 


1557 


0703 


2B 


CO 


1558 


0705 


8E 


D8 


1559 


0707 


C4 


36 0104 R 


1560 








1561 








1562 


070B 


SE 


DB 


1563 








1564 








1565 








1566 


070D 


2A 


FF 


1567 


070F 


26 


8A 5C 09 


1568 


0713 


8A 


66 F8 


1569 


0716 


80 


FC 04 


1570 


0719 


75 


06 


1571 








1572 


07IB 


26 


8A 5C OA 


1573 


071F 


EB 


09 


1574 


0721 


80 


FC E3 


1575 


0724 


75 


04 


1576 








1577 


0726 


26 


8A 5C OB 


1578 


072A 






1579 


072A 


F8 




1580 


072B 


B8 


9000 


1581 


072E 


CD 


15 


1582 


0730 


FB 




1583 








1584 


0731 


2B 


C9 


1585 








1586 








1587 








1588 


0733 






1589 


0733 


E8 


076D R 


1590 


0736 


42 




1591 


0737 


EC 




1592 


0738 


A8 


20 


1593 


073A 


75 


OA 


1594 








1595 


073C 


E2 


F5 


1596 


073E 


4B 




1597 


073F 


75 


F2 


1598 








1599 


0741 


C6 


06 0074 R 


1600 


0746 






1601 


0746 


4A 




1602 


0747 


EC 




1603 


0748 


24 


02 


1604 


074A 


08 


06 0074 R 


1605 


074E 


83 


C2 03 


1606 


0751 


32 


CO 


1607 


0753 


EE 




1608 


0754 


C3 




1609 








1610 


0755 






1611 








1612 








1613 








1614 








1615 








1616 








1617 








1618 


0755 






1619 


0755 


50 




1620 


0756 


BO 


07 


1621 


0758 


E6 


OA 


1622 


075A 


FA 




1623 


075B 


E4 


21 


1624 


075D 


OC 


20 


1625 


075F 


E6 


21 


1626 


0761 


BO 


20 


1627 


0763 


E6 


20 


1628 


0765 


FB 




1629 


0766 


86 


9100 


1630 


0769 


CD 


15 


1631 


076B 


58 




1632 


076C 


CF 




1633 


076D 






1634 








1635 








1636 








1637 








1638 








1639 








1640 








1641 


076D 






1642 


076D 


BA 


0320 


1643 


0770 


02 


16 0077 R 


1644 


0774 


C3 




1645 


0775 






1646 








1647 


0775 






1648 


0775 






1649 









THIS ROUTINE WAITS FOR THE FIXED DISK 
CONTROLLER TO SIGNAL THAT AN INTERRUPT 
HAS OCCURRED. 





PROC NEAR 


ASSUME 


DS:ABS0 


STI 




MOV 


BX.DS 


SUB 


AX, AX 


MOV 


DS.AX 


LES 


SI ,HF_TBL_VEC 


ASSUME 


DS : DATA. ES: NOTHING 


MOV 


DS.BX 


SET TIMEOUT VALUES 


SUB 


BH.BH 


MOV 


BL.BYTE PTR ES: [SI ] [9] 


MOV 


AH.CMD BLOCK+0 


CMP 


AH.FMTDRV CMD 


JNZ 


W5 


MOV 


BL.BYTE PTR ES:[SI][OAH] 


JMP 


SHORT W4 


CMP 


AH.CHK DRV CMD 


JNZ 


W4 


MOV 


BL.BYTE PTR ES:[SI][OBH] 


CLC 




MOV 


AX,9000H 


INT 


15H 



WAIT FOR INTERRUPT 



CALL 


POF 


T 


INC 


DX 




IN 


AL 


DX 


TEST 


AL 


020H 


JNZ 


W2 




LOOP 


Wl 




DEC 


BX 




JNZ 


Wl 





D I SK_STATUS , T I ME_OUT 



IN 


AL.DX 




AND 


AL,2 




OR 


DISK STATUS 


AL 


ADD 


DX.3 




XOR 


AL.AL 




OUT 


DX.AL 




RET 







RESTORE DS 



LOAD THE STANDARD Til 



; LOAD THE CHECK DRIVE 
S TIME OUT VALUE 

CLEAR CY 

DEVICE WAIT INTERRUPT 

ENABLE INTERRUPTS FOR PC AND 

XT MACHINES. 
SET THE LOOP COUNT 



PORT_l ADDRESS 
READ THE HARDWARE STATUS 
DID INTERRUPT OCCUR 
JUMP IF YES 

INNER LOOP 

OUTER LOOP 



ADDRESS PORT 

READ THE STATUS BYTE 

ISOLATE THE ERROR BIT 

SAVE IN THE STATUS 

P0RT_3 ADDRESS 

ZERO 

RESET INTERRUPT MASK 



_INT ENDP 

HD_INT 

FIXED DISK INTERRUPT ODH ROUTINE IRQ-5 



PROC 
PUSH 
MOV 
OUT 



OUT 

MOV 

OUT 

STI 

MOV 

INT 

POP 

I RET 

ENDP 



AL. INTAOI 
AL,020H 
INTAOI .AL 
AL.EOI 
INTAOO.AL 

AX,9I00H 



NO INTERRUPTS 

LOAD THE INTERRUPT ENABLE MASK 

TURN OFF FIXED DISK IRQ-5 

REPLACE THE MASK 

LOAD THE END OF INTERRUPT MASK 

CLEAR THE ACTIVE INTERRUPT LEVEL 

INTERRUPTS BACK ON 

DEVICE POST 

INTERRUPT 
RESTORE AX 



PORT 


PROC 


NEAR 




MOV 


DX.HF PORT 




ADD 


DL.PORT OFF 




RET 




PORT_0 


ENDP 




END ADDRESS 


LABEL BYT 


CODE 


ENDS 
END 





March 17, 1986 20MB Fixed Disk Drive Adapter BIOS 39 



Notes: 



40 20MB Fixed Disk Drive Adapter BIOS March 17, 1986 



Index 



addresses, port 14 



fixed disk controller 1 
fixed disk drive types 3 





R 






~ 1 


I 


BIOS listings 23 




block diagram 2 


interface 15 




interface signals 




AEN 15 




C 




A0-A19 15 






-DACK 3 16 




DO-D7 15 


command summary 10 


DRQ 3 15 


connectors 17 


-lOR 15 


control byte 8 


-lOW 15 


controller, fixed disk 1 


IRQ 5 15 




RESET 15 




D 




L 


data register 7 




description 1 


logic diagrams 19 




E 







error tables 5 



March 17, 1986 



20MB Fixed Disk Drive Adapter Index-1 



s 



port addresses 14 
programming 

considerations 3 
programming summary 14 



R 



registers 1 





S 




sense bytes 4 
specifications 17 
status register 4 
switch settings 3 


T 


liL levels 17 



Index-2 20MB Fixed Disk Drive Adapter 



March 17, 1986 



Personal Computer 
Hardware Reference 
Library 



IBM Asynchronous 

Communications 

Adapter 



6361501 



11 



Contents 



Description 1 

Programming Considerations 3 

Modes Of Operation 3 

Line-Control Register 5 

Programmable Baud-Rate Generator 7 

Line Status Register (LSR) 10 

Interrupt Identification Register (IIR) 12 

Interrupt Enable Register 14 

Modem Control Register 15 

Modem Status Register 16 

Receiver Buffer Register 18 

Transmitter Holding Register 19 

Selecting the Interface Format and Adapter Address 20 

Interrupts 21 

Interface 23 

Voltage Interchange Information 24 

INS8250 Functional Pin Description 25 

Specifications 31 

Logic Diagrams 33 

Index Index-1 



m 



IV 



Description 



The Asynchronous Communications Adapter's system control 
signals and voltage requirements are provided through a 2- by 
31 -position card-edge connector. Two jumper modules are 
provided on the adapter. One jumper module selects either 
RS-232C or current-loop operation. The other jumper module 
selects one of two addresses for the adapter, so two adapters may 
be used in one system. An additional jumper is required on 
connector J13 if the adapter is to be installed in expansion slot 8 
of an IBM Personal Computer XT or IBM Portable Personal 
Computer (see ''Selecting the Interface Format and Adapter 
Address" in this section). 

The adapter is fully programmable and supports asynchronous 
communications only. It will add and remove start bits, stop bits, 
and parity bits. A programmable baud-rate generator allows 
operation from 50 baud to 9600 baud. Five-, six-, seven-, or 
eight-bit characters with 1, 1-1/2, or 2 stop bits are supported. A 
fully prioritized interrupt system controls transmit, receive, error, 
line status, and data set interrupts. Diagnostic capabilities provide 
loopback functions of transmit/receive and input/output signals. 

The major component of the adapter is an INS8250 LSI chip or 
functional equivalent. Features in addition to those listed above 
are: 

• Full double buffering eliminating the need for precise 
synchronization 

• Independent receiver clock input 

• False-start bit detection 

• Line-break generation and detection 



Asynchronous Adapter 1 



• Modem control functions: 

Clear to send (CTS) 
Request to send (RTS) 
Data set ready (DSR) 
Data terminal ready (DTR) 
Ring indicator (RI) 
Carrier detect (CD) 

All communication protocol is a function of the system microcode 
and must be loaded before the adapter is operational. All pacing 
of the interface and control signal status must be handled by the 
system software. The following figure is a block diagram of the 
IBM Asynchronous Communications Adapter. 



Address Bus 


^ 


Address 




Chip 


















w 


Decode 


Select 


W 


8250 

Asynchronous 
Communications 
Element 








Data Bus 






^ 


Interrupt 


^ 




^ 
















Oscillator 
1.8432 MHz 
































EIA 
Receivers 




EIA 
Drivers 






> P 




'^ 






















A 
1 




Current Loop 










A 






















^ 


















^ 













25-Pin D-Shell 
Connector 



Asynchronous Communications Adapter Block Diagram 



2 Asynchronous Adapter 



Programming Considerations 



Modes Of Operation 

The different modes of operation are selected by programming 
the 8250 Asynchronous Communications Element. This is done 
by selecting the I/O address (hex 3F8 to 3FF primary, and hex 
2F8 to 2FF secondary) and writing data out to the adapter. 
Address bits AO, Al, and A2, select the different registers that 
define the modes of operation. Also, bit 1 — the divisor latch 
access bit (DLAB) — of the line-control register is used to select 
certain registers. 



I/O Decode (in Hex) 






Primary 


Alternate 


Adapter 


Adapter 


Register Selected 


DLAB State 


3F8 


2F8 


TX Buffer 


DLAB = (Write) 


3F8 


2F8 


RX Buffer 


DLAB = O(Read) 


3F8 


2F8 


Divisor Latch LSB 


DLAB = 1 


3F9 


2F9 


Divisor Latch MSB 


DLAB = 1 


3F9 


2F9 


Interrupt Enable Register 




3FA 


2FA 


Interrupt Identification Registers 




3FB 


2FB 


Line Control Register 




3FC 


2FC 


Modem Control Register 




3FD 


2FD 


Line Status Register 




3FE 


2FE 


Modem Status Register 





I/O Decodes 



Asynchronous Adapter 3 



Hex Addresses 3F8 to 3FF AND 2F8 TO 2FF 




A9 


A8 


A7 


A6 


A5 


A4 


A3 


A2 


A1 


AO 


DLAB 


Register 


1 


1/0 


1 


1 


1 


1 


1 


X 






1 
1 
1 
1 





X 




1 
1 



1 
1 





X 












X 
X 
X 
X 
X 
X 

1 
1 


Receive Buffer (read). 

Transmit 

Holding Reg. (write) 

Interrupt Enable 

Interrupt Identification 

Line Control 

Modem Control 

Line Status 

Modem Status 

None 

Divisor Latch (LSB) 

Divisor Latch (MSB) 


Note: Bit 8 will be logical 1 for the adapter designated as primary or a logical 
for the adapter designated as alternate (as defined by the address jumper 
module on the adapter). 


A2, A1 and AO bits are "don't cares" an 
register of the communications chip. 


d are used to select the different 



Address Bits 



INS8250 

The INS8250 has a number of accessible registers. The system 
programmer may access or control any of the INS 8 250 registers 
through the system unit's microprocessor. These registers are 
used to control INS8250 operations and to transmit and receive 
data. The following figure provides a Usting and description of 
the accessible registers. 



4 Asynchronous Adapter 



Register/Signal 


Reset Control 


Reset State 


Interrupt Enable Register 


Master Reset 


All bits Low (0-3 Forced and 
4-7 Permanent). 


Interrupt Identification 


Master Reset 


Bit is High, Bits 1 and 2 Low 


Register 




Bits 3-7 are Permanently Low 


Line Control Register 


Master Reset 


All Bits Low 


Modenn Control Register 


Master Reset 


All Bits Low 


Line Status Register 


Master Reset 


Except Bits 5 and 6 are High 


Modem Status Register 


Master Reset 


Bits 0-3 Low 

Bits 4-7 - Input Signal 


SOUT 


Master Reset 


High 


INTRPTIRCVR Errors) 


Read LSR/MR 


Low 


INTRPT (RCVR Data Ready) 


Read RBR/MR 


Low 


INTRPTIRCVR Data Ready) 


ReadllR/ 
Write THR/MR 


Low 


INTRPT (Modem Status 


Read MSR/MR 


Low 


Changes) 






OUT 2 


Master Reset 


High 


RTS 


Master Reset 


High 


DTR 


Master Reset 


High 


0UT1 


Master Reset 


High 



Asynchronous Communications Reset Functions 



Line-Control Register 

The system programmer specifies the format of the asynchronous 
data communications exchange through the Une-control register. 
In addition to controlling the format, the programmer may 
retrieve the contents of the Une-control register for inspection. 
This feature simplifies system programming and eliminates the 
need for separate storage in system memory of the line 
characteristics. 



Asynchronous Adapter 5 



The contents of the Hne-control register are as follows: 



Hex Address 3FB 



Bit 









^ 



Word Length Select Bit (WLSO) 

Word Length Select Bit 1 (WLS1) 

Nunnber of Stop Bits (STB) 

Parity Enable (PEN) 

Even Parity Select (EPS) 

Stick Parity 

Set Break 

Divisor Latch Access Bit (DLAB) 



Bits and 1 : These two bits specify the number of bits in each 
transmitted or received serial character. The encoding of bits 
and 1 is as follows: 



Bit1 


BitO 


Word Length 








5 Bits 





1 


6 Bits 


1 





7 Bits 


1 


1 


8 Bits 



Bit 2: This bit specifies the number of stop bits in each 
transmitted or received serial character. If bit 2 is a logical 0, one 
stop bit is generated or checked in the transmitted or received 
data, respectively. If bit 2 is logical 1 when a 5 -bit word length is 
selected through bits and 1, 1-1/2 stop bits are generated or 
checked. If bit 2 is logical 1 when either a 6-, 7-, or 8-bit word 
length is selected, two stop bits are generated or checked. 

Bit 3: This bit is the parity enable bit. When bit 3 is a logical 1, a 
parity bit is generated (transmit data) or checked (receive data) 
between the last data word bit and stop bit of the serial data. 
(The parity bit is used to produce an even or odd number of I's 
when the data word bits and the parity bit are summed.) 



6 Asynchronous Adapter 



Bit 4: This bit is the even parity select bit. When bit 3 is a logical 
1 and bit 4 is a logical 0, an odd number of logical I's is 
transmitted or checked in the data word bits and parity bit. When 
bit 3 is a logical 1 and bit 4 is a logical 1 , an even number of bits 
is transmitted or checked. 

Bit 5: This bit is the stick parity bit. When bit 3 is a logical 1 and 
bit 5 is a logical 1 , the parity bit is transmitted and then detected 
by the receiver as a logical if bit 4 is a logical 1 , or as a logical 1 
if bit 4 is a logical 0. 

Bit 6: This bit is the set break control bit. When bit 6 is a logical 
1, the serial output (SOUT) is forced to the spacing (logical 0) 
state and remains there regardless of other transmitter activity. 
The set break is disabled by setting bit 6 to a logical 0. This 
feature enables the system unit's microprocessor to alert a 
terminal in a computer communications system. 

Bit 7: This bit is the divisor latch access bit (DLAB). It must be 
set high (logical 1) to access the divisor latches of the baud-rate 
generator during a read or write operation. It must be set low 
(logical 0) to access the receiver buffer, the transmitter holding 
register, or the interrupt enable register. 



Programmable Baud-Rate Generator 

The INS8250 contains a programmable baud-rate generator that 
is capable of taking the clock input (1.8432 MHz) and dividing it 
by any divisor from 1 to (2i6_i)^ xhe output frequency of the 
baud generator is 1 6 x the baud rate (divisor # = (frequency 
input) /(baud rate x 16)). Two 8-bit latches store the divisor in a 
16-bit binary format. These divisor latches must be loaded during 
initiaUzation in order to ensure desired operation of the baud-rate 
generator. Upon loading either of the divisor latches, a 16-bit 
baud counter is immediately loaded. This prevents long counts on 
initial load. 



Asynchronous Adapter 7 



Hex Address 3F8 DLAB=1 



Bit 7 6 5 4 3 2 10 






BitO 
Bit1 
Bit 2 
Bits 
Bit 4 
Bits 
Bite 
Bit? 



Divisor Latch Least Significant Bit (DLL) 



Hex Address 3F9 DLAB=1 



Bit 



7 6 5 4 3 2 1 









Bits 
Bit 9 
Bit 10 
Bit 11 
Bit 12 
Bit 13 
Bit 14 
Bit 15 



Divisor Latch Most Significant Bit (DLIVI) 



8 Asynchronous Adapter 



The following figure illustrates the use of the baud-rate generator 
with a frequency of 1.8432 MHz. For baud rates of 9600 and 
below, the error obtained is minimal. 

Note: The maximum operating frequency of the baud-rate 
generator is 3.1 MHz. In no case should the data speed be 
greater than 9600 baud. 



Desired 


Divisor Used 




Percent Error 


Baud 


to Generate 




Difference Between 


Rate 


16x Clock 




Desired and Actual 




(Decimal) 


(Hex) 




50 


2304 


900 


— 


75 


1536 


600 


— 


110 


1047 


417 


0.026 


134.5 


857 


359 


0.058 


150 


768 


300 


— 


300 


384 


180 


— 


600 


192 


000 


— 


1200 


96 


060 


— 


1800 


64 


040 


— 


2000 


58 


03A 


0.69 


2400 


48 


030 


— 


3600 


32 


020 


— 


4800 


24 


018 


— 


7200 


16 


010 


— 


9600 


12 


OOC 


- 



Baud Rate at 1 .843 MHz 



Asynchronous Adapter 9 



Line Status Register (LSR) 

This 8-bit register provides status information to the system unit's 
microprocessor concerning the data transfer. The contents of the 
line status register are indicated and described in the following 
figure. 



Hex Address 3FD 



Bit 



3 E 


3 ^ 


1-321 





^ 






. ► 

► 



Data Ready (DR) 

Overrun Error (OR) 
^ Parity Error (PE) 

Framing Error (FE) 
^^ Break Interrupt (Bl) 

Transmitter Holding 

Register Empty 

(THRE) 

Tx Shift Register 

Empty (TSRE) 

= 



Line Status Register (LSR) 

Bit 0: This bit is the receiver data ready (DR) indicator. Bit is 
set to logical 1 whenever a complete incoming character has been 
received and transferred into the receiver buffer register. Bit 
may be reset to a logical either by the system unit's 
microprocessor reading the data in the receiver buffer register or 
by writing logical into it from the system unit's microprocessor. 

Bit 1: This bit is the overrun error (OE) indicator. Bit 1 indicates 
that data in the receiver buffer register was not read by the 
system unit's microprocessor before the next character was 
transferred into the receiver buffer register, thereby destroying 
the previous character. The OE indicator is reset whenever the 
system unit's microprocessor reads the contents of the line status 
register. 

Bit 2: This bit is the parity error (PE) indicator. Bit 2 indicates 
that the received data character does not have the correct even or 
odd parity, as selected by the even-parity select bit. The PE bit is 



10 Asynchronous Adapter 



set to logical 1 upon detection of a parity error and is reset to 
logical whenever the system unit's microprocessor reads the 
contents of the line status register. 

Bit 3: This bit is the framing error (FE) indicator. Bit 3 indicates 
that the received character did not have a vaUd stop bit. Bit 3 is 
set to logical 1 whenever the stop bit following the last data bit or 
parity is detected as a zero bit (spacing level). 

Bit 4: This bit is the break interrupt (BI) indicator. Bit 4 is set to 
logical 1 whenever the received data input is held in the spacing 
(logical 0) state for longer than a full-word transmission time 
(that is, the total time of start bit + data bits -f parity + stop 
bits). 

Note: Bits 1 through 4 are the error conditions that produce a 
receiver Hne status interrupt whenever any of the 
corresponding conditions are detected. 

Bit 5: This bit is the transmitter-holding-register-empty (THRE) 
indicator. Bit 5 indicates that the INS8250 is ready to accept a 
new character for transmission. In addition, this bit causes the 
INS8250 to issue an interrupt to the system unit's microprocessor 
when the transmit-holding-register-empty interrupt enable is set 
high. The THRE bit is set to logical 1 when a character is 
transferred from the transmitter holding register into the 
transmitter shift register. The bit is reset to logical concurrently 
with the loading of the transmitter holding register by the system 
unit's microprocessor. 

Bit 6: This bit is the transmitter-shift-register-empty (TSRE) 
indicator. Bit 6 is set to logical 1 whenever the transmitter shift 
register is idle. It is reset to logical upon a data transfer from 
the transmitter holding register to the transmitter shift register. 
Bit 6 is a read-only bit. 

Bit 7: This bit is permanently set to logical 0. 



Asynchronous Adapter 1 1 



Interrupt Identification Register (IIR) 

The INS8250 has an on-chip interrupt capability that allows for 
complete flexibility in interfacing to all the popular 
microprocessors presently available. In order to provide minimum 
software overhead during data character transfers, the INS8250 
prioritizes interrupts into four levels: receiver Hne status (priority 
1), received data ready (priority 2), transmitter holding register 
empty (priority 3), and modem status (priority 4). 

Information indicating that a prioritized interrupt is pending, and 
the type of prioritized interrupt, is stored in the interrupt 
identification register. Refer to the 'Interrupt Control 
Functions" table. The interrupt identification register (IIR), 
when addressed during chip-select time, freezes the highest 
priority interrupt pending, and no other interrupts are 
acknowledged until that particular interrupt is serviced by the 
system unit's microprocessor. The contents of the IIR are 
indicated and described in the following figure. 



Hex Address 3FA 



Bit 









1 ^ 

► 

► 




1 ^ 



If Interrupt Pending 
Interrupt ID Bit (0) 
Interrupt ID Bit (1) 
= 
= 
= 



-^ = 
-► = 



Interrupt Identification Register (IIR) 



Bit 0: This bit can be used in either a hard- wired prioritized or 
polled environment to indicate whether an interrupt is pending, 
and the IIR contents may be used as a pointer to the appropriate 
interrupt service routine. When bit is logical 1, no interrupt is 
pending, and polUng (if used) is continued. 



12 Asynchronous Adapter 



Bits 1 and 2: These two bits of the IIR are used to identify the 
highest priority interrupt pending, as indicated in the 'Interrupt 
Control Functions" table. 

Bits 3 through 7: These five bits of the IIR are always logical 0. 



Interrupt ID 
Register 


Interrupt Set and Reset Functions 


Bit 2 


Biti 


BitO 


Priority 
Level 


Interrupt 
Type 


Interrupt 
Source 


Interrupt 
Reset Control 








1 


- 


None 


None 


- 


1 


1 





Highest 


Receiver 
Line Status 


Overrun Error 

or 
Parity Error 

or 
Framing Error 

or 
Break Interrupt 


Reading the 
Line Status 
Register 


1 








Second 


Received 
Data Available 


Receiver 
Data Available 


Reading the 
Receiver Buffer 
Register 





1 





Third 


Transmitter 
Holding 
Register 
Ennpty 


Transmitter 
Holding 
Register 
Empty 


Reading the IIR 
Register (if 
source of 
interrupt) 

or 
Writing into the 
Transmitter 
Holding Register 























Fourth 


Modem 
Status 


Clear to Send 

or 
Data Set Ready 

or 
Ring Indicator 


Reading the 
Modem Status 
Register 
























Received Line 
Signal Direct 





Interrupt Control Functions 



Asynchronous Adapter 13 



Interrupt Enable Register 

This 8 -bit register enables the four types of interrupt of the 
INS8250 to separately activate the chip interrupt (INTRPT) 
output signal. It is possible to totally disable the interrupt system 
by resetting bits through 3 of the interrupt enable register. 
Similarly, by setting the appropriate bits of this register to logical 
1, selected interrupts can be enabled. Disabling the interrupt 
system inhibits the interrupt identification register and the active 
(high) INTRPT output from the chip. All other system functions 
operate in their normal manner, including the setting of the line 
status and modem status registers. The contents of the interrupt 
enable register are indicated and described in the following figure. 



Hex Address 3F9 DLAB = 



Bit 



X : 


J : 


I 




► 








► 



1 = Enable Data 

Available Interrupt 

1 = Enable Tx Holding Register 

Empty Interrupt 

1 = Enable Receive Line 

Status Interrupt 

1 = Enable Modem Status 

Interrupt 

= 

= 

= 

= 



Interrupt Enable Register (lER) 



Bit 0: This bit enables the received-data-available interrupt when 
set to logical 1 . 

Bit 1: This bit enables the transmitter-holding-register-empty 
interrupt when set to logical 1 . 

Bit 2: This bit enables the receiver-line-status interrupt when set 
to logical 1 . 



14 Asynchronous Adapter 



Bit 3: This bit enables the modem-status interrupt when set to 
logical 1. 

Bits 4 through 7: These four bits are always logical 0. 



Modem Control Register 

This 8 -bit register controls the interface with the modem or data 
set (or a peripheral device emulating a modem). The contents of 
the modem control register are indicated and described as follows: 



Hex Address 3FC 


Bit 


1 i 


5 \ 


S ^ 


\ : 


i : 


I 




^^ Data Terminal Ready (DTR) 

,„. , ,,w 




Request to Send (Rib) 




^ Out 1 




^ Out 2 




" Loop 




' = 




■ =" i 




" =0 



Modem Control Register (MCR) 



Bit 0: This bit controls the data terminal ready (-DTR) output. 
When bit is set to a high level, the -DTR output is forced to an 
active low. When bit is reset to low level, the -DTR output is 
forced high. 

Note: The -DTR output of the INS8250 may be appHed to an 
EI A inverting line driver (such as the DS 148 8) to obtain the 
proper polarity input at the succeeding modem or data set. 

Bit 1: This bit controls the request to send (-RTS) output. Bit 1 
affects the -RTS output in a manner identical to that described 
above for bit 0. 

Bit 2: This bit controls the output 1 (-OUT 1) signal, which is an 
auxiliary user-designated output. Bit 2 affects the -OUT 1 output 
in a manner identical to that described above for bit 0. 



Asynchronous Adapter 15 



Bit 3: This bit controls the output 2 (-OUT 2) signal, which is an 
auxihary user-designated output. Bit 3 affects the -OUT 2 output 
in a manner identical to that described above for bit 0. 

Bit 4: This bit provides a loopback feature for diagnostic testing 
of the INS8250. When bit 4 is set to logical 1, the following 
occurs: the transmitter serial output (SOUT) is set to the marking 
(logical 1) state; the receiver serial input (SIN) is disconnected; 
the output of the transmitter shift register is ''looped back" into 
the receiver shift register input; the four modem control inputs 
(-CTS, -DSR, -RLSD, and -RI) are disconnected; and the four 
modem control outputs (-DTR, -RTS, -OUT 1, and -OUT 2) are 
internally connected to the four modem control inputs. In the 
diagnostic mode, data that is transmitted is immediately received. 
This feature allows the system unit's microprocessor to verify the 
transmit-data and receive-data paths of the INS8250. 

In the diagnostic mode, the receiver and transmitter interrupts are 
fully operational. The modem control interrupts also are 
operational, but the interrupts' sources are now the lower four 
bits of the modem control register instead of the four modem 
control inputs. The interrupts are still controlled by the interrupt 
enable register. 

The INS8250 interrupt system can be tested by writing into the 
lower four bits of the modem status register. Setting any of these 
bits to a logical 1 generates the appropriate interrupt (if enabled). 
The resetting of these interrupts is the same as in normal INS8250 
operation. To return to normal operation, the registers must be 
reprogrammed for normal operation, then bit 4 of the modem 
control register must be reset to logical 0. 

Bits 5 through 7: These bits are permanently set to logical 0. 



Modem Status Register 

This 8 -bit register provides the current state of the control lines 
from the modem (or peripheral device) to the system unit's 
microprocessor. In addition to this current-state information, 
four bits of the modem status register provide change 
information. These bits are set to logical 1 whenever a control 



16 Asynchronous Adapter 



input from the modem changes state. They are reset to logical 
whenever the system unit's microprocessor reads the modem 
status register. 

The content of the modem status register is indicated and 
described in the following figure. 



Hex Address 3FE 



Bit 



I : 


i : 


I 1 

' ► 

► 




► 



Delta Clear to Send (DOTS) 
Delta Data Set Ready (DDSR) 
Trailing Edge Ring 
Indicator (TERI) 
Delta Rx Line Signal 
Detect (DRLSD) 
Clear to Send (GTS) 
Data Set Ready (DSR) 
Ring Indicator (Rl) 
Receive Line Signal 
Detect (RLSD) 



Modem Status Register (MSR) 

Bit 0: This bit is the delta clear to send (DCTS) indicator. Bit 
indicates that the -CTS input to the chip has changed state since 
the last time it was read by the system unit's microprocessor. 

Bit 1: This bit is the delta data set ready (DDSR) indicator. Bit 1 
indicates that the -DSR input to the chip has changed state since 
the last time it was read by the system unit's microprocessor. 

Bit 2: This bit is the trailing edge of the ring indicator (TERI) 
detector. Bit 2 indicates that the -RI input to the chip has changed 
from an on (logical 1) to an off (logical 0) condition. 

Bit 3: This bit is the delta received line signal detector (DRLSD) 
indicator. Bit 3 indicates that the -RLSD input to the chip has 
changed state. 

Note: Whenever bit 0, 1, 2, or 3 is set to logical 1, a modem 
status interrupt is generated. 



Asynchronous Adapter 17 



Bit 4: This bit is the complement of the clear to send (-CTS) 
input. If bit 4 (LOOP) of the modem control register (MCR) is 
set to logical 1, the bit is equivalent to RTS in the MCR. 

Bit 5: This bit is the complement of the data set ready (-DSR) 
input. If bit 4 of the MCR is set to logical 1, the bit is equivalent 
to DTR in the MCR. 

Bit 6: This bit is the complement of the ring indicator (-RI) input. 
If bit 4 of the MCR is set to logical 1 , the bit is equivalent to 
OUT 1 in the MCR. 

Bit 7: This bit is the complement of the received line signal detect 
(-RLSD) input. If bit 4 of the MCR is set to logical 1, the bit is 
equivalent to OUT 2 of the MCR. 



Receiver Buffer Register 

The receiver buffer register contains the received character, which 
is defined in the following figure. 



Hex Address 3F8 DLAB = Read Only 



Bit 



1 










Data Bit 
Data Bit 1 
Data Bit 2 
Data Bit 3 
Data Bit 4 
Data Bit 5 
Data Bit 6 
Data Bit 7 



Receiver Buffer Register (RBR) 



Bit is the least-significant bit and is the first bit serially received. 



18 Asynchronous Adapter 



Transmitter Holding Register 

The transmitter holding register contains the character to be 
serially transmitted and is defined as follows: 



Hex Address 3F8 DLAB = Write Only 



Bit 



5 ^ 


[ : 


J : 


I 1 











' ► 

► 

^- 


1 ► 



Data Bit 
-► Data Bit 1 
Data Bit 2 
Data Bit 3 
Data Bit 4 
-► Data Bit 5 
Data Bit 6 
Data Bit 7 



Transmitter Holding Register (THR) 



Bit is the least-significant bit and is the first bit serially 
transmitted. 



Asynchronous Adapter 19 



Selecting the Interface Format and Adapter 
Address 

The voltage or current-loop interface and adapter address are 
selected by plugging in programmed shunt modules with the 
locator dots up or down. See the following figure for the 
configurations. 



Module Position 
for Primary 
Asynchronous 
Adapter 



Module Position 
for Alternate 
Asynchronous 
Adapter 

Hex 2F8-2FF 




Asynchronous 

Communications 

Adapter 



Current Loop 
Interface 
Dot Down 



Shunt Module 
Socket 



Voltage Interface 
Dot Up 



20 Asynchronous Adapter 



If the adapter is to be installed in expansion slot 8 of an IBM 
Personal Computer XT or IBM Portable Personal Computer, a 
jumper is required on connector J 13. 



Interrupts 

One interrupt line is provided to the system. This interrupt is 
IRQ4 for a primary adapter, or IRQ3 for an alternate adapter, 
and is positive active. To allow the communications adapter to 
send interrupts to the system, bit 3 of the modem control register 
must be set to 1 (high). At this point, any interrupts allowed by 
the interrupt enable register will cause an interrupt. 

The data format will be as follows: 



Transmit 
Data Marking 



Start 
Bit 



DO D1 D2 D3 D4 D5 D6 D7 

> M M W t 



Parity 
Bit 



Stop 
Bits 



Data bit is the first bit to be transmitted or received. The 
adapter automatically inserts the start bit, the correct parity bit if 
programmed to do so, and the stop bit (1, 1-1/2, or 2 depending 
on the command in the line-control register). 



Asynchronous Adapter 21 



22 Asynchronous Adapter 



Interface 



The communications adapter provides an EI A RS-232C-like 
interface. One 25-pin, D-shell, male connector is provided to 
attach various peripheral devices. In addition, a current-loop 
interface is also located in this same connector. A jumper block is 
provided to manually select either the voltage interface or the 
current-loop interface. 

The current-loop interface is provided to attach certain printers 
provided by IBM that use this particular type of interface. IBM 
recommends that the current loop not be used beyond a distance 
of 15.3 meters (50 feet) as measured by the length of cable 
between the two interconnected points. 

Pin 18 4- receive current loop data 

Pin 25 - receive current loop return 

Pin 11 - transmit current loop data 

Pin 9 -h transmit current loop return 



+5 Vdc 



Transmit Circuit 



Tx Data 



\^ 10 



49.9 Ohm 



100 Ohm 

-^AA^ — 



-> Pin 9 
-► Pin 11 



+5 Vdc 




Rx Data 



Pin 25 ^ 



+5 Vdc 

Current Loop Interface 



Asynchronous Adapter 23 



The voltage interface is a serial interface, 
and control signals, as follows: 



It supports certain data 



Pin 2 


Transmitted Data 


Pin 3 


Received Data 


Pin 4 


Request to Send 


Pin 5 


Clear to Send 


Pin 6 


Data Set Ready 


Pin 7 


Signal Ground 


Pin 8 


Carrier Detect 


Pin 20 


Data Terminal Ready 


Pin 22 


Ring Indicator 



The adapter converts these signals to or from TTL levels from or 
to EIA voltage levels. These signals are sampled or generated by 
the communications control chip. These signals can then be 
sensed by the system software to determine the state of the 
interface or peripheral device. 



Voltage Interchange Information 



Interchange Voltage 


Binary State 


Signal Condition 


Interface 
Control Function 


Positive Voltage = 
Negative Voltage = 


Binary (0) 
Binary (1) 


= Spacing 
= Marking 


= On 
= Off 



invalid Levels 
+ 15Vdc 

On Function 

+ 3 Vdc 

Vdc Invalid Levels 

-3 Vdc 

Off Function 
- 1 5 Vdc 

Invalid Levels 



The signal will be considered in the marking condition when the 
voltage on the interchange circuit, measured at the interface 



24 Asynchronous Adapter 



point, is more negative than -3 Vdc with respect to signal ground. 
The signal will be considered in the spacing condition when the 
voltage is more positive than +3 Vdc with respect to signal 
ground. The region between +3 Vdc and -3 Vdc is defined as the 
transition region, and considered an invalid level. The voltage 
that is more negative than -15 Vdc or more positive than +15 
Vdc will also be considered an invalid level. 

During the transmission of data, the marking condition will be 
used to denote the binary state 1 , and the spacing condition will 
be used to denote the binary state 0. 

For interface control circuits, the function is on when the voltage 
is more positive than -1-3 Vdc with respect to signal ground and is 
off when the voltage is more negative than -3 Vdc with respect to 
signal ground. 



INS8250 Functional Pin Description 

The following describes the function of all INS8250 input/output 
pins. Some of these descriptions refer to internal circuits. 

Note: In the following descriptions, a low represents a logical 
(0 Vdc nominal) and a high represents a logical 1 (+2.4. 
Vdc nominal). 



Input Signals 

Chip Select (CSO, CSl, -CS2), Pins 12-14: When CSO and CSl 
are high and -CS2 is low, the chip is selected. Chip selection is 
complete when the decoded chip select signal is latched with an 
active (low) address strobe (-ADS) input. This enables 
communications between the INS8250 and the system unit's 
microprocessor. 



Asynchronous Adapter 25 



Data Input Strobe (DISTR, -DISTR), Pins 22 and 21: When 
DISTR is high or -DISTR is low while the chip is selected, it 
allows the system unit's microprocessor to read status information 
or data from a selected register of the INS8250. 

Note: Only an active DISTR or -DISTR input is required to 
transfer data from the INS8250 during a read operation. 
Therefore, tie either the DISTR input permanently low or the 
-DISTR line input permanently high, if not used. 

Data Output Strobe (DOSTR, -DOSTR), Pins 19 and 18: When 
DOSTR is high or -DOSTR is low while the chip is selected, it 
allows the system unit's microprocessor to write data or control 
words into a selected register of the INS8250. 

Note: Only an active DOSTR or -DOSTR input is required to 
transfer data to the INS8250 during a write operation. 
Therefore, tie either the DOSTR input permanently low or the 
-DOSTR input permanently high, if not used. 

Address Strobe (-ADS), Pin 25: When low, provides latching for 
the register select (AO, Al, A2) and chip select (CSO, CSl, -CS2) 
signals. 

Note: An active -ADS input is required when the register 
select (AO, Al, A2) signals are not stable for the duration of a 
read or write operation. If not required, tie the ADS input 
permanently low. 

Register Select (AO, Al, A2), Pins 26-28: These three inputs are 
used during a read or write operation to select an INS8250 
register to read or write to as indicated in the following table. 
Note that the state of the divisor latch access bit (DLAB), which 
is the most significant bit of the line-control register, affects the 
selection of certain INS8250 registers. The DLAB must be set 
high by the system software to access the baud-rate generator 
divisor latches. 



26 Asynchronous Adapter 



DLAB 


A2 


A1 


AO 


Register 














Receiver Buffer (Read), Transmitter 
Holding Register (Write) 













Interrupt Enable 


X 





1 





Interrupt Identification (Read Only) 


X 





1 




Line Control 


X 


1 








Modem Control 


X 


1 







Line Status 


X 


1 


1 





Modem Control Status 


X 


1 


1 




None 


1 











Divisor Latch (Least Significant Bit) 


1 










Divisor Latch (Most Significant Bit) 



Master Reset (MR), Pin 35: When high, clears all registers 
(except the receiver buffer, transmitter holding, and divisor 
latches), and the control logic of the INS8250. Also, the state of 
various output signals (SOUT, INTRPT, -OUT 1, -OUT 2, -RTS, 
-DTR) are affected by an active MR input. Refer to the 
''Asynchronous Communications Reset Functions" table. 

Receiver Clock (RCLK), Pin 9: This input is the 16 x baud-rate 
clock for the receiver section of the chip. 

Serial Input (SIN), Pin 10: Serial data input from the 
communications link (peripheral device, modem, or data set). 

Clear to Send (-CTS), Pin 36: The -CTS signal is a modem 
control function input whose condition can be tested by the 
system unit's microprocessor by reading bit 4 (CTS) of the 
modem status register. Bit (DCTS) of the modem status 
register indicates whether the CTS input has changed state since 
the previous reading of the modem status register. 

Note: Whenever the CTS bit of the modem status register 
changes state, an interrupt is generated if the modem status 
interrupt is enabled. 

Data Set Ready (-DSR), Pin 37: When low, indicates that the 
modem or data set is ready to establish the communications link 
and transfer data with the INS8250. The -DSR signal is a 
modem-control function input whose condition can be tested by 



Asynchronous Adapter 27 



the system unit's microprocessor by reading bit 5 (DSR) of the 
modem status register. Bit 1 (DDSR) of the modem status 
register indicates whether the -DSR input has changed since the 
previous reading of the modem status register. 

Note: Whenever the DSR bit of the modem status register 
changes state, an interrupt is generated if the modem status 
interrupt is enabled. 

Received Line Signal Detect (-RLSD), Pin 38: When low, 
indicates that the data carrier had been detected by the modem or 
data set. The -RLSD signal is a modem-control function input 
whose condition can be tested by the system unit's 
microprocessor by reading bit 7 (RLSD) of the modem status 
register. Bit 3 (DRLSD) of the modem status register indicates 
whether the RLSD input has changed state since the previous 
reading of the modem status register. 

Note: Whenever the RLSD bit of the modem status register 
changes state, an interrupt is generated if the modem status 
interrupt is enabled. 

Ring Indicator (-RI), Pin 39: When low, indicates that a telephone 
ringing signal has been received by the modem or data set. The 
-RI signal is a modem-control function input whose condition can 
be tested by the system unit's microprocessor by reading bit 6 
(RI) of the modem status register. Bit 2 (TERI) of the modem 
status register indicates whether the -RI input has changed from a 
low to high state since the previous reading of the modem status 
register. 

Note: Whenever the RI bit of the modem status register 
changes from a high to a low state, an interrupt is generated if 
the modem status interrupt is enabled. 

VCC, Pin 40: -h5 Vdc supply. 

VSS, Pin 20: Ground (0 Vdc) reference. 



28 Asynchronous Adapter 



Output Signals 

Data Terminal Ready (-DTR), Pin 33: When low, informs the 
modem or data set that the INS8250 is ready to communicate. 
The -DTK output signal can be set to an active low by 
programming bit (DTR) of the modem control register to a high 
level. The -DTR signal is set high upon a master reset operation. 

Request to Send (-RTS), Pin 32: When low, informs the modem 
or data set that the INS8250 is ready to transmit data. The -RTS 
output signal can be set to an active low by programming bit 1 
(RTS) of the modem control register to a high level. The -RTS 
signal is set high upon a master reset operation. 

Output 1 (-OUT 1), Pin 34: User-designated output that can be 
set to an active low by programming bit 2 (-OUT 1) of the 
modem control register to a high level. The -OUT 1 signal is set 
high upon a master reset operation. 

Output 2 (-OUT 2), Pin 31: User-designated output that can be 
set to an active low by programming bit 3 (-OUT 2) of the 
modem control register to a high level. The -OUT 2 signal is set 
high upon a master reset operation. 

Chip Select Out (CSOUT), Pin 24: When high, indicates that the 
chip has been selected by active CSO, CSl, and -CS2 inputs. No 
data transfer can be initiated until the CSOUT signal is a logical 
1. 

Driver Disable (DDIS), Pin 23: Goes low whenever the system 
unit's microprocessor is reading data from the INS8250. A 
high-level DDIS output can be used to disable an external 
transceiver (if used between the system unit's microprocessor and 
the INS8250 on the D7-D0 data bus) at all times, except when 
the system unit's microprocessor is reading data. 

Baud Out (-BAUDOUT), Pin 15: 16 x clock signal for the 
transmitter section of the INS8250. The clock rate is equal to the 
main reference oscillator frequency divided by the specified 
divisor in the baud-rate generator divisor latches. The 
-BAUDOUT may also be used for the receiver section by typing 
this output to the RCLK input of the chip. 



Asynchronous Adapter 29 



Interrupt (INTRPT), Pin 30: Goes high whenever any one of the 

following interrupt types has an active high condition and is 
enabled through the interrupt enable register: receiver error flag, 
received data available, transmitter holding register empty, or 
modem status. The INTRPT signal is reset low upon the 
appropriate interrupt service or a master reset operation. 

Serial Output (SOUT), Pin 11: Composite serial data output to 
the communications link (peripheral device, modem, or data set). 
The SOUT signal is set to the marking (logical 1) state upon a 
master reset operation. 



Input/ Output Signals 

Data Bus (D7-D0), Pins 1-8: This bus comprises eight tri-state 
input/output lines. The bus provides bidirectional 
communications between the INS8250 and the system unit's 
microprocessor. Data, control words, and status information are 
transferred through the D7-D0 data bus. 

External Clock Input/Output (XTALl, XTAL2), Pins 16 and 17: 

These two pins connect the main timing reference (crystal or 
signal clock) to the INS8250. 



30 Asynchronous Adapter 



Specifications 



The following page shows the connecter pin assignments and 
specifications for the Asynchronous Communications Adapter. 



Asynchronous Adapter 31 




External 
Device 



25-Pin D-Shell connector 



O 
O 



Description 
NC 



Transmitted Data 



Received Data 



Request to Send 



Clear to Send 



Data Set Ready 



Signal Ground 



Received Line Signal Detector 



+ Transmit Current Loop Data 



NC 



- Transmit Current Loop Data 



NC 



NC 



NC 



NC 



NC 



NC 



+ Receive Current Loop Data 



NC 



Data Terminal Ready 



NC 



Ring Indicator 



NC 



NC 



- Receive Current Loop Return 



25 



14 



Pin 
1 



10 



11 



12 



13 



14 



15 



16 



17 



18 



19 



20 



21 



22 



23 



24 



25 



Asynchronous 
Communications 
Adapter 
(RS-232C) 



Note: To avoid inducing voltage surges on interchange circuits, signals from 
interchange circuits shall not be used to drive inductive devices, such a 
relay coils. 

Connector Specifications 
32 Asynchronous Adapter 



> 

o 

o 
o 






JIO-O/^F X.047//F j.047^F j.047m F 




J-B25 CARD EDGE TAB 
-824 CARD EDGE TAB 



^l 



RCLK BAUD OUT 



25-PIN D-SHELL +5Vo- 
C DWNECTO R 

IHEIA CARRIER PET | 




Asynchronous Communications Adapter (Sheet 1 of 1) 



o 

(TQ 



&5 
CTQ 

C/5 



34 Asynchronous Adapter 



Index 



address strobe (-ADS) 26 



B 



baud out (-BAUDOUT) 29 
baud-rate generator 7, 9 
BI (break interrupt) 1 1 
break interrupt (BI) 1 1 



chip select (CS0,CS1,-CS2) 26 
chipselect (CSO, CS1,CS2) 25 
chip select out (CSOUT) 29 
clear to send (-CTS) 27 
clear to send (CTS) 27 
CTS (clear to send) 27 
current-loop interface 20, 23 



Index- 1 



D 



data bus (D7-D0) 30 

data input strobe (-DISTR) 26 

data input strobe (DISTR) 26 

data output strobe (-DOSTR) 26 

data output strobe (DOSTR) 26 

data ready (DR) 10 

data set ready (-DSR) 27 

data set ready (DSR) 27 

data speed 9 

data terminal ready (-DTR) 15, 29 

DCTS (delta clear to send) 17, 27 

DDSR (delta data set ready) 17, 27 

delta clear to send (DCTS) 17, 27 

delta data set ready (DDSR) 17, 27 

delta received line signal detect (DRLSD) 17 

diagnostic capabilities 1,16 

diagnostic mode 1 6 

divisor latch access bit (DLAB) 3, 7, 26 

divisor latches 7 

DLAB (divisor latch access bit) 7, 26 

DR (data ready) 10 

driver disable (DDIS) 29 

DRLSD (delta received line signal detect) 17 



E 

external clock input/output 30 



FE (framing error) 1 1 
framing error (FE) 1 1 



Index-2 



I 



IIR (Interrupt Identification Register) 12, 14 
input signals 25 

-ADS (address strobe) 26 

-CS2 (chip select) 25,26 

-CTS (clear to send) 27 

-DISTR (data input strobe) 26 

-DOSTR (data output strobe) 26 

-DSR (data set ready) 27 

-RI (ring indicator) 18, 28 

-RLSD (received line signal detect) 18, 28 

AO (register select) 3, 26 

Al (register select) 3, 26 

A2 (register select) 3, 26 

CSO (chip select) 25,26 

CSl (chip select) 25,26 

DISTR (data input strobe) 26 

DOSTR (data output strobe) 26 

DSR (data set ready) 27 

MR (master reset) 27 

RCLK (receiver clock) 27 

SIN (serial input) 16, 27 

VCC 28 

VSS 28 

XTALl (external clock input/output) 30 
input/output signals 30 

D7-D0 (data bus) 30 

XTAL2 (external clock input/output) 30 
INS8250 4, 25 

INS8250 functional pin description 25 
interface 23 

interrupt (INTRPT) 14, 30 
interrupt enable register 14 
interrupt identification register (IIR) 12, 14 
interrupts 21 
INTRPT (interrupt) 14, 30 



Index-3 



line status register (LSR) 10 
line-control register 5 
logic diagrams 33 
LSR (line status register) 10 



M 



master reset (MR) 27 
modem control function 2 
modem control inputs 16 
modem control interrupts 16 
modem control outputs 16 
modem control register 15 
modem status 12 
modem status interrupt 15, 17, 27 
modem status register 16, 27, 28 
modes of operation 3 



o 



OE (overrun error) 10 

output signals 29 

-BAUDOUT (baud out) 29 
-DTR (data terminal ready) 15,29 
-OUT 1 (output 1) 15, 29 
-OUT 2 (output 2) 16,29 
-RTS (request to send) 15, 29 
CSOUT (chip select out) 29 
DDIS (driver disable) 29 
SOUT (serial output) 7, 16, 30 

output 1 (-OUT 1) 15, 29 

output 2 (-OUT 2) 16,29 

overrun error (OE) 10 



Index-4 



parity error (PE) 10 
PE (parity error) 10 
programmable baud-rate generator 
programming considerations 3 



R 



received line signal detect (-RLSD) 18, 28 
receiver buffer register 1 8 
receiver clock (RCLK) 27 
register select (AO, Al, A2) 3, 26 
request to send (-RTS) 15,29 
ring indicator (-RI) 28 



selecting the adapter address 20 

selecting the interface format and Adapter Address 20 

serial input (SIN) 16,27 

serial output (SOUT) 7, 16, 30 

specifications 31 



Index-5 



TERI (trailing edge of the ring indicator) 17 
THRE (transmitter-holding-register-empty) 11, 12 
trailing edge of the ring indicator (TERI) 17 
transmitter holding register 12,19 
transmitter-holding-register-empty (THRE) 11, 12 
transmitter-shift-register-empty (TSRE) 1 1 
TSRE (transmitter-shift-register-empty) 1 1 



voltage interchange information 24 
voltage interface 24 



Index- 6 



Personal Computer 
Hardware Reference 
Library 



Serial/Parallel Adapter 



Contents 



Description 1 

Serial Portion of the Adapter 1 

Parallel Portion of the Adapter 20 

Specifications 25 

Logic Diagrams 27 



111 



Notes: 



IV 



Description 



The IBM Personal Computer AT Serial/Parallel Adapter provides 
a parallel port and a serial port. It plugs into a system-board 
expansion slot. All system-control signals and voltage 
requirements are provided through a 2- by 31 -position card edge 
connector. 



Serial Portion of the Adapter 

The serial portion of the adapter is fully programmable and 
supports asynchronous communications. It will add and remove 
start, stop, and parity bits. A programmable baud-rate generator 
allows operation from 50 baud to 9600 baud. Five-, six-, seven- 
and eight-bit characters with 1, 1.5, or 2 stop bits are supported. 
A prioritized interrupt system controls transmit, receive, error, 
and line status as well as data-set interrupts. 

The rear of the adapter has a 9-pin D-shell connector that is 
classified as an RS-232C port. When the optional IBM 
Communications Cable (9-Pin), which has a 9-pin D-shell 
connector on one end and a 25 -pin D-shell connector on the 
other end, is connected to the adapter, the 25 -pin end of the cable 
has all the signals of a standard EIA RS-232C interface. 



August 31, 1984 

Personal Computer AT Serial/Parallel Adapter 1 



The following figure is a block diagram of the serial portion of the 
adapter. 



Address 
Bus 



Address 
Decode 


Chip Select 




Register 
Select 



Data Bus 



Interrupt 



Oscillator 
1.8432 MHz 



EIA 
Receivers 



Controller 
Asynchronous 
Communications 
Chip 



9-Pin h<- 

Connector 



EIA 
Drivers 



Serial Portion Blocic Diagram 

The serial portion of the adapter has a controller that provides the 
following functions: 

• Adds or deletes standard, asynchronous-communications bits 
to or from a serial data stream. 

• Provides full, double buffering, which eliminates the need for 
precise synchronization. 

• Provides a programmable baud-rate generator. 

Provides modem controls (CTS, RTS, DSR, DTR, RI, and 
CD). 



2 Personal Computer AT Serial/Parallel Adapter 



August 31, 1984 



Communications Application 

The serial output port may be addressed as either communications 
port 1 or communications port 2 as defined by jumper Jl (see the 
following figure). In this section hex addresses begin with an X 
which can be either a 3 for communications port 1 (interrupt level 
4) or a 2 for communications port 2 (interrupt level 3). 




Port 1 



Port 2 



The data format will be as follows: 



DO D1 D2 D3 D4 D5 D6 D7 

TTTTTTTT 



Marking 



Start 
Bit 



Parity 
Bit 



Stop 
Bit 



Bit is the first data bit to be sent or received. The controller 
automatically inserts the start bit, the correct parity bit (if 
programmed to do so), and the stop bit (1, 1.5, or 2, depending 
on the command in the line-control register). 



August 31, 1984 



Personal Computer AT Serial/Parallel Adapter 3 



Controller Specifications 

The following describes the function of controller input/output 
signals. 



Input Signals 

-Clear to Send: (-CTS), Pin 36— The ' -CTS ' signal is a 
modem-control function input, the condition of which can be 
tested by the processor by reading bit 4 (-CTS) of the modem 
status register. Bit (DCTS) of the modem status register 
indicates if the ' -CTS ' input has changed state since the previous 
reading. 

Note: Whenever the CTS bit of the modem status register 
changes state, an interrupt is generated if the modem-status 
interrupt is enabled. 

-Data Set Ready: (-DSR), Pin 37 — When low, indicates the 
modem or data set is ready to estabUsh the communications link 
and transfer data with the controller. The ' -DSR ' signal is a 
modem-control function input, the condition of which can be 
tested by the processor reading bit 5 (-DSR) of the modem status 
register. Bit 1 (DDSR) of the modem status register indicates if 
the ' -DSR ' input has changed since the previous reading. 

Note: Whenever the DSR bit of the modem status register 
changes state, an interrupt is generated if the modem-status 
interrupt is enabled. 

-Data Carrier Detect: (-DCD), Pin 38— When low, indicates 
the modem or data set detected a data carrier. The ' -DCD ' 
signal is a modem-control function input, the condition of which 
can be tested by the processor reading bit 7 (-DCD) of the 
modem status register. Bit 3 (DDCD) of the modem status 
register indicates if the ' -DCD ' input has changed state since the 
previous reading. 

Note: Whenever the DCD bit of the modem status register 
changes state, an interrupt is generated if the modem status 
interrupt is enabled. 



August 31, 1984 
4 Personal Computer AT Serial/Parallel Adapter 



-Ring Indicator: (-RI), Pin 39 — When low, indicates the modem 
or data set detected a telephone ringing signal. The ' -RI ' signal 
is a modem-control function input, the condition of which can be 
tested by the processor reading bit 6 (-RI) of the modem status 
register. Bit 2 (TERI) of the modem status register indicates if 
the * -RI ' input has changed from an active to an inactive state 
since the previous reading. 

Note: Whenever the RI bit of the modem status register 
changes from an inactive to an active state, an interrupt is 
generated if the modem-status interrupt is enabled. 

VCC Pin 40— +5 Vdc supply 

VSS Pin 20— Ground (0 Vdc) reference 



Output Signals 

-Data Terminal Ready: (-DTR), Pin 33 — When active, informs 
the modem or data set that the controller is ready to 
communicate. The ' -DTR ' output signal can be set to an active 
level by programming bit (-DTR) of the modem control register 
to an active level. The ' -DTR ' signal is set inactive upon a 
master reset operation. 

-Request to Send: (-RTS), Pin 32 — When active, informs the 
modem or data set that the controller is ready to send data. The 
' -RTS ' output signal can be set to an active level by 
programming bit 1 (-RTS) of the modem control register to an 
active level. The ' -RTS ' signal is set inactive upon a master reset 
operation. 

-Output 1: (-OUT 1), Pin 34 — User-designated output that can 
be set to an active level by programming bit 2 (-OUT 1) of the 
modem control register to an inactive level. The ' -OUT 1 ' signal 
is set inactive upon a master reset operation. Pin 34 is connected 
to an active source. 

-Output 2: (-OUT 2), Pin 31 — User-designated output that can 
be set to an active level by programming bit 3 (-OUT 2) of the 
modem control register to an inactive level. The ' -OUT 2 ' signal 
is set inactive upon a master reset operation. Pin 3 1 controls 
interrupts to the system. 

August 31, 1984 

Personal Computer AT Serial/Parallel Adapter 5 



Controller- Accessible Registers 

The controller has a number of accessible registers. The system 
programmer may gain access to or control any of the controller 
registers through the microprocessor. These registers are used to 
control the controller's operations and to transmit and receive 
data. The X in the register address determines the the port 
selected; 3 is for port 1 and 2 is for port 2. 

Specific registers are selected according to the following figure: 



I/O Address 


Register Selected 


DLAB State 


XF8 


TX Buffer 


(Write) 


XF8 


RX Buffer 


(Read) 


XF8 


Divisor Latch LSB 


1 


XF9 


Divisor Latch iVISB 


1 


XF9 


Interrupt Enable Register 





XFA 


Interrupt Identification Register 




XFB 


Line Control Register 




XFC 


Modem Control Register 




XFD 


Line Status Register 




XFE 


Modem Status Register 




XFF 


Reserved 





Controller-Accessible Registers 

Transmitter Holding Register (hex XF8): The transmitter 
holding register (THR) contains the character to be sent. 



Transmitter Holding Register (hex XF8) 



Bit 



7 6 5 4 3 2 10 



-► Data Bit 
-► Data Bit 1 
-► Data Bit 2 



-► Data Bit 3 
-► Data Bit 4 



-► Data Bit 5 
-► Data Bit 6 
-► Data Bit 7 



Transmitter Holding Register 



Bit is the least-significant bit and the first bit sent serially. 



6 Personal Computer AT Serial/Parallel Adapter 



August 31, 1984 



Receiver Buffer Register (hex XF8): The receiver buffer 
register (RBR) contains the received character. 



Receiver Buffer Register (hex XF8) 



Bit 7 6 5 4 3 2 10 



-► Data Bit 
-► Data Bit 1 
-► Data Bit 2 
-► Data Bit 3 
-► Data Bit 4 
-► Data Bit 5 



-► Data Bit 6 
-► Data Bit 7 



Receiver Buffer Register 

Bit is the least-significant bit and the first bit received serially. 

Programmable Baud-Rate Generator: The controller has a 
programmable baud-rate generator that can divide the clock input 
(1.8432 MHz) by any divisor from 1 to 655,535 or 2^^A. The 
output frequency of the baud-rate generator is the baud rate 
multiplied by 16. Tv^o 8-bit latches store the divisor in a 16-bit 
binary format. These divisor latches must be loaded during setup 
to ensure desired operation of the baud-rate generator. When 
either of the divisor latches is loaded, a 16-bit baud counter is 
immediately loaded. This prevents long counts on the first load. 

Divisor Latch LSB (hex XF8) 



Divisor Latch Least Significant Bit (hex XF8) 



Bit 7 6 5 4 3 2 10 



-► Bit 

-► Bit 1 

-► Bit 2 

-► Bits 

-► Bit 4 



-► Bits 
-► Bite 



-^ Bit 7 



Divisor Latch Least Significant Bit 



August 31, 1984 



Personal Computer AT Serial/Parallel Adapter 7 



Divisor Latch MSB (hex XF9) 



Divisor Latch IVIost Significant Bit (hex XF9) 



Bit 



7 6 5 4 3 2 10 



-► BitO 
-► Bit 1 



-► Bit 2 

-► Bits 

-► Bit 4 

-► Bits 

-► Bite 



-► Bit 7 



Divisor Latch IVIost Significant Bit 

Interrupt Enable Register (hex XF9): This 8 -bit register allows 
the four types of controller interrupts to separately activate the 
' chip-interrupt ' (INTRPT) output signal. The interrupt system 
can be totally disabled by resetting bits through 3 of the 
interrupt enable register (lER). Similarly, by setting the 
appropriate bits of this register to logical 1 , selected interrupts can 
be enabled. Disabling the interrupt system inhibits the ' lER ' and 
the active ' INTRPT ' output from the chip. All other system 
functions operate normally, including the setting of the line-status 
and modem-status registers. 



Interrupt Enable Register (hex XF9) 



Bit 



7 6 5 4 3 2 10 



->- Received-Data-Available Interrupt 
-► Transmitter-Holding- Register-Empty 



-► Receiver-Line-Status Interrupt 
-► Modem-Status Interrupt 



-► =0 



-►=0 



Interrupt Enable Register 

Bit When set to logical 1 , enables the 

received-data-available interrupt. 



8 Personal Computer AT Serial/Parallel Adapter 



August 31, 1984 



Bit 1 When set to logical 1 , enables the 

transmitter-holding-register-empty interrupt. 

Bit 2 When set to logical 1 , enables the receiver-line-status 

interrupt. 

Bit 3 When set to logical 1 , enables the modem-status 

interrupt. 

Bits 4-7 These four bits are always logical 0. 

Interrupt Identification Register (hex XFA): The controller has 
an on-chip interrupt capabiUty that makes communications 
possible with all of the currently popular microprocessors. In 
order to minimize programming overhead during data character 
transfers, the controller prioritizes interrupts into four levels: 
receiver-line-status (priority 1), received-data-available (priority 
2), transmitter-holding-register-empty (priority 3), and modem 
status (priority 4). 

Information about a pending prioritized interrupt is stored in the 
interrupt identification register (IIR). (See the figure "Interrupt 
Control Functions," later.) The IIR, when addressed during 
chip-select time, stops the pending interrupt with the highest 
priority, no other interrupts are acknowledged until the processor 
services that interrupt. 



Interrupt identification Register (liex XFA) 



Bit 



7 6 5 4 3 2 10 



-► if Interrupt Pending 
-► Interrupt ID Bit 
-► Interrupt ID Bit 1 
■-► =0 
-► =0 



-► =0 
-► =0 



-► =0 



Interrupt Identification Register 



Bit This bit can be used in either hard- wired, prioritized, 

or polled conditions to indicate if an interrupt is 
pending. When bit is logical 0, an interrupt is 
pending, and the IIR contents may be used as a 

August 31, 1984 

Personal Computer AT Serial/Parallel Adapter 9 



pointer to the appropriate interrupt service routine. 
When bit is logical 1 , no interrupt is pending, and 
polling (if used) continues. 

Bits 1-2 These two bits identify the pending interrupt that has 
the highest priority, as shown in the following figure: 



Interrupt 

ID 

Register 


Interrupt Set And Reset Functions 


Bit 
2 


Bit 

1 


Bit 



Priority 
Level 


Interrupt 
Type 


Interrupt 
Source 


Interrupt 
Reset Control 











- 


None 


None 


- 


1 


1 





Highest 


Receiver 

Line 

Status 


Overrun Error 

or 
Parity Error 

or 
Framing Error 

or 
Break Interrupt 


Reading the Line 
Status Register 


1 








Second 


Received 

Data 

Available 


Receiver Data 
Available 


Reading the Receiver 
Buffer Register 





1 





Third 


Transmitter 
Holding 
Register 
Empty 


Transmitter 
Holding 
Register Empty 


Reading the MR 
(if source of interrupt) 
or writing into the 
THR 











Fourth 


Modem 
Status 


Clear to Send 

or 
Data Set Ready 

or 
Ring Indicator 

or 
Received Line 
Signal Detect 


Reading the Modem 
Status Register 



Interrupt Priority 

Bits 3-7 These five bits are always logical 0. 

Line-Control Register (hex XFB): The system programmer 
specifies the format of the asynchronous data communications 
exchange through the Hne control register. In addition to 



10 Personal Computer AT Serial/Parallel Adapter 



August 31, 1984 



controlling the format, the programmer may retrieve the contents 
of the Une control register for inspection. This feature simplifies 
system programming and eliminates the need to store Une 
characteristics separately in system memory. 



Line Control Register (hex XFB) 



Bit 



7 6 5 4 3 2 10 



^ 
^ 
^ 
> 
> 



Word Length Select Bit 
► Word Length Select Bit 1 
Number of Stop Bits 
Parity Enable 
Even Parity Select 



-► Stuck Parity 

-► Set Break 

->" Divisor Latch Access Bit 



Line Control Register 

Bits 0, 1 These two bits specify the number of bits in each 

serial character that is sent or received. The 
encoding of bits and 1 is as follows: 



BitO 


BItl 


Word Length (Bits) 





1 
1 



1 


1 


5 
6 

7 
8 



Word Length 



Bit 2 



This bit specifies the number of stop bits in each 
serial character that is sent or received. If bit 2 is a 
logical 0, one stop bit is generated or checked in the 
data sent or received. If bit 2 is logical 1 when a 
5 -bit word length is selected through bits and 1, 
1-1/2 stop bits are generated or checked. If bit 2 is 
logical 1 when either a 6-, 7-, or 8-bit word length 
is selected, two stop bits are generated or checked. 



Bit 3 



This bit is the parity-enable bit. When bit 3 is 
logical 1 , a parity bit is generated (transmit data) or 
checked (receive data) between the last data word 



August 31, 1984 



Personal Computer AT Serial/ParaUel Adapter 11 



and stop bit of the serial data. (The parity bit is 
used to produce an even or odd number of I's when 
the data-word bits and parity bit are summed.) 

Bit 4 This bit is the even-parity-select bit. When bit 3 is 

a logical 1 and bit 4 is a logical 0, an odd number of 
logical 1 's are sent or checked in the data word bits 
and parity bit. When both bit 3 and bit 4 are a 
logical 1 , an even number of bits are sent or 
checked. 

Bit 5 This bit is the stuck-parity bit. When bit 3 is a 

logical 1 and bit 5 is a logical 1 , the parity bit is sent 
and then detected by the receiver as a logical 0, if 
bit 4 is a logical 1 , or as a logical 1 if bit 4 is a 
logical 0. 

Bit 6 This bit is the set-break control bit. When bit 6 is 

set to a logical 1, the serial output (SOUT) is forced 
to the spacing (logical 0) state and remains there 
regardless of other transmitter activity. The 
set-break is disabled by setting bit 6 to logical 0. 
This feature enables the microprocessor to select a 
specific terminal in a computer communications 
system. 

Bit 7 This bit is the divisor-latch access bit (DLAB). It 

must be set high (logical 1 ) to gain access to the 
divisor latches of the baud-rate generator during a 
read or write operation. It must be set low (logical 
0) to gain access to the receiver buffer, the 
transmitter holding register, or the interrupt enable 
register. 



August 31, 1984 
12 Personal Computer AT Serial/Parallel Adapter 



Modem Control Register (hex XFC): This 8-bit register 
controls the data exchange with the modem or data set (an 
external device acting as a modem). 



Modem Control Register (hex XFC) 



Bit 



7 6 5 4 3 2 10 



-^^ Data Terminal Ready 
-► Request to Send 



-►Out 1 
-►Out 2 



->- Loop 
-► =0 



-► =0 
-► =0 



Modem Control Register 

Bit This bit controls the ' -data terminal ready ' (-DTR) 

output. When bit is set to logical 1, the -DTR 
output is forced active. When bit is reset to logical 

0, the ' -DTR ' output is forced inactive. 

Bit 1 This bit controls the ' -request-to-send ' (-RTS) 

output. Bit 1 affects the ' -RTS ' output in the same 
way bit affects the ' -DTR ' output. 

Bit 2 This bit controls the ' -Output 1 ' (-OUT 1) signal, 

which is a spare the programmer can use. Bit 2 
affects the ' -OUT 1 ' output in the same way bit 
affects the ' -DTR ' output. 

Bit 3 This bit controls the ' -Output 2 ' (-OUT 2) signal, 

which is a spare the programmer can use. Bit 3 
affects the ' -OUT 2 ' output in the same way bit 
affects the ' -DTR ' output. 

Bit 4 This bit provides a loopback feature for diagnostic 

testing of the controller. When bit 4 is set to logical 

1, the following occur: the 'transmitter serial output' 
(SOUT) is set to the active state; the 'receiver serial 
input ' (SIN) is disconnected; the output of the 
transmitter shift register is "looped back" to the 
receiver shift register input; the four modem-control 
inputs ( • -CTS ' , ' -DSR ' , ' -RLSD ' , and ' -RI ' ) are 



August 31, 1984 



Personal Computer AT Serial/Parallel Adapter 13 



disconnected; and the four modem-control outputs 
C-DTR', '-RTS', '-OUT1' and '-OUT 2') are 
internally connected to the four modem control 
inputs. In the diagnostic mode, data sent is 
immediately received. This feature allows the 
processor to verify the transmit- and receive-data 
paths of the controller. 

In the diagnostic mode, the receiver and transmitter 
interrupts are fully operational, as are the 
modem-control interrupts. But the interrupts' 
sources are now the lower four bits of the modem 
control register (MCR) instead of the four 
modem-control inputs. The interrupts are still 
controlled by the interrupt enable register. 

The controller's interrupt system can be tested by 
writing to the lower six bits of the line status register 
and the lower four bits of the modem status register. 
Setting any of these bits to logical 1 generates the 
appropriate interrupt (if enabled). Resetting these 
interrupts is the same as for normal controller 
operation. To return to normal operation, the 
registers must be reprogrammed for normal 
operation, and then bit 4 of the MCR must be reset 
to logical 0. 

Bits 5-7 These bits are permanently set to logical 0. 



August 31, 1984 
14 Personal Computer AT Serial/Parallel Adapter 



Line Status Register (hex XFD): This 8 -bit register provides 
the processor with status information about the data transfer. 



Line Status Register (hex XFD) 



Bit 



7 6 5 4 3 2 10 



-► Data Ready 
-► Overrun Error 



-► Parity Error 
-► Framing Error 



-► Break Interrupt 

-► Transmitter Holding Register Empty 



Tx Shift Register Empty 
■ =0 



Line Status Register 

Bit This bit is the receiver data ready (DR) indicator. It 

is set to logical 1 whenever a complete incoming 
character has been received and transferred into the 
receiver buffer register. Bit may be reset to logical 
by reading the data in the receiver buffer register. 

Bit 1 This bit is the overrun error (OE) indicator. It 

indicates that data in the receiver's buffer register 
was not read by the processor before the next 
character was transferred into the register, thereby 
destroying the previous character. The OE indicator 
is reset whenever the processor reads the contents of 
the Une status register. 

Bit 2 This bit is the parity error (PE) indicator and 

indicates the received data character does not have 
the correct even or odd parity, as selected by the 
even-parity-select bit. The PE bit is set to logical 1 
upon detection of a parity error, and is reset to 
logical whenever the processor reads the contents 
of the Une status register. 

Bit 3 This bit is the framing error (FE) indicator. It 

indicates the received character did not have a vaUd 
stop bit. Bit 3 is set to logical 1 whenever the stop 
bit following the last data bit or parity bit is detected 
as a zero bit (spacing level). 



August 31, 1984 



Personal Computer AT Serial/ParaUel Adapter 15 



Bit 4 This bit is tlie break interrupt (BI) indicator. It is set 

to logical 1 whenever the received data input is held 
in the spacing state (logical 0) for longer than a full 
word transmission time (that is, the total time of 
start bit + data bits + parity bits + stop bits). 

Note: Bits 1 through 4 are error conditions that 
produce a receiver line-status interrupt 
whenever any of the corresponding conditions 
are detected. 

Bit 5 This bit is the transmitter holding register empty 

(THRE) indicator. It indicates the controller is 
ready to accept a new character for transmission. In 
addition, this bit causes the controller to issue an 
interrupt to the processor when the THRE interrupt 
enable is set active. The THRE bit is set to logical 1 
when a character is transferred from the transmitter 
holding register into the transmitter shift register. It 
is reset to logical when the processor loads the 
transmitter holding register. 

Bit 6 This bit is the transmitter empty (TEMT) indicator. 

It is set to logical 1 whenever the transmitter holding 
register (THR) and the transmitter shift register 
(TSR) are both empty. It is reset to logical if THR 
or TSR contain a data character. 

Bit 7 This bit is permanently set to logical 0. 



August 31, 1984 
16 Personal Computer AT Serial/Parallel Adapter 



Modem Status Register (hex XFE): The 8-bit MSR provides 
the current state of the control Unes from the modem (or external 
device) to the processor. In addition, four bits of the MSR 
provide change information. These four bits are set to logical 1 
whenever a control input from the modem changes state. They 
are reset to logical whenever the processor reads this register. 



Modem Status Register (hex XFE) 



Bit 



7 6 5 4 3 2 10 



-► Delta Clear to Send 
-► Delta Data Set Ready 



-► Trailing Edge Ring Indicator 
-► Delta Data Carrier Detect 



-► Clear to Send 
-► Data Set Ready 
-► Ring Indicator 
-^^ Data Carrier Detect 



Modem Status Register 

Bit This bit is the delta clear-to-send (DCTS) indicator. 

It indicates the ' -CTS ' input to the chip has changed 
state since the last time it was read by the processor. 

Bit 1 This bit is the delta data-set-ready (DDSR) 

indicator. It indicates the ' -DSR ' input to the chip 
has changed state since the last time it was read by 
the processor. 

Bit 2 This bit is the trailing-edge ring-indicator (TERI) 

detector. It indicates the ' -RI ' input to the chip has 
changed from an active condition to an inactive 
condition. 

Bit 3 This bit is the delta data-carrier-detect (DDCD) 

indicator. It indicates the ' -DCD ' input to the chip 
has changed state. 

Note: Whenever bit 0, 1, 2, or 3 is set to a 
logical 1 , a modem status interrupt is generated. 

Bit 4 This bit is the opposite of the ' -clear-to-send ' 

(-CTS) input. If bit 4 of the MCR loop is set to a 
logical 1, this bit is equivalent to RTS of the MCR. 



August 31, 1984 



Personal Computer AT Serial/Parallel Adapter 17 



Bit 5 This bit is the opposite of the ' -data-set-ready ' 

(-DSR) input. If bit 4 of the MCR is set to a logical 
1, this bit is equivalent to DTR of the MCR. 

Bit 6 This bit is the opposite of the ' -ring-indicator ' (-RI) 

input. If bit 4 of the MCR is set to a logical 1, this 
bit is equivalent to OUT 1 of the MCR. 

Bit 7 This bit is the opposite of the ' -data-carrier-detect ' 

(-DCD) input. If bit 4 of the MCR is set to a logical 
1, this bit is equivalent to OUT 2 of the MCR. 



August 31, 1984 
18 Personal Computer AT Serial/Parallel Adapter 



Pin Assignment for Serial Port 



The following figure shows the pin assignments for the serial port 
in a communications environment. 








Carrier Detect 


1 










Receive Data 


2 










Transmit Data 


3 










Data Terminal Ready 


4 






External 




Signal Ground 


5 




Serial 

Parallel 

Aciapter 


Device 




Data Set Ready 


6 








Request To Send 


7 










Clear To Send 


8 










Ring Indicator 


9 



















August 31, 1984 



Personal Computer AT Serial/Parallel Adapter 19 



Parallel Portion of the Adapter 

The parallel portion of the adapter makes possible the attachment 
of various devices that accept eight bits of parallel data at 
standard TTL levels. The rear of the adapter has a 25-pin, 
D-shell connector. This port may be addressed as either parallel 
port 1 or 2. The port address is determined by the position of 
jumper J2, as shown in the following figure. 




?onz 



20 Personal Computer AT Serial/Parallel Adapter 



August 31, 1984 



The following figure is a block diagram of the parallel portion of 
the adapter. 



Data 
Bus 





Address 
Decode 


^ r 


uffer 

;ontrol 

Jgnals 




Address 


^ r 




Bus 


^ 1 




^ £ 






Interrupt 


























Data 

Output 

Buffer 




25-Pin D 
Connector 






Data 
Wrap 
Buffer 








■^ 


^^ 


"^ 




- 














^ 


Control 
Output 
Buffer 




Control Wrap 

and 
Signal Input 























Parallel Portion Block Diagram 

Printer Application 

The following discusses the use of the parallel portion of the 
adapter to connect to a parallel printer. Hexadecimal addresses in 
this section begin with an X, which is replaced with a 3 to indicate 
port 1, or a 2 to indicate port 2. 



Data Latch (hexX78, X7C) 

Writing to this address causes data to be stored in the printer's 
data buffer. Reading this address sends the contents of the 
printer's data buffer to the system microprocessor. 



Printer Controls (hex X7A, X7E) 

Printer control signals are stored at this address to be read by the 
system microprocessor. The following are bit definitions for this 
byte. 



August 31, 1984 



Personal Computer AT Serial/Parallel Adapter 21 



Bit 7 Not used 

Bit 6 Not used 

Bit 5 Not used 

Bit 4 +IRO Enable — A logical 1 in this position allows an 

interrupt to occur when ' -ACK ' changes from active to 
inactive. 

Bit 3 +SLCT IN — A logical 1 in this bit position selects the 
printer. 

Bit 2 -INIT — A logical starts the printer (50-microsecond 
pulse, minimum). 

Bit 1 + AUTO FD XT— A logical 1 causes the printer to 
line-feed after a line is printed. 

Bit + STROBE — A 0.5 -microsecond minimum, high, active 
pulse clocks data into the printer. Valid data must be 
present for a minimum of 0.5 microsecond before and 
after the strobe pulse. 



Printer Status - (hex X79, X7D) 

Printer status is stored at this address to be read by the 
microprocessor. The following are bit definitions for this byte. 

Bit 7 -BUSY — When this signal is active, the printer is busy 
and cannot accept data. It may become active during 
data entry, while the printer is offline, during printing, 
when the print head is changing positions, or while in an 
error state. 

Bit 6 -ACK — This bit represents the current state of the 
printer's ' -ACK ' signal. A means the printer has 
received the character and is ready to accept another. 
Normally, this signal will be active for approximately 5 
microseconds before ' -BUSY ' stops. 



August 31, 1984 
22 Personal Computer AT Serial/Parallel Adapter 



Bit 5 -hPE — A logical 1 means the printer has detected the 
end of paper. 

Bit 4 +SLCT — A logical 1 means the printer is selected. 

Bit 3 -Error — A logical means the printer has encountered 
an error condition. 

Bit 2 Unused. 

Bit 1 Unused. 

Bit Unused. 



August 31, 1984 

Personal Computer AT Serial/ParaUel Adapter 23 



Parallel Interface 

The adapter has a 25-pin, D-shell connector at the rear of the 
adapter. The following figure shows the signals and their pin 
assignments. Typical printer input signals also are shown. 




External 
Device 



-Strobe 



Data Bit 



Data Bit 1 



Data Bit 2 



Data Bit 3 



Data Bit 4 



Data Bit 5 



Data Bit 6 



Data Bit 7 



-ACK 



-BUSY 



PE 



SLCT 



-AUTO FEED XT 



-ERROR 



-INIT 



-SLCT IN 



Ground 



10 



11 



12 



13 



14 



15 



16 



17 



18-25 



Serial 

Parallel 

Adapter 



24 Personal Computer AT Serial/ParaUel Adapter 



August 31, 1984 



Specifications 

The following figures list characteristics of the output driver. 



Sink current 
Source Current 
High-level Output Voltage 
Low- Level Output Voltage 


24 mA 
-2.6 mA 
2.4 Vdc 
0.5 Vdc 


Max 
Max 
Min 
Max 




Parallel Data and Processor IRQ 






Sink Current 

Source Current 

High Level Output Voltage 

Low Level Output Voltage 


16 mA 
0.55 mA 
5 Vdc 
0.4 Vdc 


Max 
Max 

Minus Pull 
Max 


-Up 


Parallel Control 








Sink Current 

Source Current 

High Level Output Voltage 

Low Level Output Voltage 


24 mA 
-15 mA 
2.0 Vdc 
0.5 Vdc 


Max 
Max 
Min 
Max 





Parallel Processor Interface (Except IRQ) 

The following are the specifications for the serial interface. 
Function Condition 

On Spacing condition (binary 0, positive voltage). 

Off Marking condition (binary 1, negative voltage). 



Voltage 


Function 


Above +15 Vdc 


Invalid 


+3 Vdc to +15 Vdc 


On 


-3 Vdc to +3 Vdc 


Invalid 


-3 Vdc to -15 Vdc 


Off 


Below -15 Vdc 


Invalid 



Serial Port Functions 



August 31, 1984 



Personal Computer AT Serial/ParaUel Adapter 25 



Notes: 



August 31, 1984 
26 Personal Computer AT Serial/Parallel Adapter 



QTQ 

c 



00 
4^ 



3^ 

© 



o 
S 



H 

I 



(SHT 3) 
(SHT 3) 
(SHT 2) 




>► 
§- 






S) 
^ 



kLi''L.U Lz L L La U loo I 



i 



10J)uF ylOJDwF 



-j-|OD«F Y^' J^^ Y' 



T r r 



-1^ 



Serial/Printer Adapter (Sheet 1 of 3) 



00 

© 



n 

o 
5 

IS 

c 
<^ 

I 

a. 

PS 



e 

dQ 



u> 







Serial/Printer Adapter (Sheet 2 of 3) 



> 

c 

C 

^^ 






o 
SL 

n 

o 
3 

c 
H 

I 

Id 



§" 



(SHT1) • 

(SHT1) \ 

(SHT1) ! 

(SHT1) • 

(SHT1) ■ 

(SHT1) • 

(SHT1) . 

(SHT1) . 

(SHT1) . 



(SHT1) 
(SHT1) 
(SHT1) 
(SHT1) 
(SHT1) 



^^ 



^_rt 



''///////////// /////X7 



TCOfl 






TSvT ,8^ 


AO 






28~ 








27 


A2 






26 






8 


13 


-ENABLE SER I/O 




U2 


12 



I^ 



CSOUT 
DDIS 



< CS2 

XTAL2 



RLSD 
CIS 



■^ RCLK BAUD OUT 



.^^ 




'-'^H^g^^ 



RECEIVE DATA 



) PIN "D"SHaL " 
CONNECTOR 

~|EIA CARRIER DET 



7SIS^ 




EIA DATA SET ROY 



EIA CLR TO SND i 



+SVO— 
EIA RI 



\Z^1 



EIA RX DATA 



"^"1 









Serial/Printer Adapter (Sheet 3 of 3) 



Notes: 



August 31, 1984 
30 Personal Computer AT Serial/Parallel Adapter 



Personal Computer 
Hardware Reference 
Library 



IBM Binary 
Synchronous 
Communications 
Adapter 



6361499 



Contents 



Description 1 

Programming Considerations 3 

Typical Programming Sequence 3 

USART Programming 5 

Interface 9 

Specifications . 11 

Logic Diagrams 13 



lU 



IV 



Description 



The IBM Binary Synchronous Communications (BSC) Adapter 
provides an RS-232C--compatible communications interface for 
the IBM Personal Computer family of products. All system 
control, voltage, and data signals are provided through a 2- by 
3 1 -position card-edge connector. External interface is in the 
form of Electronic Industries Association (EIA) drivers and 
receivers connected to an RS-232C, standard 25-pin, D-shell 
connector. 

The adapter is programmed to operate in a binary synchronous 
mode. Maximum transmission rate is 9600 bits per second (bps). 
The main feature of the adapter is an Intel 8251 A Universal 
Synchronous/ Asynchronous Receiver/Transmitter (US ART). 
An Intel 8255A-5 Programmable Peripheral Interface (PPI) also 
is used for expanded modem operation, and an Intel 8253-5 
Programmable Interval Timer provides time-outs and generates 
interrupts. 

The following is a block diagram of the BSC adapter. 



Data 

Communications 

Equipment 




BSC Adapter Block Diagram 



BSC Adapter 1 



2 BSC Adapter 



Programming Considerations 



Before starting data transmission or reception, the system unit 
programs the BSC adapter to define control and gating ports, 
timer functions and counts, and the communications environment. 



Typical Programming Sequence 

The 8255A-5 Programmable Peripheral Interface (PPI) is set for 
the proper mode by selecting address hex 3A3 and writing the 
control word. This defines port A as an input, port B as an output 
for modem control and gating, and port C for 4-bit input and 
4-bit output. An output to port C sets the adapter to the wrap 
mode, disallows interrupts, and gates external clocks (address = 
hex 3A2, data = hex OD). The adapter is now isolated from the 
communication interface, and setup continues. 

Bit 4 of the PPFs port B brings the USART reset pin high, holds 
it, then drops it. This resets the internal registers of the USART. 



BSC Adapter 3 



The PPI's port assignments are as follows: 



8255 Port A Assignments 
Input Port 



Address: 



hex SAO for BSC 

hex 380 for Alternate BSC 



Bit 



L 



= Ring Indicate is on from Interface 
= Data Carrier Defect is on from Interface 
Oscillating = Transmit Clock Active 

= Clear-to-Send is on from Interface 
Oscillating = Receive Clock Active 

1 = TxRDY Active 

1 = Timer 2 Output Active 
1 = Timer 1 Output Active 



8255 Port B Assignments 
Output Port 



Address: hex 3A1 for BSC 

hex 381 for Alternate BSC 



Bit 



L 



= Turn on Data Signal Rate Selector 
= Turn on Select Standby 
= Turn on Test 

= Not Used 

= Reset 8251A 

= Gate Timer 2 

= Gate Timer 1 

= Gate Timers 1 and 2 to Interrupt Level 4 



8255 Port C Assignments 



Address: hex 3A2 for BSC 

hex 382 for Alternate BSC 



Bit 7 



5 ^ 


I : 


I : 


I 1 







1 = Gate Internal Clock (Output Bit) 
1 = Gate External Clock (Output Bit) 
1 = Electronic Wrap (Output Bit) 
= Enable Timer 1 and 2, Interrupt 6 and 

Receive Interrupt 3 
Oscillating = Receive Data (Input Bit) 
Oscillating = Timer Output (Input Bit) 
= Test Indicate Active (Input Bit) 
= BSC Adapter 



The USART uses the 8253-5 Programmable Interval Timer (PIT) 
in the synchronous mode for inactivity time-outs to interrupt the 
system unit after a preselected amount of time has elapsed from 
the start of a communication operation. Counter is not used for 
synchronous operation. Counters 1 and 2 connect to 



4 BSC Adapter 



interrupt-level 4 and, being programmed to terminal-count values, 
provide the desired time delay before generating a level-4 
interrupt. These interrupts signal the system that a predetermined 
amount of time has elapsed without a TxRDY (level 4) or an 
RxRDY (level 3) interrupt being sent to the system unit. 



USART Programming 

After the support devices on the BSC adapter are programmed, 
the USART is loaded with a set of control words that defines the 
communication environment. The control words consist of mode 
instructions and command instructions. 

Both the mode and command instructions must conform to a 
specified sequence for proper device operation. The mode 
instruction must be inserted immediately after a reset operation 
before using the USART for data communications. The required 
synchronization characters for the defined communication 
technique are then loaded into the USART (usually hex 32 for 
BSC). All control words written to the USART after the mode 
instruction will load the command instruction. Command 
instructions can be written to the USART in the data block any 
time during its operation. 

To return to the mode instruction, the master reset bit in the 
command instruction word is set to start an internal reset 
operation, which places the USART back into the mode 
instruction. Command instructions must follow the mode 
instructions or synchronization characters. 



BSC Adapter 5 



The following represents a typical data block and shows the mode 
instruction and command instruction. 



3A9 C/D = 1 
3A9 C/D = 1 
3A9 C/D = 1 
3A9 C/D = 1 



Mode Instruction 1 



SYNC Character 1 



SYNC Character 2 



Command Instruction 



3A8 C/D = r, 



Data 



3A9 C/D = 1 



^ 



Command Instruction 



3A8 C/D = 1 M 



3A9 C/D = 1 



Data 



# 



Command Instruction 



Typical Data Block 

The following are the communications interrupt levels. 

• Interrupt level 4 

- Transmit 

- Timer 1 

- Timer 2 

• Interrupt level 3 

- Receive 



6 BSC Adapter 



The following are device addresses. 



Hex Address 


Device 


Register Name 


Function 






Primary 


Alternate 








3A0 


380 


8255 


Port A Data 


Internal/External Serising 


3A1 


381 


8255 


Port B Data 


External Modem Interface 


3A2 


382 


8255 


Port C Data 


Internal Control 


3A3 


383 


8255 


Mode Set 


8255 Mode Initialization 


3A4 


384 


8253 


Counter OLSB 


Not Used in Sync. Mode 


3A4 


384 


8253 


Counter MSB 


Not Used in Sync. Mode 


3A5 


385 


8253 


Counter 1 LSB 


Inactivity Time Outs 


3A5 


385 


8253 


Counter 1 MSB 


Inactivity Time Outs 


3A6 


386 


8253 


Counter 2 LSB 


Inactivity Time Outs 


3A6 


385 


8253 


Counter 2 MSB 


Inactivity Time Outs 


3A7 


387 


8253 


Mode Register 


8253 Mode Set 


3A8 


388 


8251 


Data Select 


Data 


3A9 


389 


8251 


Command/Status 


USART Status 



Device Address Summary 



BSC Adapter 7 



8 BSC Adapter 



Interface 



The IBM Binary Synchronous Communications Adapter 
conforms to interface signal levels standardized by the Electronic 
Industries Association (EI A) RS-232C Standard. The following 
figure shows these levels. 



Driver 

+ 15 Vdc 



+5 Vdc 
+5 Vdc 



-5 Vdc 
-5 Vdc 



-15 Vdc 



EIA RS232C/CCITT V24-V28 Signal Levels 



Active/Data = 



Invalid Level 



inactive/ Data = 1 



Receiver 



+25 Vdc 



+3 Vdc 
+3 Vdc 

-3 Vdc 
-3 Vdc 



-25 Vdc 



EIA RS232C/CCITT V24-V28 Signal Levels 



Active/Data = 



Invalid Level 



Inactive/Data = 1 



Interface Voltage Levels 



BSC Adapter 9 



Pins 11, 18, and 25 on the interface connector are not 
standardized by the EI A. These lines are designated as 'select 
standby,' 'test,' and 'test indicate.' 'Select standby' is used to 
support the switched network backup facility of a modem that 
provides this option. 'Test' and 'test indicate' support a modem 
wrap function on modems designated for business-machine, 
controUed-modem wraps. 



10 BSC Adapter 



Specifications 



25-Pin D-Shell 
Connector 



25 




14 







Signal Name — Description 
No Connection 


Pin 
1 


















Transmitted Data 


2 










Received Data 


3 










Request to Send 


4 










Clear to Send 


5 










Data Set Ready 


6 










Signal Ground 


7 










Received Line Signal Detector 


8 










No Connection 


9 










No Connection 


10 




Binary 


External 




Select Standby* 


11 




Synchror 


Device 




No Connection 


12 




Commun 






No Connection 


13 




Adapter 






No Connection 


14 










Transmitter Signal Element Timing 


15 










No Connection 


16 










Receiver Signal Element Timing 


17 










Test (IBM Modems Only)* 


18 










No Connection 


19 










Data Terminal Ready 


20 










No Connection 


21 










Ring Indicator 


22 










Data Signal Rate Selector 


23 










No Connection 


24 










Test Indicate (IBM Modems Only)* 


25 








r""" 











*Not standardized by EIA (Electronic Industries Association). 
Connector Specifications 



BSC Adapter 11 



12 BSC Adapter 



Logic Diagrams 





I/O BUS 




B 


A 


+ *0 -. 


1 


31 


GND 


31 




+*1 -\ 


1 


30 


OSC 


30 




+»2 




PR 


+ 5MLTS- 


20 




+ A3 


J8j 


28 


+ A4 


27 


27 


+ A5 J 


20 


28 


+ *8 




25 


-IRQ3 -J 


25 




+«7 




24 


+IBQ4 - 


24 




+A8 


73 


23 


+A9 


22 

21 
20 
19 
18 
17 
18 
15 


22 
21 
20 
19 
18 
17 
18 
15 
14 


-lOR H 


14 


13 


-low - 


13 
12 


12 


+ AEH - 


~^ 


11 
10 


GND 






+ 00 


— 


9 


+12 VOLTS^ 






+ 01 


~ 


8 


+ 02 




7 


-12 KOLTS- 






+ 03 -\ 


— 


6 


+ 04 


— 


5 


+ 05 


— 


4 


+ 06 ^ 




3 


+ 5mTS-< 




2 






+BESET ^ 






GNO 








13 

25 
12 

24 


TEST INO 


SELECT STAY 


23 
22 
21 


BATE SELECT 


BIN6 IND 


CABRIEB OETECT 


20 


OATA TERM ROY 




19 


DATA SEL ROY 


18 




CLEAR TO SEND 


17 


RECEIVE CLOCK 




16 


BECEIVE OATA 


15 


TBANSMIT CLOCK 


TBANSMIT OATA 


14 





11 11 



-B01/B31 
-807 



-i-I- 



Binary Synchronous Communications Adapter (Sheet 1 of 2) 



BSC Adapter 13 




Binary Synchronous Communications Adapter (Sheet 2 of 2) 



14 BSC Adapter 




BSC Adapter 15 



16 BSC Adapter 



Personal Computer 
Hardware Reference 
Library 



IBM Synchronous Data 
Link Control (SDLC) 
Communications 
Adapter 



6361497 



Contents 



Description 1 

8273 SDLC Protocol Controller 2 

8255A-5 Programmable Peripheral Interface 2 

8253-5 Programmable Interval Timer 4 

Programming Considerations 5 

Initializing the Adapter (Typical Sequence) 5 

8253-5 Programmable Interval Timer 5 

Address and Interrupt Information 6 

Interface 7 

Specifications 9 

Logic Diagrams 11 



ui 



IV 



Description 



The IBM Synchronous Data Link Control (SDLC) 
Communications Adapter provides communications support to 
the system in a half -duplex synchronous mode. The adapter 
receives address, data, and control signals from the system board 
through the internal bus. Electronic Industries Association (EI A) 
drivers and receivers connect to an RS232-C standard 25 -pin, 
D-shell, male connector. 

The adapter is programmed by communications software to 
operate in a half-duplex mode. Maximum transmission rate is 
9600 bits per second, as generated by the attached modem or 
other data communications equipment. 

The SDLC adapter uses an Intel 8273 SDLC Protocol Controller 
and an Intel 8255A-5 Programmable Peripheral Interface (PPI) 
for an expanded external modem interface. An Intel 8253 
Programmable Interval Timer (PIT) generates timing and 
interrupt signals. Internal test-loop capability is provided for 
diagnostic purposes. 

The following figure is a block diagram of the IBM SDLC 
Communications Adapter. 



o 



System 
Bus 



Data 

Bus 

Buffer 



c=? 



Data 



c 



i I? 







Control 



Address 



Address 
Decode 
Logic 



r-'T T«-» * — ► 



8255A-5 
Programmable 
% Peripheral 



Interface 



n 



W^ 8253-5 
*~-N. Timer 






8273 
SDLC 
Protocol 
Controller 



EIA 

Drivers 

Receivers 



DOE 



Modem 
Status 
Change 
Logic 



SDLC Communications Adapter Blocl< Diagram 



SDLC Communications Adapter 1 



8273 SDLC Protocol Controller 

The 8273 SDLC Protocol Controller has three operations — 
transmission, reception, and port read — with each operation 
consisting of three phases: 

Command: Commands and/or requirements for the operation 
are issued by the system unit's microprocessor. 

Execution: Executes the command, manages the data link, and 
may transfer data to or from memory using direct memory access 
(DMA), and thus freeing the system unit's microprocessor except 
for minimal interruptions. 

Result: Shows the effect of the command by returning the 
interrupt results. 

Support of these phases is through the internal registers and 
control blocks of the controller. 



8255A-5 Programmable Peripheral Interface 

The 8255A-5 PPI has three 8-bit ports— A, B, and C. 
Descriptions of each bit of these ports follow. 



8255A-5 Port A Assignments* 



Hex Address 380 



Bit 



7 6 5 



I : 


I : 


I 1 




— ► 

— ► 




► 



= Ring Indicator is on from Interface 

0= Data Carrier Detect is on from Interface 

Oscillating = Transmit Clock Active 

= Clear to Send is on from Interface 
Oscillating = Receive Clock Active 

1 = Modem Status Changed 
1 = Timer 2 Output Active 

1 = Timer 1 Output Active 



•^Port A is defined as an input port 



2 SDLC Communications Adapter 



8255A-5 Port B Assignments* 



Hex Address 381 



Bit 



7 6 5 



]■ : 


5 : 


I 




— ► 







= Turn On Data Signal Rate Select at 

Modem Interface 
= Turn On Select Standby at Modem 

Interface 

= Turn On Test 

1 = Reset Modem Status Changed Logic 
1 = Reset 8273 

1 = Gate Timer 2 
1 = Gate Timer 1 
1 = Enable Level 4 Interrupt 



*Port B is defined as an output port 



8255A-5 Port C Assignments* 



Hex Address 382 



Bit 



7 6 5 4 3 2 10 



u 



1 = Gate Internal Clock (Output Bit) 
1 = Gate External Clock (Output Bit) 
1 = Electronic Wrap (Output Bit) 



-^►0 = Gate Interrupts 3 and 4 (Output Bit) 
-^►Oscillating = Receive Data (Input Bit) 
-►Oscillating = Timer Output (Input Bit) 
— ►O = Test Indicate Active (Input Bit) 
-►Not Used 



*Port C is defined for internal control and gating functions. It has three input 
and four output bits. The four output bits are defined during initialization, but 
only three are used. 



SDLC Communications Adapter 3 



8253-5 Programmable Interval Timer 

The 8253-5 PIT is driven by a microprocessor clock signal that is 
divided by 2. The PIT's three counters provide the following 
output: 

Counter Programmed to generate a square-wave signal that is 
used as an input to timer 2. Also connected to port 
C, bit 5 of the PIT. 

Counter 1 Connected to PPI port A, bit 7, and interrupt-level 4. 

Counter 2 Connected to PPI port A, bit 6, and interrupt-level 4. 



4 SDLC Communications Adapter 



Programming Considerations 



Initializing the Adapter (Typical Sequence) 

Before the 8273 SDLC Protocol Controller is started, the support 
devices on the adapter must be set to the correct modes of 
operation. 

Setup of the 8255A-5 Programmable Peripheral Interface is 
accomplished by selecting the mode set address for the PPI and 
by writing the appropriate control word to hex 98 to set ports A, 
B, and C to the modes described previously in this section. 

Next, a bit pattern sent to port C disallows interrupts, sets wrap 
mode on, and gates the external clock pins (address is hex 382, 
data is hex OD). The adapter is now isolated from the 
communications interface. 

The controller reset line is brought high through bit 4 of port B, 
held, then dropped. This action resets the internal registers of the 
controller. 



8253-5 Programmable Interval Timer 

The PIT'S counters 1 and 2 terminal-count values are set to values 
that will provide the desired time delay before a level-4 interrupt 
is generated. These interrupts may be used to indicate to the 
communication programs that a predetermined amount of time 
has elapsed without a result interrupt (interrupt-level 3). The 
terminal-count values for these counters are set for any time delay 
the programmer requires. Counter also is set to mode 3 
(generates square-wave signal used to drive counter 2 input). 

The counter modes are set up by selecting the address for the 
PIT'S counter-mode register and by writing the control word for 
each individual counter to the device separately. 



SDLC Communications Adapter 5 



When the support devices are set to the correct modes and the 
8273 SDLC Protocol Controller is reset, it is ready to be set up 
for the operating mode that defines the communications 
environment in which it will be used. 



Address and Interrupt Information 

The following tables provide address and interrupt information 
for the SDLC adapter. 



Hex Code 


Device 


Register Name 


Function 


380 


8255 


Port A Data 


Interrial/External Sensing 


381 


8255 


Port B Data 


External Modem Interface 


382 


8255 


Port C Data 


Internal Control 


383 


8255 


Mode Set 


8255 Mode Initialization 


384 


8253 


Counter LSB 


Square Wave Generator 


384 


8253 


Counter MSB 


Square Wave Generator 


385 


8253 


Counter 1 LSB 


Inactivity Time-Outs 


385 


8253 


Counter 1 MSB 


Inactivity Time-Outs 


386 


8253 


Counter 2 LSB 


Inactivity Time-Outs 


386 


8253 


Counter 2 MSB 


Inactivity Time-Outs 


387 


8253 


Mode Register 


8253 Mode Set 


388 


8273 


Comnnand/Status 


Out = Command In = Status 


389 


8273 


Parameter/Result 


Out = Parameter In = Status 


38A 


8273 


Transmit INT Status 


DMA/INT 


38B 


8273 


Receive INT Status 


DMA/INT 


38C 


8273 


Data 


DPC (Direct Program Control) 



SDLC Communications Adapter Device Addresses 



Interrupt Level 3 Transmit/Receive Interrupt 



Interrupt Level 4 



Timer 1 Interrupt 
Timer 2 Interrupt 
Clear to Send Changed 
Data Set Ready Changed 



DMA Level 1 is used for Transmit and Receive 



Interrupt Information 



6 SDLC Communications Adapter 



Interface 



The SDLC Communications Adapter conforms to interface signal 
levels standardized by the Electronic Industries Association 
(EIA) RS232-C Standard. These levels are shown in the 
following figure. 



Drivers 
+ 15Vdc 



+ 5Vdc 



■5Vdc 



• 15Vdc 



Active Level: Data = 



Invalid Level 



Inactive Level: Data = 1 



Receivers 
+ 25Vdc 



+ 3Vdc 



-3Vdc 



■25Vdc 



Additional lines used but not standardized by the EIA are pins 1 1 , 
18, and 25. These lines are designated as ^select standby,' 'test,' 
and 'test indicate,' respectively. 'Select standby' supports the 
switched network backup facility of a modem that has this option. 
'Test' and 'test indicate' support a modem-wrap function for 
modems that are designed for business-machine controlled 
modem- wraps. Two jumpers on the adapter (PI and P2) connect 
'test' and 'test indicate' to the interface. 



SDLC Communications Adapter 7 



8 SDLC Communications Adapter 



Specifications 



External 
Device 




Signal Name — Description 
No Connection 



Transmitted Data 



Received Data 



Request to Send 



Clear to Send 



Data Set Ready 



Signal Ground 



Received Line Signal Detector 



No Connection 



No Connection 



Select Standby^ 



No Connection 



No Connection 



No Connection 



Transmitter Signal Element Timing 



No Connection 



Receiver Signal Element Timing 



Test (IBM Modems Only)^ 



No Connection 



Data Terminal Ready 



No Connection 



Ring Indicator 



Data Signal Rate Selector 



No Connection 



Test Indicate (IBM Modems Only)^ 



25-Pin D-Shell 
Connector 



25 



O 
O 



10 



11 



12 



13 



14 



15 



16 



17 



18 



19 



20 



21 



22 



23 



24 



25 



14 



Pin 
1 



Synchronous 
Data Link 
Control 

Communications 
Adapter 



*Not standardized by El A (Electronic Industries Association). 

Connector Specifications 

SDLC Communications Adapter 9 



10 SDLC Communications Adapter 



Logic Diagrams 



The following pages contain the logic diagrams for the IBM 
Synchronous Data Link Control (SDLC) Adapter. 



SDLC Communications Adapter 1 1 



ij 




/.oo;D7. iim v/ //// // / ////// /////Z lZZi 



r 



w^m^M^^/// ///,///, 



\ Q zz //> ym\ 



y^ yf- 



SDLC Communications Adapter (Sheet 1 of 2) 



12 SDLC Communications Adapter 




SDLC Communications Adapter 13 



C/5 

D 

n 

n 

© 

s 
s 



P5 








I/O BUS 




B 


A 


+ A0 





31 


GNO — 


31 




+ A1 — 




-30 


OSC 


30 




+ A2 




-29 


+ 5V01TS — . 


29 




+ A3 


28 


28 


+ A4 


27 


-27 


+ A5 — 


26 


-26 


+ A6 — 




-2b 


-IRQ3 —i 


25 




+ A7 — 




-24 


+ IRg4 -^ 


?4 




+ A8 — 


23 


-23 










22 


21 




21 


20 




20 


19 




19 


18 


+ DRgi — 


18 


17 


- 0ACK1 — 


17 
15 


16 
15 
14 


-lOR — 


14 


13 


-low — 


13 
12 


12 


+ AEH — 


11 




GNO — 


in 




+ D0 — 






+ 12V0LTS — 


9 




+ D1 — 


8 




+ 02 — 






-12 VOITS — 
+ 03 — 


7 




+ 04 — 


6 
5 




+ 05 — 


4 




+ 06 — 






+ 5 VOLTS — 


3 




+ 07 — 






+ RESET — 


2 




GNO 


1 


' 



DECOUPLING CAPACITORS 



-CARRIER DETECT 

- DATA TERM ROY 

- SIGNAL GNO 



- DATA SEL ROY 
-TEST 

- CLEAR TO SEND 

- RECEIVE CLOCK 

- REQUEST TO SEND 

- RECEIVE DATA 



MODEM RECEIVE CLOCK 
MODEM TRANSMIT CLOCK 
TRANSMIT DATA 
REQUEST TO SEND 
DATA TERMINAL READY 
DATA SET READY 
CLEAR TO SEND 
RECEIVE DATA 
CARRIER DETECT 




liC2»** lie 

T.047MF T 



SDLC Communications Adapter (Sheet 2 of 2) 



Personal Computer 
Hardware Reference 
Library 



IBM Cluster Adapter 



6361495 



Contents 



Description 1 

8031 Microcomputer 5 

Cluster Adapter I/O Register Definitions 12 

Programming Considerations 18 

Interface 83 

System Processor I/O Interface 83 

Cluster Adapter Switch Settings 84 

System Processor Memory Interface 90 

System Processor Interrupt Interface 90 

8255 Programmable Peripheral Interface (PPI) ... 91 

Cluster Bus Interface 94 

Specifications 96 

Logic Diagrams 97 

Index Index^l 



ui 



IV 



Description 



The Cluster Adapter is a 10.16 cm (4 inch) high by 25.4 cm (10 
inch) wide communication adapter used for linking up to 64 IBM 
Personal Computers (PCs). The transmission rate is 375,000 bits 
per second (bps). A multi-drop bus architecture passively links 
(cluster operation is unaffected if the power to any station is off) 
the PCs to a coaxial cable. The coaxial cable bus can be a 
maximum length of 1 kilometer (3280 feet) and requires a 
7 5 -ohm (S2) terminating resistor at both ends to minimize signal 
reflection. The coaxial cable drop can be a maximum length of 5 
meters (16.4 feet) and a minimum length of 1 meter (3.3 feet). 

The following is an example of a cluster: 



















ibn 


















75^ 


Resistor 


PC 




PC 




PC 


Resistor 








CLUST 


ER 


EX/5 


^MPLE 









The PCs share the bus through a distributed-access protocol 
called carrier sense multiple access with coUision avoidance 
(CSMA/CA). With this protocol, each PC (station) that wants 
to transmit, calculates its own access-window wait time after no 
signal is sensed on the bus. The wait time differs for each station 
and changes with each transmission to prevent collisions (two 
stations transmitting at the same time). If cluster traffic is light 
(no signal is on the coaxial cable for approximately 2.8 
milUseconds), a station that wants to transmit establishes cluster 
synchronization by transmitting all I's (111 ... 1) for 150 



Cluster Adapter 1 



microseconds (/xs), thereby forcing a carrier sense transition 
(On-to-Off). The station can then calculate its access-window 
wait time. 

Because the PCs are passively connected and operate under a 
distributed-access protocol, the operation of the cluster is 
unaffected if the power to any single station is off. 

The Cluster Adapter sends and receives frames consisting of 
link-control and information fields to and from other Cluster 
Adapters in the cluster. 

The Cluster Adapter consists of the following components: 

8031 8 -bit Microcomputer 

8031 Accessible ROM 

8031 Accessible RAM 

System Processor (8088) Interface 

Adapter Status Register 

8088 Accessible ROM 

8255 Programmable Peripheral Interface (PPI) 

Cychc Redundancy Checking (CRC) Hardware 

Cluster Interface 



2 Cluster Adapter 



The following is a block diagram of the Cluster Adapter: 



Cluster Coaxial Cable 



-Oh 



Cluster 

Serial 

Interface 



CRC 
H/W 



Data 

8K R0M/4K RAM 

Address 



Latch 



Data Buffer 

8255 

PB PA PC 



Addr 
Switches 



PO P2 P3 

8031 

PI 



Status 
Register 



Processor 
Interface 



< 

System Processor Bus 

Cluster Adapter Block Diagram 



8088 ROM 
8K 



Cluster Adapter 3 



DANGER 
TO HELP PROTECT FROM LIGHTNING AND 
OTHER SOURCES OF ELECTRICAL SHOCK, IBM 
REQUIRES THAT THE COAXIAL CABLE 
SHIELDING BE GROUNDED, AND NEITHER THE 
FRAME NOR COVERS OF THE IBM PERSONAL 
COMPUTER CAN BE USED AS THE GROUNDING 
POINT. 



To ensure proper operation of the cluster, the shielding of the 
coaxial cable cannot be grounded at more than one point. 

If compliance to electrical codes require multiple ground 
points, then triaxial cable (double shielded) must be used. In 
using the triaxial cable, only the outer shielding can be 
grounded and under no circumstances should the outer shield 
be connected to the inner shield. 

This installation should be performed by a Ucensed electrician. 



4 Cluster Adapter 



8031 Microcomputer 

The 8031 Microcomputer is the controlling processor for the 
Cluster Adapter. The 8031 has an 8K x 8-bit ROM, and a 4K x 
8-bit static RAM. 

The 8031 consists of the following: 

• A processor 

• A dynamic 128 x 8-bit read/write data memory 

• 32 I/O lines 

• 2 16-bit timer/event counters 

• A five-source, two-priority-level, nested interrupt structure 

• A serial I/O port for multiprocessor communications 

• I/O expansion or a full duplex Universal 
Synchronous/Asynchronous Receiver/Transmitter (USART) 

• An on-chip oscillator and clock circuits. 

The 8031 also provides addressing for up to 64K bytes of 
program memory and 64K bytes of data memory. 

The 8031 is operated at 12 Megahertz (MHz), yielding a 
single-cycle time of 1 /xs. 

Program and data address spaces on the adapter are combined 
into a 64K-byte address space by ORing -Program Store Enable 
(-PSEN) and -Read (-RD). The memory address space includes 
not only the 8K x 8-bit ROM and 4K x 8-bit static RAM, but also 
the 8255 port and control registers and the 2653 registers 
necessary for CRC calculation. 



Cluster Adapter 5 



8031 Ports 

The 8031 on the Cluster Adapter provides external memory 
addresses through ports and 2. 

• Port is an 8-bit, open-drain, bidirectional, I/O port used as 
the multiplexed low-order address and data bus. 

• Port 2 is a bidirectional I/O port and provides the high-order 
address byte for the external memory. 

Port 1 of the 8031 is an 8-bit, bidirectional, I/O port used on the 
adapter for status conditions. 

Port 3 is an 8-bit, bidirectional, I/O port used as a serial port and 
as a source for external memory and serial-transmission control 
lines. 



6 Cluster Adapter 



The following is a summary of the 8031 port signals: 



Bits 


Porto 


Port 2 


Ports 


Port 1 


External Memory 
Address 


Transmission 
and Control 
Lines 


Status 


Low Order 
Byte and 
Data Bus 


High Order 
Address 
Byte Only 


7 


A7/D7 


A15 


-RD 


Direction to 8031 


6 


A6/D6 


A14 


-WR 


Error 


5 


A5/D5 


A13 


-CRC INT 


Communication 
Port Busy 


4 


A4/D4 


A12 


-RTS 


RX Virtual I/O 
Frame Available 


3 


A3/D3 


All 


+lnternal Loop 


RX Frame in (FIFO) 


2 


A2/D2 


A10 


-Carrier Sense 


Data Available for 
8088 (0 = Active) 


1 


A1/D1 


A9 


+TXD 


Command or Data 
Available for 8031 





AG/ DO 


A8 


+RXD 


Command in 
Progress 



Summary of 8031 Port Signals 



Cluster Adapter 7 



Serial Transmission and Control Lines 



The serial transmission lines are: 



+Receive Data (+RXD) 
+Transmit Data (h-TXD) 



The +RXD line provides the 
serial port's receiver data input. 

The +TXD Une provides the serial 
port's transmitter data output. 



The serial transmission control lines are: 



-Request to Send (-RTS) 



+ Internal Loop 



-Carrier Sense 



The -RTS signal enables the 
adapter's transmitter to send data 
on the cluster cable bus. 

The + Internal Loop line is used in 
the diagnostic mode. When high, 
it activates the internal loopback 
feature so the Cluster Adapter can 
receive the data it is transmitting 
without interference or being 
attached to the bus. 

-Carrier Sense is an input signal to 
port 3 that indicates the current 
state of the cluster; it is low (0) 
when the cluster is busy. 



8 Cluster Adapter 



The memory control lines are: 
-Write (-WR) 

-Read (-RD) 

The interrupt line is: 

-CRC Interrupt (-CRC INT) 



The -WR line latches the data 
byte from port into the external 
data memory. 

The -RD Hne enables external 
data memory to port 0. 



The -CRC INT line is used to 
indicate a successful or 
unsuccessful comparison in CRC 
values. The signal source is -INT 
from the 2653 Polynomial 
Checker Generator. 



8K X 8-Bit ROM 

The 8K X 8-bit ROM contains the 8031 code necessary for 
hardware initialization and the data link control program 
(DLCP). The DLCP is the lowest level of software for the 
Cluster Adapter. The DLCP resides in the 8K by 8-bit ROM on 
the Cluster Adapter, which is accessible by the 8031 
Microcomputer. 



4K X 8-Bit Static RAM 

The 4K X 8-bit static RAM is available to the 8031 for read/write 
storage necessary to implement the DLCP. The available space is 
used to buffer frames and to store control and cluster 
information. The 4K x 8-bit static RAM is implemented using 
two 2K X 8-bit static RAM modules. 



Cluster Adapter 9 



The following is the 8031 memory map: 



Start Address (Hex) 


Function 


0000 


DLCPROM 


2000 


RAM 


3000 


8255 Port A 


3001 


8255 Port B 


3002 


8255 Port C 


3003 


8255 Control 


3004 


2653 Character Register 


3005 


2653 Status Register 


3006 


2653 Mode Register 


3007 


2653 CRC Upper/Lower Registers 



8031 Memory Map 



8088 Accessible ROM 



The 8088 (System Processor) accessible ROM is an 8K x 8-bit 
ROM and contains the 8088 code necessary to perform the 
remote initial program load (IPL) and power-on diagnostic 
functions. 



2653 Polynomial Generator Checker 

The 2653 Polynomial Generator Checker is used by the 8031 
Microcomputer to compute the CycHc Redundancy Check (CRC) 
value for transmitted or received data blocks for error checking. 



10 Cluster Adapter 



The 2653 is programmed by the 8031 in the automatic mode to 
generate the American National Standards Institute (ANSI) 
CRC-16 values. Two 8-bit characters are read from the 2653 
character register into the Block Check Character (BCC) 
generation unit to calculate the 16-bit check character. 

Programming is achieved as follows: 

• The Clear CRC command, hex 02, is issued to the 2653 
command register at address hex 3005. 

• The Automatic Accumulation Mode command, hex 49, is 
issued to the 2653 mode register at address hex 3006. 

• The Start Accumulation command, hex 01, is issued to the 
2653 command register at address hex 3005. 

• Characters to be accumulated are written to the character 
register at address hex 3004. 

The accumulated CRC value may be read by the 8031 from 
address hex 3007 (the 2653 CRC upper and lower registers) in 
two read operations. The 2653 alternately provides the upper and 
lower values. 

The 2653 is activated upon proper decoding of addresses in the 
range of hex 3004 through hex 3007 and the occurrence of -Read 
Strobe (-RS) or -Write (-WR). This allows the input to the 
-Read/Write (-R/W) pin of the 2653 to become stable prior to 
the fall of -Clear Entry 1 (-CE1), as required. 



Cluster Adapter 1 1 



Cluster Adapter I/O Register Definitions 

The following defines the Cluster Adapter I/O registers: 



Adapter 


I/O Address 
(Hex) 


Device 


Adapter 1 


0790 


Adapter Status Register 


0791 


Adapter Command/Data (Output) 


Adapter Result/Data (Input) 


0792 


Adapter Interrupt Register 


0793 


Adapter Reset Control 


Adapter 2 


0B90 


Adapter Status Register 


0B91 


Adapter Command/Data (Output) 


Adapter Result/Data (Input) 


0B92 


Adapter Interrupt Register 


0B93 


Adapter Reset Control 


Adapter 3 


1390 


Adapter Status Register 


1391 


Adapter Command/Data (Output) 


Adapter Result/Data (Input) 


1392 


Adapter Interrupt Register 


1393 


Adapter Reset Control 


Adapter 4 


2390 


Adapter Status Register 


2391 


Adapter Command/Data (Output) 


Adapter Result/Data (Input) 


2392 


Adapter Interrupt Register 


2393 


Adapter Reset Control 



Cluster Adapter I/O Registers 



12 Cluster Adapter 



Adapter Status Register 

The adapter status is provided to the system data bus by a 
74LS373 transparent latch. 

The following are the bit assignments: 



Bit 


Definition (1 = Active Unless Noted) 


7 


Direction (1 = data expected from 8088 to 8031 ) 


6 


Error 


5 


Communication Port Busy 


4 


RX Virtual I/O Frame Available 


3 


RX Frame in First in First Out (FIFO) 


2 


Data Available for 8088 (0 = active) 


1 


Command/Data Available for 8031 





Command in Progress 



Status Register Bit Definitions 



The outputs of the transparent latch, though not enabled on the 
bus, continuously follow the inputs provided by the 8031 and 
8255. Upon decoding of the read-status I/O address, the 
latch-enable input to the transparent latch goes low, latching the 
inputs of the current state and enabling the data onto the bus. 

The status bits are latched during the active read time to preserve 
the integrity of the data. When the outputs are disabled and the 
latch-enable input to the latch goes high at the end of the read 
cycle, the outputs of the transparent latch again monitor the 
inputs in real time. 



Cluster Adapter 13 



Definition of Bits at Port 0791 

(for Adapter 1) 

(Command or Parameters for 8031 ) 


Bit 


Definition 


7 


Command or Data Bit 7 


6 


Command or Data Bit 6 


5 


Command or Data Bit 5 


4 


Command or Data Bit 4 


3 


Command or Data Bit 3 


2 


Command or Data Bit 2 


1 


Command or Data Bit 1 





Command or Data Bit 



Cluster Adapter Command/Data Register (Output) 



Definition of Bits at Port 0791 

(for Adapter 1) 
(Result or Data from 8031 ) 


Bit 


Definition 


7 


Result or Data Bit 7 


6 


Result or Data Bit 6 


5 


Result or Data Bit 5 


4 


Result or Data Bit 4 


3 


Result or Data Bit 3 


2 


Result or Data Bit 2 


1 


Result or Data Bit 1 





Result or Data Bit 



Cluster Adapter Result/Data Register (Input) 



14 Cluster Adapter 



Definition of Bits at Port 0792 (for Adapter 1 ) 


Bit 


Definitions 


7-2 


Not used. 


1 


Received Frame(s) Available. One or more information frames have 
been received and may be read using either the BIOS Receive 
Frame or Receive Virtual I/O Frame command (1 = active). 





Cluster BIOS Command Complete. The Cluster BIOS command 
intiated with the Initiate Transmit bit set is complete. The result 
must be obtained by issuing the same Cluster BIOS command with 
the Finish Transmit bit set (1 = active). 



Cluster Interrupt Status Bits 



Note: Both bits 1 and are set to indicate interrupt due to 
Cluster Status command complete. 



Definition of Bits at Port 0793 (for Adapter 1 ) 


Bit 


Definitions 


7-1 


Not used. 





Reset Cluster Adapter. The adapter microprocessor as well as all 
other logic on the adapter will be held in a reset condition until 
there is an output with this Reset Adapter bit set to zero (1 = active). 



Note: Any output to the reset register will also disable the adapter from 
generating interrupts. 

Cluster Adapter Reset Register Bit Definitions 



Cluster Adapter 15 



Cluster Adapter Interrupts 

The Cluster Adapter may be set (one jumper selectable) to allow 
interrupts on either interrupt-level 3 or interrupt-level 7. An 
adapter error detected by diagnostic tests is reported if the 
interrupt jumper is missing. The received frames must be 
available or the Transmit operation complete (if initiated by a 
Transmit command with the Initiate Transmit bit set). 

Up to four Cluster Adapters can be installed at a station. Each 
adapter can be enabled/disabled and all are similar in operation. 
If enabled, the adapter generates interrupts on levels 3 or 7 
provided one of the following conditions is met: 

• A received frame is available. 

• The Transmit Frame command is complete. 

• The Cluster Status command is complete. 

The following description is for adapter 1 : 

1 . Interrupts are enabled by executing an output instruction to 
the adapter's interrupt enable register. 

2. Interrupts are disabled by writing the hex 00 instruction to the 
adapter's reset register. Also, additional interrupts are 
disabled by generating the interrupt request. The adapter 
must be re-enabled after each interrupt if additional interrupts 
are desired. 



16 Cluster Adapter 



3. To avoid resetting the adapter, data bit must be set to a 
when an output is sent to the adapter's reset register. 

No interrupt handler is provided for the cluster, and must be 
provided by the user who requires interrupt capability. 

The interrupt condition is provided in the adapter's interrupt 
register, as described in the Cluster Adapter Interrupt Status 
Bits table. 



Cluster Adapter 17 



Programming Considerations 



The data link control program (DLCP) is the lowest level of 
software for the Cluster Adapter. The DLCP resides in the 8K 
by 8-bit ROM, which is accessible by the 8031 Microcomputer. 

The Cluster Adapter basic input/output system (BIOS) code 
resides in an 8K-byte 8088 accessible ROM on the Cluster 
Adapter at address hex DOOOO. 

Note: The Cluster Adapter decodes a 32K-byte range starting 
at hex DOOOO. High-level cluster BIOS commands are 
processed by the cluster BIOS into the appropriate low-level 
. commands and parameters. The low-level commands and 
parameters are then passed to the 8031 Microcomputer, which 
performs the requested command. After the command is 
complete, the 803 1 Microcomputer transfers the results back 
to the DLCP BIOS routine, which fills in the requester's link 
control block (LCB) with the results and then return through 
an interrupt return (IRET) to the requester that issued the 
INT hex 5A. 

The cluster BIOS level interface allows the higher layer 
communication program to transmit to and receive data from the 
specified destination through the bus. The basic unit of 
information transmitted using DLCP is a frame. A frame consists 
of a control field and an optional data field. 



18 Cluster Adapter 



The following functions are implemented in the DLCP to 
interface with the higher layer communication program and to 
ensure rehable data transfer between stations on the bus: 

• Higher layer communication program BIOS interface to the 
communication software 

• Frame assembly, reception and transmission 

• CRC generation and checking 

• Carrier sense multiple access with collision avoidance 
(CSMA/CA) 

• Error detection and recovery 

• Cluster status monitoring 

• Remote IPL 



Cluster Adapter 19 



Higher Layer Communicatioii Program BIOS 
Interface 

When the Power switch is set to On, the hex 5A software 
interrupt vector is set to the address of the Cluster Adapter BIOS 
by the adapter's self-test diagnostic code. 

Notes: 

1 . The DLCP must be initialized before it can process most of its 
commands. 

2. Interrupt hex 5A is reserved for the Cluster Adapter BIOS and 
should not be changed. 

The higher layer communication program must access the Cluster 
Adapter BIOS through an interrupt hex 5A instruction. The 
program must set the Extra Segment (ES) Register output to the 
segment and the Base Index (BX) Register output to the offset of 
the Link Control Block (LCB) before invoking the cluster DLCP 
BIOS. All parameters, the return code, and the cluster status are 
passed through the LCB. 



20 Cluster Adapter 



The format of the LCB is shown below: 



Link Control Block (LCB) 


Number of Bytes 


Destination Station Physical Address 


1 


Source Station Physical Address 


1 


Command 


1 


Buffer 1 Length 


2 


Buffer 1 Address 


2 (Offset) 


2 (Segment) 


Buffer 2 Length 


2 


Buffer 2 Address 


2 (Offset) 


2 (Segment) 


Return Code 


1 


Cluster Status 


1 


Select Adapter 


1 



Structure of Link Control Block (LCB) 



Notes: 



1 . The internal variables and buffers of the DLCP are in the 
RAM resident on the adapter and are not directly accessible 
from the higher layer communication program. 

2. Select Adapter is used to select the adapter for which the 
command is intended (0 for adapter 1, 1 for adapter 2, 2 for 
adapter 3, and 3 for adapter 4). 

3. For the length and address fields, the word values are ordered 
least-significant byte first. 



Cluster Adapter 21 



The contents of buffer 1 and buffer 2 together form the 
information field of the frame. For example, buffer 1 can be used 
to store header bytes while buffer 2 can be used to store the 
actual data to be transferred. 

The return code indicates the success or failure of the function 
requested, and the error code if the function fails. The LCB 
status indicates the current status of the cluster. This field is vaUd 
as a result of the DLCP Status command. The LCB status field is 
also used by some commands to store an extended return code. 



Frame Transmission 

Transmit or Transmit Virtual Information frames are sent by the 
DLCP to complete the corresponding DLCP BIOS commands. The 
DLCP on its own initiative transmits various frames. The 
following response frames are issued in response to a received 
frame: 

Ack Reception OK with no problems 

Frame Reject All receive buffers full 

Not Connected Not connected to sending station 

Bad Error Frame out of sequence (rejected) 

DupUcate Address Duplicate station address exists on the 

cluster 



22 Cluster Adapter 



The following control frame is transmitted by the DLCP when the 
Power switch is set to On or at initialization: 

Initializing Broadcast to all stations to indicate that the 

source station is in the process of initializing and 
all connections to that station should be set to 
the disconnected state. Also, if any station has 
the same station address, it sends a 
dupHcate-address response back to the 
initializing station. 

In addition, the DLCP determines if it is necessary to send a 
connect frame to estabhsh connection with the destination 
station. If this station's Cluster Status table indicates that it is not 
connected to the destination station, the DLCP transmits a 
connect frame to estabhsh connection and then transmits the 
information frame. If a not-connected control frame is received 
in response to the transmission of a frame, the DLCP transmits a 
connect frame to establish connection, then transmits the 
information frame. 



Cluster Adapter 23 



Frame Format 

The basic unit of information transmitted is a frame. The 
On-to-Off transition of the 'carrier sense' signal identifies the 
beginning of a frame, and the Off-to-On transition identifies the 
end. A frame consists of fixed control fields and an optional 
variable length information field. The following shows the format 
of a frame: 



Field 


Number of Bytes 


Note 


Destination Address 




Control 
Field 


Source Address 




Transmit Window Token 




Control 




Sequence 




Byte Count 


2 


Control CRC 


2 


Information 


1 to 578 


Information 
Field 


Data CRC 


2 



Frame Format 

Note: The minimum and maximum total number of bytes 
transmitted for a frame is 9 and 587, respectively. The 
transmission time for a frame ranges from approximately 1 
millisecond (ms) for a minimum length frame up to 
approximately 16.5 ms for the maximum length frame. 
However, additional time may be required to gain access to 
the cluster before a frame can be sent. 



24 Cluster Adapter 



Control Field Format 

The control field consists of the following: 

Destination Address - The destination address can be any 
number from hex 00 through hex 3F; that is, 64 station addresses 
are supported. Address hex FF is reserved as the broadcast 
address that all stations respond to. Addresses hex FE through 
hex FO are reserved for use as multicast addresses. 

Source Address - The source address is used to tell the DLCP 
the senders station address. The DLCP uses the source address 
as an index into a Cluster Status Table, which is used to maintain 
the status of connected stations and sequence numbers for each 
possible sender. Station addresses hex 00 through hex 3F are the 
only supported source addresses. 

Transmit Window Token - This value is updated for every 
transmission and is used in an algorithm to determine how long 
each station must wait after Carrier Sense Off before 
transmitting. 

Control Byte - The control byte is used to identify the function 
of a frame. There are two basic types of frames used in the 
cluster, information frames and control frames. Information 
frames are used to transfer information from one station to 
another, and control frames are used to assure reliable transfer of 
information across the cluster bus. 



Cluster Adapter 25 



The following types of frames are used by the DLCP: 

Acknowledge (hex 10) Confirm receipt of a frame. 

Initializing (hex 21) Indicates that the source station is 

re-initiaUzing. Existing connections to this station 
should be cleared. 

Virtual Disk (hex 82) Identifies that this frame contains a data 
block and was transmitted as a result of the source 
station issuing a Transmit Virtual Frame DLCP 
command. One buffer is reserved for this frame. 

Information (hex 83) Signifies the frame contains a data block and 
was transmitted as a result of the source station 
issuing a Transmit Frame DLCP command. There is a 
first-in-first-out (FIFO) buffer set aside for this 
frame. 

Connect (hex 04) EstabHshes the virtual point-to-point 
connection between a pair of stations. 

Broadcast (hex 45) Signifies that the frame is a broadcast or 
multicast frame. 

Not Connected (hex 16) Indicates that the receiving station is not 
connected to the sending station. 

Frame Reject (hex 17) Sent by the receiving station when it has 
received an information frame or a virtual disk frame 
and the DLCP does not have buffer space available to 
store the frame. 

Bad Error (hex 18) Sent by the receiving station to indicate that a 
frame is out of sequence. 

Duplicate Address (hex 19) Sent by the receiving station in 

response to an initializing control frame to indicate 
that more than one station has the same address. 



26 Cluster Adapter 



Are You There? (hex lA) Sent to each station to poll for status in 
the cluster. Each station that is on sends a response 
to this query. An Acknowledge response frame is sent 
by stations that are initialized. A Frame Reject 
response is sent by stations that are not initialized. 

Note: The most-significant four bits of the frame-control byte 
have the following meaning: 

Sequenced Information Bit 7 

Broadcast Information Bit 6 

Broadcast Control Bit 5 

Response Bit 4 

Frame Sequence Byte - If one of the acknowledge frames did 
not reach the transmitting station, the frame sequence byte is used 
to make sure that no dupHcate information frames are received. 
The least-significant four bits in the Cluster Status Entry are used 
for maintaining a sequence number for transmitted and received 
frames. The first two bits are used for the sequence number for 
received frames. The two least-significant bits are used for the 
sequence number for transmitted frames. The sequence numbers 
are incremented each time a transmitting station sends an 
information frame and each time the receiving station accepts an 
information frame. If a mismatch occurs between the two 
stations, the sender marks the destination station in the 
disconnected state and sends a connect frame to try to reconnect 
with the destination station. If the connection attempt is 
successful, the frame is transmitted again. 



Cluster Adapter 27 



Byte Count - The byte count is the number of information bytes 
to be transmitted. If the frame is a control frame, the byte count 
is zero. There are two bytes allocated for the byte count. 

Control CRC - A 16-bit cyclic redundancy check (CRC) is 
calculated and appended to the end of the control block. A 
hardware CRC generator is used. The receiving station compares 
the control CRC received with the CRC calculated from the 
received data and makes sure they are the same. If they are not 
the same, the receiving station ignores the rest of the frame. 

Data CRC - A 16-bit CRC is calculated and appended to the 
end of the data block. The receiving station compares the data 
CRC received with the CRC calculated from the received 
information bytes and makes sure they are the same. If they are 
not the same, the receiving station ignores the received frame. 



Information Field 

This field is for an information frame only. The information field 
is absent in the control frames. The maximum number of 
information bytes that can be transmitted in a frame is 578. 



28 Cluster Adapter 



Cluster Access Protocol 

Collision avoidance is used with the Cluster Adapter. To avoid 
collisions, each station waits a different amount of time after 
'carrier sense' goes inactive before transmitting. 

Stations get access to the cluster by timing from the end of the 
current transmission (-Carrier Sense On-to-Off transition) until 
its transmit time is reached, and then it may transmit. See also 
"Collision Avoidance (Medium or High Activity)" on page 30. 

Each station maintains two flags to determine that it is permitted 
to transmit. 

1 . Synchronized Transmit Period. 

2. Transmit Window. 

The Synchronized Transmit Period is set and the Transmit 
Window is cleared when the Carrier Sense Interrupt routine is 
entered. Also, timer is reloaded with the count corresponding 
to this station's calculated Transmit Access Window. Timer 
counts while 'carrier sense' is off and overflows when this 
station's Transmit Access Window is reached. Timer O's overflow 
causes an interrupt that sets the Transmit Window flag and then 
reloads timer with the count corresponding to the end of the 
synchronized transmit period. When timer interrupts again on 
overflow, the Synchronized Transmit Period flag is reset to 
indicate that the synchronized transmit period is finished. 



Cluster Adapter 29 



Collision Avoidance (Medium or High Activity) 

The following shows the timing during medium or high activity in 
the cluster: 



Carrier On -i 

Sense Off I 



I — TR — I M 2 I •'• |63|64 
T2 1 



T64 



Synchronized On 

Transmit Off 

Period 



Transmit On 

Window Off 

Slot 2 



L 



30 Cluster Adapter 



Collision Avoidance (Medium or High Activity) 

TR = Time allocated for a receiver to start transmitting a 

response. 
Tl = Time delay for 1st Transmit Access Window. 
T2 = Time delay for 2nd Transmit Access Window. 



T64 = Time delay for 64th Transmit Access Window. 
SN = Station N's address with the bits in reverse order. 
Token = Transmit Window Token which is decremented by 2 
for each transmitted frame. 



Delay time for Station N = TR + ((Token + SN) mod 128) x 

transmit window/2. 

Notes: 

1. TR is approximately 200 /xs. 

2. Transmit Access Window is approximately 40 fis. 

A station must see its Transmit Window flag change from Off to 
On before it is permitted to transmit. The case where it does not 
see the change is covered in the next section. 

Collision Avoidance (Light Activity) 

If cluster activity is light (1480 /xs average access time since the 
previous transmission on the cluster) enough that the 
Synchronized Transmit Period (STP) flag is reset, then 
synchronization needs to be re-estabHshed to avoid colHsions. 



Cluster Adapter 31 



The method used to re-estabhsh synchronization is to transmit all 
I's in the cluster for approximately 150 /xs and then to time the 
carrier sense On-to-Off condition to this station's transmit slot 
time. (See also '^Collision Avoidance (Light Activity)" on page 
33). 



Transmit 
Data 



i...jn ...... 



All I's Transmit Frame 



m-MW 



Carrier On 

Sense Off 



J~L 



I — TR 1 1 I 2 I ••• |64| 

^T2 1 

-T64 1 



Synchronized 


On 


Transmit 


Off 


Period 






On 


Transmit 


Off 


Window 




Slot 2 





"L 



32 Cluster Adapter 



Collision Avoidance (Light Activity) 

TR = Time allocated for a receiver to start transmitting a 

response. 
Tl = Time delay for 1st Transmit Access Window^. 
T2 = Time delay for 2nd Transmit Access Window. 



T64 = Time delay for 64th Transmit Access Window. 

Note: Average cluster access time is 1480 /xs if the cluster is 
Hghtly loaded. 

A station that is initializing waits the time of two complete 
synchronization periods before sending its broadcast initializing 
frame to allow it to become synchronized with the cluster. If no 
frames are received in that time, it uses the procedure above to 
estabHsh a synchronized transmit period. 



Frame Reception 

The leading edge of the 'carrier sense' signal is used to interrupt 
the 8031 Microcomputer. The 8031 interrupt service routine 
updates its Transmit Window Token to the value transmitted with 
the frame, and also sets the timer counter to the calculated 
Transmit Access Window based on the new token value. If the 
frame is not addressed to this station, the DLCP ignores the rest 
of the frame and leaves the interrupt routine. 

If the frame is addressed to the station, the DLCP checks the 
Cluster Adapter status to see if it can accept the frame. If this 
station is not connected to the source station then a 
not-connected control frame is transmitted to the source station. 
If the frame is out of sequence, an bad error control frame is 
transmitted to the source station. 

If the DLCP can accept the frame, a check is made that a receive 
buffer is available. If a buffer cannot be obtained, a frame- reject 
control frame is sent back to the transmitting station. This 
indicates that the frame cannot be accepted at this time and 
another attempt should be made. If the frame is received 



Cluster Adapter 33 



correctly, DLCP transmits an Acknowledge frame to the 
transmitting station and return the control to the interrupted 803 1 
program. 



Error Detection and Recovery 

The DLCP can detect various cluster errors and tries to recover 
from them. If it is not able to recover after a specified number of 
retries, it notifies the calling program with the returned error 
code. The Ust of errors that can be detected is in the figure 
below: 



Type of Error 


Action Taken 


Retry Count 


(Seconds) 


Cluster Busy Timeout 


Report Error 


N/A 


1.0 


Cluster Access Timeout 


Report Error 


N/A 


13.0 


No Response 


Retransmit Frame 


8 


0.20 


Frame Reject 


Retransmit Frame 
after Delay 


1 
2 
3 
4 
5 
6 
7 


0.24 
0.09 
0.16 
0.25 
0.36 
0.49 
0.64 


Not Connected or Bad 
Error 


Transmit Connect 
Control Frame and 
If Successful 
Retransmit Frame 


N/A 


N/A 


Command Timeout 


Reset Adapter and 
Report Error 


N/A 


120.0 



Detectable Errors and Recovery 



34 Cluster Adapter 



After correctly receiving a control frame or an information frame, 
the receiving station sends a response frame. If all receive buffers 
are in use, a Frame Reject response frame is transmitted. If the 
frame is out of sequence, a Bad Error response frame is 
transmitted. 

If the transmitting station did not get a confirmation of receipt 
after a certain time period, it assumes that the receiving station 
never got the frame and it transmits the same frame again. If the 
transmitting station still does not get a reply after eight retries, it 
assumes that the receiving station is not available and resets the 
Connected bit in the corresponding Cluster Adapter status entry. 



Cluster Status Table 

The DLCP keeps track of the status and sequence numbers for 
connection with stations through 63 in the Cluster Table in the 
Cluster Adapter's RAM space. Offset in the Cluster Table 
corresponds to the status for connection to station 0, offset 1 for 
station 1, and so on. The offset corresponding to a station's own 
address is used to store a duplicate-station address indicator. 



Cluster Adapter 35 



The bits for each Cluster Status Table byte are designated in the 
following chart: 



Cluster Status Entry (1 Byte) 1 


C 


7 


1 = Connected 


RBI 


6 


Response ID 


RBO 


5 


Response ID 


P 


4 


1 == Response Pending 


RS1 


3 


Received Frame Sequence 


RSO 


2 


Received Frame Sequence 


TS1 


1 


Transmitted Frame Sequence 


TSO 





Transmitted Frame Sequence 



Cluster Status Table Entry 



Bit? 



Connected (C) is set to 1 when your station has 
sent a connect frame and an acknowledge frame 
has been received, or when a connect frame has 
been received and an acknowledge has been sent. 
Connected is reset when a not-connected, bad 
error, or initializing control frame is received. 



Bit 6, 5 



Response ID 



The following table defines the meaning of these 
two bits: 



Bite 

RB1 


Bit 5 
RBO 


Type of Response 





1 



1 



Acknowledge 
Frame Reject 
Not Connected 



Response ID In Cluster Table Status Entry 



36 Cluster Adapter 



Bit 4 - Pending (P) is set to 1 by the transmitting station to 
indicate that it is waiting for an acknowledge frame 
from the destination station , and is reset by the 
interrupt handler when a response is received or upon 
a time-out. 

Bit 3, 2 - Received Frames Sequence Number is incremented 

every time a new data-sequenced information frame is 
successfully received. This sequence number and the 
transmitted frame sequence number are reset to 
when a connection is established between two 
stations. 

Bit 1, - Transmitted Frames Sequence Number is incremented 
every time a sequenced information frame is 
successfully transmitted; that is, an acknowledge is 
received from the destination station. 



Remote IPL 

A vector is estabhshed at bootstrap vector INT hex 19 to the 
Remote System Reset Program Loader for the cluster, which is 
located in adapter 1 's ROM. The original contents of the 
bootstrap vector are stored at vector INT hex 5B. The disk server 
station address is stored at the least-significant byte of vector INT 
hex El. The number of the adapter from which to IPL is stored 
at the word corresponding to the segment at vector INT hex El. 



Cluster Adapter 37 



The following actions are performed by the Remote System Reset 
Program Loader: 

1 . The Remote System Reset Program Loader (in the Cluster 
Adapter's 8088 accessible ROM) uses a portion of the top IK 
bytes of memory for variable and buffer space. 

2. The bootstrap vector is restored with its original vector (which 
was temporarily saved at INT hex 5B). The INT hex 5B 
vector is set to point to the adapter's diagnostic routines. 

3. The variables of DLCP are initiaHzed by executing a DLCP 
BIOS Cluster Initialization command (hex 00) with 
parameters provided by a table of constants in the adapter's 
8088 ROM. 

4. The user timer-interrupt vector at vector hex IC is saved at 
interrupt vector hex E2 and replaced with the address of a 
routine to update a timer count variable used for time-outs by 
the Remote System Reset Program Loader. It is restored 
before this routine is left. 

5. A broadcast frame requesting IPL is sent using the DLCP 
BIOS command's Transmit Broadcast Frame (hex 08) to all 
stations in the cluster. The format of the data portion of the 
frame is: 

Command = hex 91 (Request for IPL) 
Session ID = hex 0000 (2 bytes) 



38 Cluster Adapter 



6. An acknowledge information frame is expected with the 
following data: 



Command = 


hex 92 


(Response to IPL request) 


Session ID = 


hex xxxx 


(2 bytes) 


Status = 


hex 00 


(non-zero is irrecoverable error) 



xxxx = any hexidecimal number 

The server station's address is saved at the least-significant 
byte of vector INT hex El. 

Up to eight retries are made unless a response from the disk 
server station is received. Approximately 4 seconds are 
allowed between retries. After the eight retries have been 
used, the user timer-interrupt vector is restored and then 
control is passed to the bootstrap routine. 

Note: If a Keep- Alive command is received from the disk 
server station, an additional 30 seconds is allowed. 

7. Next, the Remote IPL program requests a data block 
containing program code from the disk server station. The 
request has the following form: 



Command = 
Session ID = 
Status = 


hex 93 
hex xxxx 
hex 00 


Request IPL data block 

(2 bytes) 

(Non-zero is a irrecoverable 

error) 



xxxx = any hexidecimal number 

The request is sent using the DLCP BIOS command's 
Transmit Frame (hex 03). Retries are made for up to 20 
seconds if the return code indicates a Frame Reject or a No 
Response error. 



Cluster Adapter 39 



The disk server sends a response containing the next data 
block. The response has the following form: 



Command = 


hex 94 


Response with IPL data 
block 


Session ID = 


hex xxxx 


(2 bytes) 


Status = 


hex 00 


(Non-zero is a irrecoverable 
error) 


Sector # = 


hex xxxx 


Relative sector number 


Data Block = 


[0-512 bytes] 


Data Block containing 
program code. 



xxxx = any hexidecimal number 

The DLCP BIOS Receive Frame command (hex 02) is issued 
to read the response frame containing the block of program 
code. Approximately 20 seconds are allowed to receive a 
valid response from the disk server station. If a Keep-Alive 
command is received from the disk server station, an 
additional 30 seconds are allowed. There is no limit to the 
number of Keep- Alive commands that are accepted. On 
time-out, the user timer-interrupt vector is restored and 
control is passed to the Bootstrap Loader by INT hex 19. 

The received sector number must start at zero and increment 
for each block of program code received. If the received 
sector number is incorrect or if the status is non-zero, then the 
user timer-interrupt vector is restored and control is passed to 
the bootstrap vector by INT hex 19. The sector number is 
two bytes long with the least-significant byte first in the 
received data. 



40 Cluster Adapter 



The received program code is inserted in memory starting at 
location hex 07C0:0000 and continuing upward. The end of 
the program code is determined when a frame is received that 
does not contain 512 bytes of program code. 

9. The above two steps are repeated until the end of the program 
code is received. The user timer-interrupt vector is restored 
and control passes to the loaded program by a jump to hex 
07C0:0000. 

Notes: 

1. The Remote IPL function is performed, even if local drives are 
attached, if the Remote IPL switch on Cluster Adapter 1 is 
On. Remote IPL is supported only for Cluster Adapter I. 
The Remote IPL function can be stopped by pressing Control 
Break, and normal loading from local diskette drives occurs. 

2. For every block of data received, an arrow rotates in a 
clockwise direction on the screen. 

3. After power on or system reset, the cursor is moved to the 
right three columns for about 1 second. Special ROM 
diagnostic tests for the adapter can be executed by 
immediately pressing "Ctrl D" on the keyboard. Also, a 
request to load a general diagnostic program over the cluster 
can be selected by pressing "Ctrl L" at which time a blinking 
L is displayed. The adapter sends out a broadcast frame 
requesting a diagnostic program load. (The first data byte of 
the request frame is set to hex 90.) 



Cluster Adapter 41 



DLCP BIOS Commands 

The DLCP BIOS commands are issued by the higher layer 
communication program to send and receive information through 
the cluster. The following are the DLCP BIOS commands: 



Command Number (Hex) 


Command Name 


00 


Cluster Initialization 


01 


Receive Virtual Frame 


02 


Receive Frame 


03 


Transmit Frame 


04 


Reserved 


05 


Display Cluster Status 


06 


Cluster Status 


07 


Status 


08 


Broadcast Frame 


09 


Transmit Virtual Frame 


OA 


Stop DLCP 


OB 


Read Station Address 


oc 


Set Multicast Address 


OD 


Check Command In Progress 


OE 


Read IPL Switch 


OF 


Start DLCP 


10 


Dump Statistics 


11 


Diagnostic Function 1 


12 


Diagnostic Function 2 


13 


Diagnostic Function 3 


14 


Diagnostic Function 4 


15 


Diagnostic Function 5 


16 


Diagnostic Function 6 


17 


Diagnostic Function 7 



DLCP BIOS Commands 



42 Cluster Adapter 



DLCP Return Codes 

The following table indicates the Return Codes that are defined 
for the cluster DLCP: 



DLCP Return Codes 


Return Code 


Meaning 


Hex 00 


Successful Completion 


Hex 30 


Initialization failed 


Hex 31 


Cluster busy timeout (carrier sense 
active for 2 seconds) 


Hex 32 


Duplicate station address on cluster 


Hex 33 


No response from destination 


Hex 34 


Frame rejected at destination 


Hex 35 


Reserved 


Hex 36 


Cluster access timeout (could not gain 
access to cluster within a 1 3 second timeout) 


Hex 37 


Information field too long (more than 
578 bytes) 


Hex 38 


Information field empty 


Hex 39 


DLCP command in progress 


Hex3A 


Initialization required 


Hex3B 


Received frame not available 


Hex 30 


Error detected with 8031 (due to command 
timeout or other processor interface error 


Hex 3D 


Extended return code in cluster status field 


Hex3E 


Invalid initialization parameters (too many 
or too large buffers specified) 


Hex3F 


Previous DLCP BIOS command initiated 
with Initiate Transmit bit set is not complete 



Cluster DLCP Return Codes 



Note: A return code of hex 00 indicates successful completion 
of the DLCP BIOS command. Most of the other return codes 
indicate error conditions. 



Cluster Adapter 43 



Cluster Initialization (DLCP) = Hex 00 

Function: This command initializes the DLCP and also transmits 
an initializing frame to inform others in the cluster. If 
another station in the cluster has the same address as 
this station, it sends a response frame indicating 
dupHcate station address, and the return code is hex 
32. The Initialization Control Block (ICB) must be 
built by the calling program with the initialization 
values indicated by the following: 



Return Code 



Definition 



hex 00 
hex 30 
hex 32 
hex 39 
hex3C 
hex3E 



Successful completion 

InitiaUzation failed 

DupUcate station address in the cluster 

Command in progress 

Error with 8031 

InvaHd initialization parameters 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= 00 (Hex) 


Unchanged 


Buffer 1 Length 


= OF (Hex) 


Unchanged 


Buffer 1 Address 


Address of Initialization 
Control Block (ICB) 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Don't Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Cluster Initialization (DLCP) = Hex GO 



44 Cluster Adapter 



Initialization Control Block (ICB) 

The calling program must set the buffer 1 address field in the 
LCB to the address of an initialization control block (ICB). The 
figure below shows the composition and bytes that make up the 
ICB: 



Byte 


Byte Definition 


Value 





(Bits) 7 6 5 4 3 2 1 
(Value) NVB MM1 MM2 





1 


Number of Large Buffers 


4 


2 


Number of Small Buffers 


10 


3 


Large Buffer Size 


584^8 


4 


Small Buffer Size 


40 


5 


Maximum Number of Retries for No Response 


8 


6 


Maximum Number of Retries for Rejected Frame 


2 


7 


Transmit Access Window (TAW) 


40-2 


8 


Time Period Reserved for Response 


200- 


-20 


9 


Time from Frame Start to First Byte 


150- 


-2 


10 


Time Between Control Field and Data Field 


100- 


-2 


11 


Timeout Waiting for Response to be Received 


300- 


-6 


12 


Timeout Waiting for Next Byte to be Received 


300- 


-6 


13 


Timeout Waiting for Command to Complete 


7 


14 


Timeout Waiting to Access Cluster 


200 



Initialization Control Block (ICB) 



Cluster Adapter 45 



Byte - Bits 7, 6, 5, 4, and 3 are reserved and must be set to 0. 

Bit 2 - No Virtual Buffer (NVB), when set to zero, 
allocates a receive buffer for Virtual Frames. 

Bit 1 and - These bits are set to enable the first 
portion of all frames to be received (even if they are 
not addressed to this station). 

The following figure shows the Monitor Mode (MM) 
bit definitions: 



MM1 


MMO 


Monitor Mode Condition 








Normal Mode 





1 


Receives All Frames on Cluster 


1 





Invalid Setting 


1 


1 


Receives Only Frames from or to Multicast 
Address or This Station Address 



Monitor Mode Bit Definitions 

Note: In Monitor Mode, only the first portion of a frame (up 
to the size of the small buffer minus 7 bytes) is received. The 
first byte is set to the value of Transmit Window Token, and 
the second byte corresponds to the first data byte of the 
information field of the frame. 



46 Cluster Adapter 



Byte 1 - This byte indicates the number of large buffers 
allocated in the 8031 RAM for incoming frames. 

Byte 2 - This byte indicates the number of small buffers 
allocated in the 8031 RAM for incoming frames. 

Byte 3 - This byte indicates the large buffer size (each unit 

represents 8 bytes). Six bytes of the large buffer are 
reserved for control information. 

Byte 4 - This byte indicates the small buffer size (each unit 
represents 1 byte). Six bytes of the small buffer are 
reserved for control information. 

Byte 5 - This byte indicates the maximum number of times a 
frame is transmitted with no response from the 
destination station. 

Byte 7 - This byte is used to specify the Transmit Access 
Window (TAW) time period in jus. For a 40 /as 
TAW, set this byte to 20. After every transmitted 
frame, an Access Time Period is allocated, which is 
64 times the TAW time period. 

Byte 8 - The value of this byte times TAW divided by 2 

equals the amount of time (jits.) reserved after each 
frame for a response frame to be transmitted. 



Cluster Adapter 47 



Byte 9 - The value of this byte times 2 equals the delay in /xs 
after the start of a transmit frame before the first 
byte (destination) is transmitted. 

Byte 10 - The value of this byte times 2 equals the delay in /xs 
between the control field and data field of a frame. 

Byte 1 1 - The value of this byte times 6 equals the time 

allowed in /xs for a response frame to be received. 

Byte 12 - The value of this byte times 6 equals the time 
allowed in /xs for the next byte of a frame to be 
received. 

Byte 13 - The value of this byte times 16.7 equals the number 
of seconds allowed for any command in progress to 
finish before the 8031 indicates error hex 3C to the 
Cluster Adapter BIOS code. 

Byte 14 - The value of this byte times 67 milliseconds equals 
the amount of time allowed waiting to access the 
cluster before error hex 36 is returned. 



48 Cluster Adapter 



Receive Virtual Frame = Hex 01 

Function: This command is used to retrieve a data frame sent by 
the disk server (using Transmit Virtual Frame). 

Notes: 

1 . There is only one virtual frame buffer for this type of data 
frame. 

2. The destination, command, and cluster status fields in the 
LCB are modified. 



Return Code 


Destination 


hex 00 


Successful completion 


hex 32 


DupUcate station address in the cluster 


hex 37 


Information field too long 


hex 38 


No information field present 


hex 39 


Command in progress 


hex 3 A 


Initialization required 


hex3B 


No receive frame exists 


hex3C 


Error detected with 8031 



Cluster Adapter 49 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Destination 


Source 


Don't Care 


Source 


Command 


= 01 (Hex) 


Frame Control 


Buffer 1 Length 


Length of Calling 
Program's Buffer 1 


Length of Received Data if 
Less Than Buffer 1 Length 


Buffer 1 Address 


Points to Calling 
Program's Buffer 1 


Unchanged 


Buffer 2 Length 


Length of Calling 
Program's Buffer 2 


Length of Received Data 
Placed in This Buffer 


Buffer 2 Address 


Points to Calling 
Program's Buffer 2 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Frame Sequence 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Receive Virtual I/O Frame = Hex 01 



50 Cluster Adapter 



Receive Frame (from FIFO queue) = Hex 02 

Function: This command is used to retrieve a data frame sent 

from another station (using Transmit Frame) from the 
First-In-First-Out (FIFO) queue. 

The FIFO queue can contain four full size frames and 
10 small frames. 

Note: The field's destination, command, and cluster status in 
the LCB are modified. 

Note: If the adapter is in Monitor mode, the first byte 
returned is the Transmit Window Token. The second byte is 
the first data byte of the information field of the received 
frame. 



Return Code 


Definition 


hex 00 


Successful completion 


hex 32 


Duphcate station address in the cluster 


hex 37 


Information field too long 


hex 38 


No information field present 


hex 39 


Command in progress 


hex3A 


InitiaUzation required 


hex3B 


No receive frame exists 


hex3C 


Error detected with 8031 



Cluster Adapter 51 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Destination 


Source 


Don't Care 


Source 


Command 


= 02 (Hex) 


Frame Control 


Buffer 1 Length 


Length of Calling 
Program's Buffer 1 


Length of Received Data if 
Less Than Buffer 1 Length 


Buffer 1 Address 


Points to Calling 
Program's Buffer 1 


Unchanged 


Buffer 2 Length 


Length of Calling 
Program's Buffer 2 


Length of Received Data 
Placed in This Buffer 


Buffer 2 Address 


Points to Calling 
Program's Buffer 2 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Frame Sequence 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Receive Frame (from FIFO Queue) = Hex 02 



52 Cluster Adapter 



Transmit Frame = Hex 03 

Function: This command is used to transmit a data frame to 

another station where it can be retrieved by using the 
Receive Frame command. 

Note: See also ''Special Transmit Mode Command Bits" on 
page 8 1 

Return Code Definition 

hex 00 Successful completion 

hex 3 1 Cluster always busy 

hex 32 Duplicate station address in the cluster 

hex 33 No response from destination 

hex 34 Exceed allowed number of rejected frames 

hex 36 Cluster access time-out 

hex 37 Information field too long (frame is not 

sent) 
hex 38 No information field present (frame is not 

sent) 
hex 39 Command in progress 

hex 3 A Initialization required 

hex 3 C Error detected with 803 1 



Cluster Adapter 53 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Destination 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= 03 (Hex) 


Unchanged 


Buffer 1 Length 


Length of Calling 
Program's Buffer 1 


Unchanged 


Buffer 1 Address 


Points to Calling 
Program's Buffer 1 


Unchanged 


Buffer 2 Length 


Length of Calling 
Program's Buffer 2 


Unchanged 


Buffer 2 Address 


Points to Calling 
Program's Buffer 2 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Transmit Frame = Hex 03 



54 Cluster Adapter 



Display Cluster Status = Hex 05 

Function: This command is used to determine and then display 
the cluster status. The On/Off status of 64 stations is 
displayed. Stations that have the Power switch set to 
On are displayed in reverse video. Your station is 
displayed in reverse video and blinking. If another 
station in the cluster has the same address as your 
station, a long beep sounds. Only those stations that 
are initialized can be displayed. 

Note: The screen should be cleared before issuing this 
command. 

Note: Type of status (destination field): 

hex 00 = report stations that are On 

hex FF = report stations that are initialized 
Return Code Definition 

hex 00 Successful completion 

hex 3 1 Cluster always busy 

hex 36 Cluster access time-out 

hex 39 Command in progress 

hex 3C Error detected with 803 1 



Cluster Adapter 55 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Type of Status 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


-05 (Hex) 


Unchanged 


Buffer 1 Length 


Number of Stations 
to Display 


Unchanged 


Buffer 1 Address 


Don't Care 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Don't Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Extended Return Code on 
Error 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Display Cluster Status = Hex 05 



56 Cluster Adapter 



This page explains the cluster status that may appear on your 
screen. 

NN is any station address from to 63. 



Nl\l 



The station you are using is indicated on the screen 
in bhnking reverse video, and the box is marked by 
two asterisks. 



NN 

-X X- 



Stations that have their Power switches set to On 
are displayed in reverse video, and their boxes are 
marked by two Xs. 



N N 

-X -Jf- 



Another station has the same address as your 
station; a long beep sounds every 3 seconds, the 
box is displayed in blinking reverse video, and is 
marked by an X and an asterisk. 



N N 



A station address not in the cluster is indicated by a 
box displayed in normal video and not marked with 
Xs or asterisks. 



Cluster Adapter 57 



Cluster Status = Hex 06 

Function: This command determines the stations' On/Off 
status. The status bytes are stored in buffer 1 (as 
determined by the buffer 1 pointer in the LCB). The 
first byte's least-significant bit is the status of station 
0. Bit 1 represents station 1. The least-significant bit 
of the second byte is the status of station 8, and so on. 
The number of stations checked is a parameter of this 
command. Only those stations that are initialized are 
reported. 

Notes: 

1. Type of status (destination field): 

hex 00 = report stations that are On 
hex FF = report stations initiahzed 

2. See also "Special Transmit Mode Command Bits" on page 81 

3 . The size of the buffer required to store the cluster status bytes 
is (number of stations to check + 7)-^8. 

Return Code Definition 

hex 00 Successful completion 

hex 3 1 Cluster always busy 

hex 36 Cluster access time-out 

hex 39 Command in progress 

hex 3C Error detected with 803 1 



58 Cluster Adapter 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Type of Status 


Unchanged 


Source 


Don't Care 


Unchanged 


Connmand 


= 06 (Hex) 


Unchanged 


Buffer 1 Length 


Number of Stations 
to Check 


Unchanged 


Buffer 1 Address 


Points to Calling 
Program's Buffer 1 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Don't Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Extended Return Code 
on Error 


Select Adapter 


= for Adapter 1 
== 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Cluster Status = Hex 06 



Cluster Adapter 59 



status = Hex 07 



Function: This command is used to return the status of the 
connection with a particular station. 



Return Code 



Definition 



hex 00 
hex 39 
hex3C 



Successful completion 
Command in progress 
Error detected with 8031 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Stations for Which 
Status is Desired 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= 07 (Hex) 


Unchanged 


Buffer 1 Length 


Don't Care 


Unchanged 


Buffer 1 Address 


Don't Care 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Don't Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Cluster Status 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Status = Hex 07 



60 Cluster Adapter 



Transmit Broadcast Frame = Hex 08 

Function: This command is used to transmit a data frame to 

another station where it can be retrieved by using the 
Receive Frame command. No acknowledgment to the 
frame is sent by the receiving stations. 

Note: Transmit Frame and Transmit Virtual Frames are 
converted to Broadcast Frames if the destination station 
number is greater than 127. 

Note: See also ''Special Transmit Mode Command Bits" on 
page 81.. 



Return Code 


Definition 


hex 00 


Successful completion 


hex 31 


Cluster always busy 


hex 32 


Duplicate station address in cluster 


hex 36 


Cluster access time-out 


hex 37 


Information field too long (frame is not 




sent) 


hex 38 


No information field present (frame is not 




sent) 


hex 39 


Command in progress 


hex3A 


Initialization required 


hex3C 


Error detected with 8031 



Cluster Adapter 61 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Destination 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= 08 (Hex) 


Unchanged 


Buffer 1 Length 


Length of Calling 
Program's Buffer 1 


Unchanged 


Buffer 1 Address 


Points to Calling 
Program's Buffer 1 


Unchanged 


Buffer 2 Length 


Length of Calling 
Program's Buffer 2 


Unchanged 


Buffer 2 Address 


Points to Calling 
Program's Buffer 2 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Transmit Broadcast Frame = Hex 08 



62 Cluster Adapter 



Transmit Virtual Frame = Hex 09 

Function: This command is used to transmit a data frame 

containing sector information from the disk server 
station. The information can be retrieved only by 
using the Receive Virtual Frame command. 

Note: See "Special Transmit Mode Command Bits" on page 
81 



Return Code 


Definition 


hex 00 


Successful completion 


hex 31 


Cluster always busy 


hex 32 


Duplicate station address in cluster 


hex 33 


No response from destination 


hex 34 


Frame rejected at destination 


hex 36 


Cluster access time-out 


hex 37 


Information field too long (frame is not 




sent) 


hex 38 


No information field present (frame is not 




sent) 


hex 39 


Command in progress 


hex3A 


Initialization required 


hex3C 


Error detected with 8031 



Cluster Adapter 63 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Destination 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= 09 (Hex) 


Unchanged 


Buffer 1 Length 


Length of Calling 
Program's Buffer 1 


Unchanged 


Buffer 1 Address 


Points to Calling 
Program's Buffer 1 


Unchanged 


Buffer 2 Length 


Length of Calling 
Program's Buffer 2 


Unchanged 


Buffer 2 Address 


Points to Calling 
Program's Buffer 2 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Transmit Virtual Disk Frame = Hex 09 



64 Cluster Adapter 



stop DLCP = Hex OA 

Function: This command is used to temporarily inhibit the 

DLCP from receiving or transmitting frames. Issue a 
Start DLCP command to leave the stopped state. 



Return Code 



Definition 



hex 00 
hex 39 
hex3A 
hex3C 



Successful completion 
Command in progress 
InitiaUzation required 
Error detected with 8031 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= OA(Hex) 


Unchanged 


Buffer 1 Length 


Don't Care 


Unchanged 


Buffer 1 Address 


Don't Care 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Dont' Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Stop DLCP = Hex OA 



Cluster Adapter 65 



Read Station Address = Hex OB 

Function: This command is used to return the address and state 
of the remote IPL switch of this station. 



Return Code 



Definition 



hex 00 
hex 39 
hex3C 



Successful completion 
Command in progress 
Error detected with 8031 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


This station's address 


Command 


-OB (Hex) 


Unchanged 


Buffer 1 Length 


Don't Care 


Unchanged 


Buffer 1 Address 


Don't Care 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Don't Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


00 = NolPLFF = IPL 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Read Address = Hex OB 



66 Cluster Adapter 



Set Multicast Address = Hex OC 

Function: This command is used to set the desired multicast 
address. The multicast address is a variation of the 
broadcast address (hex FF). More than one station 
may be assigned the same multicast address. A 
default value of hex FF is set when a cluster 
Initialization command is issued to the DLCP. A 
frame sent, using the Transmit Broadcast Frame 
command (8), to the group multicast address is 
received by all stations that share the multicast 
address. 



Return Code 



Definition 



hex 00 
hex 39 
hex3C 



Successful completion 
Command in progress 
Error detected with 8031 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Desired Multicast 
Address 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= OC(Hex) 


Unchanged 


Buffer 1 Length 


Don't Care 


Unchanged 


Buffer 1 Address 


Don't Care 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Don't Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Set Multicast Address = Hex OC 



Cluster Adapter 67 



Check Inside DLCP Flag = Hex OD 

Function: This command is used to return an indication that a 
DLCP command is already in progress. This 
command is necessary only for programs that call 
DLCP from inside an interrupt routine. If a DLCP 
command is already in progress, the interrupt routine 
should return to the interrupted program to allow the 
current DLCP command to finish. 



Return Code 



Definition 



hex 00 
hex 39 
hex3C 



Command not in progress 
Command in progress 
Error detected with 8031 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= OD(Hex) 


Unchanged 


Buffer 1 Length 


Don't Care 


Unchanged 


Buffer 1 Address 


Don't Care 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Don't Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Check Inside DLCP Flag = Hex OD 



68 Cluster Adapter 



Read IPL Switch = Hex OE 



Function: This command is used to read the state of the Remote 
IPL switch on the requesting station. 



Return Code 



Definition 



hex 00 
hex 39 
hex3C 



Successful completion 
Command in progress 
Error detected with 8031 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


This station's address 


Command 


= OE(Hex) 


Unchanged 


Buffer 1 Length 


Don't Care 


Unchanged 


Buffer 1 Address 


Don't Care 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Don't Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


IPL Switch (00 = No IPL 
FF = IPL) 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Read IPL Switch = Hex OE 



Cluster Adapter 69 



start DLCP = Hex OF 

Function: This command is used to release the DLCP from the 
stopped state. It enables the DLCP to receive and 
transmit frames. 



Return Code 



Definition 



hex 00 
hex 39 
hex3A 
hex3C 



Successful completion 
Command in progress 
InitiaHzation required 
Error detected with 8031 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= OF (Hex) 


Unchanged 


Buffer 1 Length 


Don't Care 


Unchanged 


Buffer 1 Address 


Don't Care 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Don't Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
=^3 for Adapter 4 


Unchanged 



Start DLCP = Hex OF 



70 Cluster Adapter 



Dump Statistics = Hex 10 

Function: This command is used to transfer the current 

communication statistics block from the adapter. 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= 10 (Hex) 


Unchanged 


Buffer 1 Length 


1 2 bytes 


Unchanged 


Buffer 1 Address 


Points to Calling 
Program's Buffer 1 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Don't Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3for Adapter 4 


Unchanged 



Dump Statistics = Hex 10 



Cluster Adapter 71 



Communication Statistics Block (CSB) 



The Cluster Adapter returns information regarding previous 
activity in tlie CSB. 



Return Code 



Definition 



hex 00 
hex 39 
hex3C 



Successful completion 
Command in progress 
Error detected with 8031 



The figure below shows the composition and definition of the 
CSB bytes: 



Byte 


Definition 





Number of Times No Response Received (LSB) 


1 


Number of Times No Response Received (MSB) 


2 


Number of Times Frame Rejects Received 


3 


Number of Control Frames Correctly Received (LSB) 


4 


Number of Control Frames Correctly Received (MSB) 


5 


Number of Data Frames Correctly Received (LSB) 


6 


Number of Data Frames Correctly Received (MSB) 


7 


Number of Control Frames with CRC Error 


8 


Number of Data Frames with CRC Error 


9 


Number of Duplicate Frames Received 


10 


Number of Received Frames That Were Rejected 


11 


Number of Transmit Collisions 



Communication Statistic Block 



72 Cluster Adapter 



Diagnostic Function 1 = Hex 1 1 

Function: This command is used to run an internal diagnostic 
test. 

(Reserved for diagnostic use only.) 

Bit 1 Test adapter processor-to-processor interface 

Bit 2 Reserved 

Bit 3 Test driver and receiver logic (terminating plug required 

for diagnostic use) 
Bit 4 Test interrupt logic (set transmit interrupt status bit) 
Bit 5 Test interrupt logic (set receive interrupt status bit) 
Bit 6 Clear transmit and receive interrupt status bits (no 

interrupt) 
Bit 7 Set transmit and receive interrupt status bits (no 

interrupt) 

Return Code Definition 

hex 00 Successful completion 

hex 39 Command in progress 

hex 3C Error detected with 803 1 

hex 3D Error detected by 8031 diagnostic test 

(reason for error in Cluster Status field) 



Cluster Adapter 73 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Test Number ** 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= 1 1 (Hex) 


Unchanged 


Buffer 1 Length 


Don't Care 


Unchanged 


Buffer 1 Address 


Don't Care 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Don't Care 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Extended Return Code 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Diagnostic Function 1 = Hex 11 



Note: ** Test number (Destination field) 



74 Cluster Adapter 



Diagnostic Function 2 = Hex 12 

Function: This command is used to transfer data to the adapter's 
RAM from a buffer in system memory. The data in 
buffer 1 is transferred to the address specified by 
buffer 2 in the 8031 address space. 

(Reserved for diagnostic use only.) 
Return Code Definition 



hex 00 
hex 39 
hex3C 



Successful completion 
Command in progress 
Error detected with 803 1 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= 12 (Hex) 


Unchanged 


Buffer 1 Length 


Length of Calling 
Program's Buffer 1 


Unchanged 


Buffer 1 Address 


Points to Buffer 1 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Set Offset to Address 
in 8031 RAM Space 
to Place Data 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 




= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Diagnostic Function 2 = Hex 12 



Cluster Adapter 75 



Diagnostic Function 3 = Hex 13 

Function: This command is used to transfer data from the 

adapter's RAM to a buffer in system memory. The 
data is transferred starting at the address specified by 
the buffer 2 address (offset) in 8031 memory to 
buffer 1 in the main system's memory. 

(Reserved for diagnostic use only.) 
Return Code Definition 



hex 00 
hex 39 
hex 3C 



Successful completion 
Command in progress 
Error detected with 8031 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= 13 (Hex) 


Unchanged 


Buffer 1 Length 


Length of Calling 
Program's Buffer 1 


Unchanged 


Buffer 1 Address 


Points to Buffer 1 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Set Offset to Address 
in 8031 RAM Space 
from Which to get 
Data 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Diagnostic Function 3 = Hex 13 



76 Cluster Adapter 



Diagnostic Function 4 = Hex 14 



Function: This command is used to transfer data to the 803 Ts 
internal RAM from a buffer in system memory. The 
data in buffer 1 is transferred to the address specified 
by buffer 2 address in 8031 memory. 

(Reserved for diagnostic use only.) 

Note: Extreme care must be used to prevent destroying data 
in the 803 1's stack and registers in this internal chip RAM. 
Also, there are only 128 bytes of RAM. 



Return Code 



Definition 



hex 00 
hex 39 
hex3C 



Successful completion 
Command in progress 
Error detected with 8031 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= 14 (Hex) 


Unchanged 


Buffer 1 Length 


Length of Calling 
Program's Buffer 1 


Unchanged 


Buffer 1 Address 


Points to Buffer 1 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Set Offset to Address 
in 8031 on Chip 
Space to Place Data 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Diagnostic Function 4 = Hex 14 



Cluster Adapter 77 



Diagnostic Function 5 = Hex 15 

Function: This command is used to transfer data from the 

803 Ts internal RAM to a buffer in system memory. 
The data is transferred starting at the address 
specified by buffer 2 address (offset) in 803 1 memory 
to buffer 1 in the main system's memory. 

(Reserved for diagnostic use only.) 
Return Code Definition 



hex 00 
hex 39 
hex3C 



Successful completion 
Command in progress 
Error detected with 8031 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


Unchanged 


Command 


= 15 (Hex) 


Unchanged 


Buffer 1 Length 


Length of Calling 
Program's Buffer 1 


Unchanged 


Buffer 1 Address 


Points to Buffer 1 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Set Offset to Address 
in 8031 RAM from 
Which to Get Data 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Diagnostic Function 5 = Hex 15 



78 Cluster Adapter 



Diagnostic Function 6 = Hex 16 

Function: This command is used to execute an 803 1 program at 
the address specified by the buffer 2 address field. A 
"Call" is made to that address and it is expected that 
the called program sets the 8031 accumulator to a 
return code value before returning. This return code 
is placed in the Cluster Status field if non-zero. 

(Reserved for diagnostic use only.) 
Return Code Definition 



hex 00 
hex 39 
hex3C 
hex 3D 



Successful completion 

Command in progress 

Error detected with 803 1 

Extended return code in cluster status 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Don't Care 


Unchanged 


Source 


Don't Care 


Unchanged 


Comnnand 


- 16 (Hex) 


Unchanged 


Buffer 1 Length 


Don't Care 


Unchanged 


Buffer 1 Address 


Don't Care 


Unchanged 


Buffer 2 Length 


Don't Care 


Unchanged 


Buffer 2 Address 


Set Offset to Address 
in 8031 RAM Space 
where a Callable 
Program Exists 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Extended Return Code 


Select Adapter 


= for Adapter 1 
== 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Diagnostic Function 6 = Hex 16 



Cluster Adapter 79 



Diagnostic Function 7 = Hex 17 

Function: This command is used to transmit any type of frame 
to another station. For example, a control frame may 
be sent to another station. 

(Reserved for diagnostic use only.) 
Return Code Definition 



hex 00 
hex 31 
hex 32 
hex 33 
hex 34 
hex 36 
hex 37 
hex 39 
hex3A 
hex3C 



Successful completion 
Cluster always busy 
DupHcate station address in cluster 
No response from destination 
Exceeded allowed rejected frames 
Cluster access time-out 
Information field too long 
Command in progress 
Initialization required 
Error detected with 8031 



Link Control Block (LCB) 


Field 


Value at Entry 


Value at Exit 


Destination 


Destination 


Unchanged 


Source 


Frame Type 


Unchanged 


Command 


= 17 (Hex) 


Unchanged 


Buffer 1 Length 


Length of Calling 
Program's Buffer 1 


Unchanged 


Buffer 1 Address 


Points to Calling 
Program's Buffer 1 


Unchanged 


Buffer 2 Length 


Length of Calling 
Program's Buffer 2 


Unchanged 


Buffer 2 Address 


Points to Calling 
Program's Buffer 2 


Unchanged 


Return Code 


Don't Care 


Set to Return Code 


Cluster Status 


Don't Care 


Unchanged 


Select Adapter 


= for Adapter 1 
= 1 for Adapter 2 
= 2 for Adapter 3 
= 3 for Adapter 4 


Unchanged 



Diagnostic Function 7 = Hex 17 



80 Cluster Adapter 



Special Transmit Mode Command Bits 

The three most-significant bits in the command field of the LCB 
have the following meanings for transmit commands: 



Name 


Bit 


Meaning 


Initiate Transmit 


7 


Initiate transmit operation but return before 
complete with return code set to immediate 
result. 


Finish Transmit 


6 


Wait for previously started transmit operation 
to complete. Return with return code in LCB 
set to result of transmit operation. 


Return Status 


5 


If the transmit operation is complete, the 
return code is set to hex 00 (transmit operation 
complete result available). Otherwise the 
return code is set to hex 3F (transmit operation 
not complete). 



Special Transmit Command Bits 



Notes: 



1 . These special transmit command bits are valid only for the 
following DLCP BIOS commands: 



Transmit Frame 
Cluster Status 
Transmit Broadcast 
Transmit Virtual Frame 



(hex 03) 
(hex 06) 
(hex 08) 
(hex 09) 



2. A transmit operation started with the Initiate Transmit bit set 
to 1 must be finished by issuing the same transmit command, 
with a different LCB and the Finish Transmit bit set to 1. If 
the immediate return code was not zero, the transmit 
operation is already complete. 

3. If an interrupt handler is being used for receive frames, an 
interrupt is also generated when the transmit operation is 
complete for transmit operations initiated with the Initiate 
Transmit bit set. The Transmit Interrupt status bit is set to 1 
to indicate that the transmit operation is complete. This bit is 
bit of adapter port hex 0792 (for adapter 1). 



Cluster Adapter 81 



82 Cluster Adapter 



Interface 



System Processor I/O Interface 

Four Cluster Adapters can be installed at each station. The 
Cluster Adapter number is selected by switch positions 1 through 
4 of switch block 2. These positions correspond to I/O address 
bits 10, 11, 12, and 13. An adapter is selected when a select 
switch is On, and the adapter receives a high level (1) on the 
corresponding I/O address bit. 

Note: High level is 1 and low level is 0. 

If multiple Cluster Adapters are installed at a station, each 
adapter can have only one address select switch set to On. A 
station cannot have two Cluster Adapters with the same address. 

Notes: 

1 . When more than one address select switch is On, the Cluster 
Adapter decodes and responds to all I/O addresses selected. 

2. Cluster Adapter 1 is the only adapter that decodes and 
responds to all memory addresses; therefore, if more than one 
Cluster Adapter is set as number 1 (CI), undesirable results 
occur. 

3. If a Cluster Adapter does not have a select switch set to On, it 
does not respond. 



Cluster Adapter 83 



Cluster Adapter Switch Settings 

Cluster Adapter addresses and functions can be selected by two 
eight-switch dual in-line package (DIP) switch blocks. The 
following shows the switch assignments: 

Notes: 

1. Switch 8 of switch block 1 selects remote initial program load 
(IPL) when in the On position. 

2. Switch 7 of switch block 1 is reserved. It must be in the Off 
position. 



Switch 


Legend 


Function 


SW-8 


IPL 


Remote IPL 


SW-7 


N/A 


Reserved (Must be Off) 


SW-6 


A5 


Station Address Bit 5 


SW-5 


A4 


Station Address Bit 4 


SW-4 


A3 


Station Address Bit 3 


SW-3 


A2 


Station Address Bit 2 


SW-2 


A1 


Station Address Bit 1 


SW-1 


AO 


Station Address Bit 



Switch Block 1 Bit Assignments 



Switch 


Legend 


Function 


SW-8 


N/A 


Reserved 


SW-7 


RDY 


I/O Channel Ready 


SW-6 


N/A 


Reserved 


SW-5 


N/A 


Reserved 


SW-4 


C4 


Select Adapter 4 


SW-3 


C3 


Select Adapter 3 


SW-2 


C2 


Select Adapter 2 


SW-1 


CI 


Select Adapter 1 



Switch Block 2 Bit Assignments 



84 Cluster Adapter 



The following shows the station-address switch settings on switch 
block 1. 



Station 


Switch Block 1 Switch Settings 


SW1 


SW2 


SW3 


SW4 


SW5 


SW6 





Off 


Off 


Off 


Off 


Off 


Off 


1 


On 


Off 


Off 


Off 


Off 


Off 


2 


Off 


On 


Off 


Off 


Off 


Off 


3 


On 


On 


Off 


Off 


Off 


Off 


4 


Off 


Off 


On 


Off 


Off 


Off 


5 


On 


Off 


On 


Off 


Off 


Off 


6 


Off 


On 


On 


Off 


Off 


Off 


7 


On 


On 


On 


Off 


Off 


Off 


8 


Off 


Off 


Off 


On 


Off 


Off 


9 


On 


Off 


Off 


On 


Off 


Off 


10 


Off 


On 


Off 


On 


Off 


Off 


11 


On 


On 


Off 


On 


Off 


Off 


12 


Off 


Off 


On 


On 


Off 


Off 


13 


On 


Off 


On 


On 


Off 


Off 


14 


Off 


On 


On 


On 


Off 


Off 



Notes: 

1 . Bit switches 7 and 8 are not applicable to the station address. 

2. "On" represents the closed/on position. 

3. "Off" represents the open/off position. 

Station Address Switch Settings 



Cluster Adapter 85 



Station 


Switch Block 1 Switch Settings 


SW1 


SW2 


SW3 


SW4 


SW5 


SW6 


15 


On 


On 


On 


On 


Off 


Off 


16 


Off 


Off 


Off 


Off 


On 


Off 


17 


On 


Off 


Off 


Off 


On 


Off 


18 


Off 


On 


Off 


Off 


On 


Off 


19 


On 


On 


Off 


Off 


On 


Off 


20 


Off 


Off 


On 


Off 


On 


Off 


21 


On 


Off 


On 


Off 


On 


Off 


22 


Off 


On 


On 


Off 


On 


Off 


23 


On 


On 


On 


Off 


On 


Off 


24 


Off 


Off 


Off 


On 


On 


Off 


25 


On 


Off 


Off 


On 


On 


Off 


26 


Off 


On 


Off 


On 


On 


Off 


27 


On 


On 


Off 


On 


On 


Off 


28 


Off 


Off 


On 


On 


On 


Off 


29 


On 


Off 


On 


On 


On 


Off 


30 


Off 


On 


On 


On 


On 


Off 


31 


On 


On 


On 


On 


On 


Off 


32 


Off 


Off 


Off 


Off 


Off 


On 



Station Address Switch Settings 



86 Cluster Adapter 



Station 


Switch Blocl< 1 Switch Settings 


SW1 


SW2 


SW3 


SW4 


SW5 


SW6 


33 


On 


Off 


Off 


Off 


Off 


On 


34 


Off 


On 


Off 


Off 


Off 


On 


35 


On 


On 


Off 


Off 


Off 


On 


36 


Off 


Off 


On 


Off 


Off 


On 


37 


On 


Off 


On 


Off 


Off 


On 


38 


Off 


On 


On 


Off 


Off 


On 


39 


On 


On 


On 


Off 


Off 


On 


40 


Off 


Off 


Off 


On 


Off 


On 


41 


On 


Off 


Off 


On 


Off 


On 


42 


Off 


On 


Off 


On 


Off 


On 


43 


On 


On 


Off 


On 


Off 


On 


44 


Off 


Off 


On 


On 


Off 


On 


45 


On 


Off 


On 


On 


Off 


On 


46 


Off 


On 


On 


On 


Off 


On 


47 


On 


On 


On 


On 


Off 


On 


48 


Off 


Off 


Off 


Off 


On 


On 


49 


On 


Off 


Off 


Off 


On 


On 


50 


Off 


On 


Off 


Off 


On 


On 



Station Address Switch Settings 



Cluster Adapter 87 



Station 


Switch Block 1 Switch Settings 


SW1 


SW2 


SW3 


SW4 


SW5 


SW6 


51 


On 


On 


Off 


Off 


On 


On 


52 


Off 


Off 


On 


Off 


On 


On 


53 


On 


Off 


On 


Off 


On 


On 


54 


Off 


On 


On 


Off 


On 


On 


55 


On 


On 


On 


Off 


On 


On 


56 


Off 


Off 


Off 


On 


On 


On 


57 


On 


Off 


Off 


On 


On 


On 


58 


Off 


On 


Off 


On 


On 


On 


59 


On 


On 


Off 


On 


On 


On 


60 


Off 


Off 


On 


On 


On 


On 


61 


On 


Off 


On 


On 


On 


On 


62 


Off 


On 


On 


On 


On 


On 


63 


On 


On 


On 


On 


On 


On 



Station Address Switch Settings 



88 Cluster Adapter 



The following I/O addresses are assigned to the Cluster 
Adapters: 



Adapter 


I/O Address 
(Hex) 


Device 


Adapter 1 


0790 


Adapter Status Register 


0791 


Adapter Command/Data (Output) 


Adapter Result/Data (Input) 


0792 


Adapter Interrupt Register 


0793 


Adapter Reset Control 


Adapter 2 


0890 


Adapter Status Register 


0891 


Adapter Command/Data (Output) 


Adapter Result/Data (Input) 


0892 


Adapter Interrupt Register 


0893 


Adapter Reset Control 


Adapter 3 


1390 


Adapter Status Register 


1391 


Adapter Command/Data (Output) 


Adapter Result/Data (Input) 


1392 


Adapter Interrupt Register 


1393 


Adapter Reset Control 


Adapter 4 


2390 


Adapter Status Register 


2391 


Adapter Command/Data (Output) 


Adapter Result/Data (Input) 


2392 


Adapter Interrupt Register 


2393 


Adapter Reset Control 



Cluster Adapter I/O Summary 

The Adapter Reset command resets the 8031 and 8255 on a 
Cluster Adapter by writing a 1 to that adapter's Adapter 
Reset/Interrupt Disable port address. This sets a 74LS74 latch, 
which remains set until a is written to the same port. The latch 
must remain set for a minimum of 2 /xs, which is the minimum 
reset time of the 8031 operating at 12 MHz. 

The interrupts on a Cluster Adapter can be disabled by writing a 
to the Adapter Reset/Interrupt Disable port, when -lOW is 
active (0). 



Cluster Adapter 89 



The Cluster Adapter can drive the I/O Channel Ready line low in 
synchronization with the system clock when the processor reads 
from the adapter card. This enables a longer read cycle from the 
expansion slots. The option is selected by setting the I/O 
Channel Ready switch (switch 7 of switch block 2) to On. 



System Processor Memory Interface 

The memory addresses assigned to the Cluster Adapter are hex 
DOOOO through hex D7FFF. These addresses are fully decoded 
only on adapter 1, and are selected by setting the CI select switch 
(SW2-1) to On. Each station must have one Cluster Adapter 
selected as number 1 . 



System Processor Interrupt Interface 

The Cluster Adapter provides an interrupt interface to the system 
processor with Interrupt Request 3 (IR03) or Interrupt Request 7 
(IRQ7). The desired interrupt is selected using the interrupt 
select jumper on the Cluster Adapter. The selection of the 
interrupt is dependent on the programming requirements. 



90 Cluster Adapter 



The following is a sequence of the interrupt process for adapter 1 : 

1 . The system processor enables interrupts by writing to the 
adapter interrupt enable register at address hex 0792. 

2. Upon receipt of an interrupt condition, the 8031 sends a 
negative active (0) pulse of 10 /as on the port C bit (PCO) 
line of the 8255 which is connected to IRQ3 or IRQ7. The 
low-to-high transition of this line prevents this adapter and 
other Cluster Adapters in the system from generating further 
interrupt requests. The 8031 processor also sets either Port 
CI (PCI) or Port C2 (PC2) of the 8255 to indicate the 
source of the interrupt. PCI corresponds to a transmit 
interrupt, and PC2 corresponds to a receive interrupt. If both 
PCI and PC2 are set, the source of the interrupt is the 
completion of a Cluster Status command. 

3. The system processor reads I/O addresses hex 0792, 0B92, 
1392, and 2392 on each Cluster Adapter to determine the 
cause of the interrupt. After all pending requests are handled, 
the system processor re-enables interrupts on all desired 
adapters. 



8255 Programmable Peripheral Interface 
(PPI) 

The 8255 is used to provide an asynchronous interface between 
the system processor and the 8031 Microcomputer without the 
use of interrupts or direct memory access (DMA). 



Cluster Adapter 91 



Port A 

Port A is operated in mode 2 as a strobed, bidirectional, I/O bus. 
In this mode, all eight bits of Port A (PAO through PA7) are 
dedicated to data transfer between the microcomputer (8031) and 
the system processor (8088). 



PortB 

Port B is operated in mode 0. The low-order six bits (PBO 
through PBS) provide the station address, and the high-order bit 
(PB7) provides the Remote IPL (On/Off) status. Bit 7 (PB6 is 
reserved). The source of information for Port B is switch block 1. 
When a bit switch is On, the bit is active (low). The 
microprocessor code in the 8031 complements the Port B 
information to produce logical 1 active bits. 



PortC 

When port C is operated in mode 2, five lines are dedicated as 
handshaking signals. The following four handshaking signals are 
used by the Cluster Adapter: 

. -Output Buffer Full (-OBF) 

A low signal on the -OBF (PC7) line indicates that the 
microcomputer (8031) has written data to Port A. -OBF 
provides status to the adapter status register. 

• -Acknowledge (-ACK) 

A low signal on the -ACK (PC6) line enables the tri-state 
output buffer of Port A to send out data to the system 
processor (8088); otherwise the output is in a high 
impedance state. 



92 Cluster Adapter 



. Input Buffer Full (IBF) 

A high signal on the IBF (PCS) output indicates that data 
from the 8088 has been loaded into Port A. IBF provides 
input to the adapter status register and to the 8031. 

• -Strobe Input (-STB) 

A low signal on the -STB (PC4) loads data from the 8088 
into Port A. 

The following is a summary of the 8255 port signals: 



8255 Port Signals 


Bit 


Port A 
Mode 2 


Port B 
ModeO 


PortC 
Mode 2 


7 


Data Bit 7 


Remote IPL 


-DBF 


6 


Data Bit 6 


Reserved 


-ACK 


5 


Data Bit 5 


Station Address Bit 5 


+IBF 


4 


Data Bit 4 


Station Address Bit 4 


-STB 


3 


Data Bit 3 


Station Address Bit 3 


Reserved 


2 


Data Bit 2 


Station Address Bit 2 


Receive Frame Interrupt 


1 


Data Bit 1 


Station Address Bit 1 


TX Complete Interrupt 





Data Bit 


Station Address Bit 


Interrupt Request 



Summary of 8255 Port Signals 



Cluster Adapter 93 



Cluster Bus Interface 

The bus interface consists of a transmitter, receiver, carrier sense 
circuitry, and internal loopback-mode logic. They are the 
interface between the 8031 serial port and the 75fi coaxial cable. 



Cluster Adapter Transmitter 

The Cluster Adapter transmitter consists of an Am26LS29 
tri-state, single-ended, line driver. This driver features a high 
capacitive-load drive capability with buffered outputs, individual 
rise-time control, and output short-circuit protection. 

To transmit data to the bus, the microprocessor code in the 8031 
must first enable the -RTS signal on the port 3 interface. Data 
can then be sent to the bus bit-by-bit from +TXD on port 3. 

The transmitter is electrically isolated from the logic circuits on 
the Cluster Adapter by an HCPL-2531 high-speed optocoupler, 
which uses a light-emitting diode and an integrated light detector 
to obtain electrical insulation. 



Cluster Adapter Receiver 

The Cluster Adapter receiver consists of an Am26LS34 
high-performance, differential line receiver. 

The received signal is amplified by a 5535 Operational Amplifier 
and is provided to the Am26LS34. To receive the digital data, the 
microprocessor code in the 8031 must ensure that the +Internal 
Loop signal on port 3 is inactive. Data can then be received 
bit-by-bit at port 3 from +RXD. 

The receiver is also electrically isolated from the logic circuits on 
the Cluster Adapter by an HCPL-2531 high-speed optocoupler. 



94 Cluster Adapter 



Carrier Sense Circuitry 

The carrier sense circuitry provides information about the state of 
the Cluster Adapter. This information is needed to implement 
the collision avoidance protocol. The amplified signal received 
from the bus is passed through a comparator to detect the 
negative voltage state (less than approximately -150 millivolts). 
This negative portion of the signal is inverted into +NRXD and 
then ORed with the positive portion (greater than approximately 
+ 150 millivolts) of the +RXD signal. The result is then sent to 
the clear input of a 74LS161 counter. As long as this ORed 
signal (CLR) is active (0), the counter is held reset. When the 
signal goes inactive (1), the counter begins counting on the rising 
edges of the 8031 +ALE signal. On the fourth +ALE pulse, the 
counter is disabled and the -Carrier Sense signal goes inactive (1). 
The time delay between the bus going inactive and -Carrier Sense 
going inactive is 1.5 /xs. 



Internal Loopback Mode 

The Cluster Adapter provides logic to allow the 803 1 to receive 
the data it is transmitting without interference from the bus by 
wrapping the transmitter to the receiver on the Cluster Adapter. 

The adapter is placed into internal loopback mode when the 8031 
microprocessor code sets the + Internal Loop signal active (1). 
This mode returns any data transmitted on -hTXD to +RXD. 
Notice that -RTS may or may not be active. If -RTS is active, the 
data not only returns to -hRXD, but also is transmitted to the bus. 



Cluster Adapter 95 



Specifications 



Ballpoint 
Pen 




Signal 



Jumper 



Jumper 



Shield 



96 Cluster Adapter 



Logic Diagrams 

The following pages contain logic diagrams. 



Cluster Adapter 97 




.1^ I : 



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S TIT 







Cluster Adapter (Sheet 1 of 3) 



98 Cluster Adapter 




Cluster Adapter 99 













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Cluster Adapter (Sheet 2 of 3) 



100 Cluster Adapter 



ft 
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Cluster Adapter (Sheet 3 of 3) 



102 Cluster Adapter 



Index 



adapter reset 89 
address switch settings 85 



B 



BIOS interface 20 
block diagram 3 



check inside DLCP flag 68 
cluster access protocol 29 
Cluster Adapter 1 

adapter reset 89 

address switch settings 85 

BIOS interface 20 

block diagram 3 

bus interface 94 

check inside DLCP flag 68 

cluster access protocol 29 

cluster initialization (DLCP initialization) 44 

cluster status 58 

cluster status table 35 

collision avoidance 30 

control field format 25 

diagnostic function 1 73 



Index- 1 



diagnostic function 2 75 

diagnostic function 3 76 

diagnostic function 4 77 

diagnostic function 5 78 

diagnostic function 6 79 

diagnostic function 7 80 

display cluster status 55 

DLCP BIOS commands 42 

dump statistics 7 1 

error detection and recovery 34 

frame format 24 

frame reception 33 

frame transmission 22 

I/O addresses 83 

I/O register definitions 12 

Intel 8031 memory map 10 

Intel 803 1 port signals 5 

Intel 8255 port signals 91 

interrupt interface 90 

interrupts 16 

Link Control Block (LCB) 21 

memory interface 90 

polynomial generator checker 10 

programming considerations 18 

read IPL switch 69 

read station address 66 

receive frame 5 1 

receive virtual frame 49 

remote IPL 37 

set Multicast address 67 

special transmit mode command bits 8 1 

start DLCP 70 

status 60 

status register bit definitions 13 

stop DLCP 65 

switch blocks bit assignments 84 

switch settings 84 

transmit broadcast frame 6 1 

transmit frame 53 

transmit virtual frame 63 
Cluster Adapter switch settings 84 
cluster bus interface 94 
cluster initialization (DLCP initialization) 44 



Index-2 



cluster status 58 
cluster status table 35 
collision avoidance 30 
control field format 25 



D 



data link control program (DLCP) 18 
diagnostic function 1 73 
diagnostic function 2 75 
diagnostic function 3 76 
diagnostic function 4 77 
diagnostic function 5 78 
diagnostic function 6 79 
diagnostic function 7 80 
display cluster status 55 
DLCP BIOS commands 42 
dump statistics 7 1 



E 

error detection and recovery 34 



frame format 24 
frame reception 33 
frame transmission 22 



Index-3 



I/O addresses 83 
I/O register definitions 12 
Intel 8031 memory map 10 
Intel 8031 port signals 5 
Intel 8255 port signals 91 
interrupt interface 90 
interrupts 16 



link control block (LCB) 21 

M 

memory interface 90 



polynomial generator checker 10 
programming considerations 18 



R 



read IPL switch 69 
read station address 66 



Index-4 



receive frame 5 1 
receive virtual frame 49 
remote IPL 37 



set multicast address 67 

special transmit mode command bits 8 1 

start DLCP 70 

status 60 

status register bit definitions 1 3 

stop DLCP 65 

switch blocks bit assignments 84 



transmit broadcast frame 6 1 
transmit frame 53 
transmit virtual frame 63 



Index-5 



Index-6 



Personal Computer 
Hardware Reference 
Library 



IBM Game Control 
Adapter 



6361493 



Contents 



Description 1 

Programming Considerations 3 

Address Decode 3 

Data Bus Buffer/Driver 3 

Trigger Buttons 3 

Joystick Positions 3 

I/O Channel Description 4 

Interface 5 

Specifications 7 

Logic Diagram 9 



ui 



IV 



Description 



The IBM Game Control Adapter allows up to four paddles or two 
joysticks to be attached to the system. This adapter fits into one 
of the system board's or expansion board's expansion slots. The 
game control interface cable attaches to the rear of the adapter. 
In addition, four inputs for switches are provided. Paddle and 
joystick positions are determined by changing resistive values sent 
to the adapter. The adapter, when used with system software, 
converts the present resistive value to a relative paddle or joystick 
position. On receipt of an output signal, four timing circuits are 
started. By determining the time required for the circuit to 
timeout (a function of the resistance), the paddle position can be 
determined. This adapter could be used as a general purpose I/O 
card with four analog (resistive) inputs plus four digital input 
points. 



A9-A0 

1 



o 



AEN 



low 



lOR 



Instruction 
Decode 



D7-D0 



C 



Data Bus 

Buffer/ 

Driver 



C 



V 



Convert 
Resistance 
Digital 
Pulse 



< 



Resistive Input 



Typical Frequency 
833 Hz 



Digital Inputs 



Game Control Adapter Block Diagram 



Game Control Adapter 1 



2 Game Control Adapter 



Programming Considerations 



Address Decode 

The select on the Game Control Adapter is generated by two 
74LS138s as an address decoder. AEN must be inactive while 
the address is hex 201 in order to generate the select. The select 
allows a write to fire the one-shots, or a read to give the values of 
the trigger buttons and one-shot outputs. 



Data Bus Buffer/Driver 

The data bus is buffered by a 74LS244 buffer/driver. For an In 
from address hex 201, the Game Control Adapter will drive the 
data bus; at all other times, the buffer is left in the high 
impedance state. 



Trigger Buttons 



The trigger button inputs are read by an In from address hex 201. 
A trigger button is on each joystick or paddle. These values are 
seen on data bits 7 through 4. These buttons default to an open 
state and are read as 1. When a button is pressed, it is read as 0. 
Software should be aware that these buttons are not debounced in 
hardware. 



Joystick Positions 

The joystick position is indicated by a potentiometer for each 
coordinate. Each potentiometer has a range of to 100 kilohms 
that varies the time constant for each of the four one-shots. As 
this time constant is set at different values, the output of the 
one-shot will be of varying durations. 



Game Control Adapter 3 



All four one-shots are fired at once by an Out to address hex 201. 
All four one-shot outputs will go true after the fire pulse and will 
remain high for varying times depending on where each 
potentiometer is set. 

These four one-shot outputs are read by an In from address hex 
201 and are seen on data bits 3 through 0. 



I/O Channel Description 

A9-A0: Address Hues 9 through are used to address the 

Game Control Adapter. 

D7-D0: Data Unes 7 through are the data bus. 

lOR, lOW: I/O Read and I/O Write are used when reading 
from or writing to an adapter (In, Out). 

AEN: When active, the adapter must be inactive and the 

data bus driver inactive. 

+5 Vdc: Power for the Game Control Adapter. 

GND: Common ground. 

The following I/O channel lines are not used: 

MEMR, MEMW ALE, T/C 

DACK0-DACK3 CLK, OSC 

IRQ7-IRQ2 -5 Vdc 

DRQ3-DRQ1 +12 Vdc 

I/OCHRDY -12 Vdc 

I/O CH CK RESET DRV 

A19-A10 



4 Game Control Adapter 



Interface 



The Game Control Adapter has eight input lines; four digital 
inputs and four resistive inputs. The inputs are read with one In 
from address hex 201. 

The four digital inputs each have a 1-kilohm pullup resistor to +5 
Vdc. With no drives on these inputs, a 1 is read. For a reading, 
the inputs must be pulled to ground. 

The four resistive pullups, measured to +5 Vdc, will be converted 
to a digital pulse with a duration proportional to the resistive load, 
according to the following equation: 

Time = 24.2 /xs + 0.011 (r) /xs 

The user must first begin the conversion by an Out to address hex 
201. An In from address hex 201 will force the digital pulse to go 
high and remain high for the duration according to the resistance 
value. All four bits (bit 3-bit 0) function in the same manner; 
their digital pulse will all go high simultaneously and will reset 
independently according to the input resistance value. 



Bit? 


Bit 6 


Bit 5 


Bit 4 


Bits 


Bit 2 


Bit 1 


BitO 



Digital Inputs Resistive Inputs 

The typical input to the Game Control Adapter is a set of 
joysticks or game paddles. 

The joysticks will typically be a set of two (A and B). These will 
have one or two buttons each with two variable resistances each, 
with a range of to 100 kilohms. One variable resistance will 
indicate the X coordinate and the other variable resistance will 
indicate the Y coordinate. 



Game Control Adapter 5 



The joystick should be attached to give the following input data: 



Bit? 


Bite 


Bit 5 


Bit 4 


Bit 3 


Bit 2 


Bit 1 


BitO 


B-#2 
Button 


B-#1 
Button 


A-#2 
Button 


A-#1 
Button 


B-Y 
Coordinate 


B-X 

Coordinate 


A-Y 
Coordinate 


A-X 
Coordinate 



The game paddles will consist of two (A and B) or four (A, B, C, 
and D) p