Skip to main content

Full text of "sgs :: dataBooks :: 1990 SGS Z8000 Microprocessor Family Programming"

See other formats


Z8000 
MICROPROCESSOR 

FAMILY 



*.N I 



PROGRAMMING 





1 st EDITION 



^ 





Z8000 

MICROPROCESSOR 

FAMILY 



PROGRAMMING 



1 st EDITION 



JUNE 1990 



CONTENTS 



Instruction Set 1 

Introduction 1 

Functional Summary 1 

Load and Exchange Instructions 1 

Arithmetic Instructions 2 

Logical Instructions 3 

Program Control Instructions 3 

Bit Manipulation Instructions , 4 

Rotate and Shift Instructions 5 

Block Transfer And String Manipulation 5 

Input/Output Instructions . 6 

CPU Control Instructions 7 

Extended Instructions 7 

Processor Flags 8 

Condition Codes 9 

Instruction Interrupts and Traps . 9 

Notation and Binary Encoding 10 

Z8000 Instruction Descriptions and Formats 13 

EPA Instruction Templates 169 

Programmers Quick Reference 173 



Instruction Set 



Introduction 

This Manual describes the instruction set of 
the Z8000. An overview of the instruction set is 
presented first, in which the instructions are 
divided into ten functional groups. The 
instructions in each group are listed, followed 
by a summary description of the instructions. 
Significant characteristics shared by the 
instructions in the group, such as the available 
addressing modes, flags affected, or inter- 
ruptibility, are described. Unusual instructions 
or features that are not typical of predecessor 
microprocessors are pointed out. 

Following the functional summary of the 
instruction set, flags and condition codes are 



discussed in relation to the instruction set. This 
is followed by a section discussing interrupt- 
.ibility of instructions and a description of 
traps. The last part of this chapter consists, of a 
detailed description of each Z8000 instruction, 
listed in alphabetical order. This section is 
intended to be used as a reference by Z8000 
programmers. The entry for each instruction 
includes a description of the instruction, 
addressing modes, assembly language mne- 
monics, instruction formats, execution times' 
and simple examples illustrating the use of the 
instruction. 



Functional Summary 

This section presents an overview of the 
Z8000 instructions. For this purpose, the 
instructions may be divided into ten functional 
groups: 

■ Load and Exchange 

■ Arithmetic 

■ Logical 

■ Program Control 

■ Bit Manipulation 

■ Rotate and Shift 

■ Block Transfer and String Manipulation 

■ Input/Output 

■ CPU Control 

■ Extended Instructions 

The Load and Exchange group includes, a 
variety of instructions that provide for move- 
ment of data between registers, memory, and 
the program itself (i.e., immediate data). These 
instructions are supported with the widest 
range of addressing modes, including the Base 
(BA) and the Base Index (BX) mode which are 
available here only. None of these instructions 
affect any of the CPU flags. 

The Load and Load Relative instructions 
transfer a byte, word, or long word of data 
from the source operand to the destination 
operand. A special one-word instruction, LDK, 



is also included to handle the frequent require- 
ment for loading a small constant (0 to 15) into 
a register. - 

Load and Exchange Instructions. 

Instruction Operand(s) Name of Instruction 



CLR 
CLRB 


dst 


Clear 


EX 
EXB 


dst, src 


Exchange 


LD 

LDB 

LDL 


dst, src 


Load 


LDA 


dst, src 


Load Address 


LDAR 


dst. src 


Load Address Relative 


LDK 


dst, src 


Load Constant 


LDM 


dst, src, num 


Load Multiple 


LDR 

LDRB 

LDRL 


dst, src 


Load Relative 


POP 
POPL 


dst, src 


Pop 


PUSH 
PUSHL 


dst, src 


Push 



These instructions basically provide one of 
the following three functions: 
■ Load a register with data from a register or 

a memory location. 



Functional Summary (Continued) 

■ Load a memory location with data from a 
register. 

■ Load a register or a memory location with 
immediate data. 

The memory location is specified using any 
of the addressing modes (IR, DA, X, BA, 
BX, RA). 

The Clear and Clear Byte instructions can 
be used to clear a register or memory location 
to zero. While this is functionally equivalent to 
a Load Immediate where the immediate data is 
zero, this operation occurs frequently enough 
to justify a special instruction that is more 
compact and faster. 

The Exchange instructions swap the contents 
of the source and destination operands. 

The Load Multiple instruction provides for 
efficient saving and restoring of registers. This 
can significantly lower the overhead of pro- 
cedure calls and context switches such as 
those that occur at interrupts. The instruction 
allows any contiguous group of 1 to 16 regis- 
ters to be transferred to or from a memory 
area, which can be designated using the DA, 
IR or X addressing modes. (RO is considered to 
follow R 15, e.g., one may save R9-R15 and 
R0-R3 with a single instruction.) 

Stack operations are supported by the 
PUSH, PUSHL, POP, and POPL instructions. 
Any general-purpose register (or register pair 
in segmented mode) may be used as the stack 
pointer except RO and RRO. The source 
operand for the Push instructions and the 
destination operand for the Pop instructions 
may be a register or a memory location, 
specified by the DA, IR, or X addressing 
modes. Immediate data can also be pushed 
onto a stack one word at a time. Note that byte 
operations are N not supported, and the stack 
pointer register must contain an -even value 
when a stack instruction is executed. This is 
consistent with the general restriction of using 
even addresses for word and long word 
accesses. 

The Load Address and Load Address Rela- 
tive instructions compute the effective address 
for the DA, X, BA, BX and RA modes and 
return the value in a register. They are use- 
ful for management of complex data structures. 

The Arithmetic group consists of instructions 
for performing integer arithmetic. The basic 



instructions use standard two's complement 
binary format and operations. Support is also 
provided for implementation of BCD 
arithmetic. 

Arithmetic Instructions 

Instruction Operandi s) Name of Instruction 

ADC dst, src Add with Garry 

ADCB 



ADD 

ADDB 

ADDL 


dst, src 


Add 


CP 

CPB 

CPL 


dst, src 


Compare 


DAB 


dst 


Decimal Adjust 


DEC 
DECB 


dst, src 


Decrement 


DIV 
DIVL 


dst, src 


Divide 


EXTS 

EXTSB 

EXTSL 


dst 


Extend Sign 


INC 
INCB 


dst, src 


Increment 


MULT 
MULTL 


dst, src 


Multiply 


NEG 
NEGB 


dst 


Negate 


SBC 
SBCB 


dst, src 


Subtract with Carry 


SUB 

SUBB 

SUBL 


dst, src 


Subtract 



Most ot the instructions in this, group per- 
form an operation between a register operand 
and a second operand designated by any. of 
the five^basic addressing modes, and load the 
result into the register. 

The arithmetic instructions in general alter 
the C, Z, S and P/V flags, which can then be 
tested by subsequent conditional jump instruc- 
tions. The P/V flag is used to indicate arith- 
metic overflow for these instructions and it is 
referred to as the-V (overflow) flag. The byte 
version of these instructions generally alters 
the D and H flags as well. 

The basic integer (binary) operations are 
performed on byte, word or long word oper- 
ands, although not all operand sizes are sup- 
ported by all instructions. Multiple precision 
operations can be implemented in software 
using the Add with Carry, (ADC, ADCB), 



Functional Summary (Continued) 



Subtract with Carry (SBC, SBCB) and Extend 
Sign (EXTS, EXTSB, EXTSL) instructions. 

BCD operations are not provided directly, 
but can be implemented using a binary addi- 
tion (ADC, ADCB) or subtraction (SUBB, 
SBCB) followed by a decimal adjust instruc- 
tion (DAB). 

The Multiply and Divide instructions perform 
signed two's complement arithmetic on word or 
long word operands. The Multiply instruction 
(MULT) mutliplies two 16-bit operands and 
produces a 32-bit result, which is loaded into 
the destination register pair. Similarly, Mult- 
iply Long (MULTL) multiplies two 32-bit oper- 
ands and produces a 64-bit result, which is 
loaded into the destination register quadruple. 
An overflow condition is never generated by a 
multiply, nor can a true carry be generated. 
The carry flag is used instead' to indicate 
where the product has too many significant bits 
to be contained entirely in the low-order half 
of the destination. 

The Divide instruction (DIV) divides a 32-bit 
number in the destination register pair by a 
16-bit source operand and loads a 16-bit quo- 
tient into the, low-order half of the destination 
register. A 16-bit remainder is loaded into the 
high-order half. Divide Long (DIVL) operates 
similarly with a 64-bit destination register 
quadruple and a 32-bit source. The overflow 
flag is set if the quotient is bigger than the 
low-order half of the destination, or if the 



source is 


zero. 




Logical Instructions. 




Instruction 


Operand(s) 


Name of Instruction 


AND 
ANDB 


dst, src 


And 


COM 
COMB 


dst 


Complement 


OR 
ORB 


dst, src 


Or 


TEST 

TESTB 

TESTL 


dst 


Test 


XOR 
XORB 


dst, src 


Exclusive Or 



The instructions in this group perform logi- 
cal operations on each of the bits of the oper- 
ands. The operands may be bytes or words; 
logical operations on long word are not sup- 
ported (except for TESTL) but are easily imple- 



mented with pairs of instructions. 

The two-operand instructions, And (AND, 
ANDB), Or (OR, ORB) and Exclusive-Or 
(XOR, XORB) perform the appropriate logical 
operations on corresponding bits of the desti- 
nation register and the source operand, which 
can be designated by any of four basic add- 
ressing modes (R, IR, DA, IM, X). The result is 
loaded into the destination register. 

Complement (COM, COMB) complements 
the bits of the destination operand. Finally, 
Test (TEST, TESTB, TESTL) performs the OR 
operation between the destination operand and 
zero and sets the flags accordingly. The Com- 
plement and Test instructions can use four 
basic addressing modes to specify the 
destination. 

The Logical instructions set the Z and S flags 
based on the result of the operation. The byte 
variants of these instructions also set the Parity 
Flag (P/V) if the parity of the result is even, 
while the word instructions leave this flag 
unchanged. The H and D flags are not affected 
by these instructions. 

Program Control Instructions. 

Instruction Operand(s) Name of Instruction 

dst 



CALL 

CALR 

DJNZ 
DBJNZ 

IRET 

JP 

JR 

RET 

SC 



dst 



, dst 



, dst 
, dst 



Call Procedure 

Call Procedure Relative 

Decrement and Jump if 
Not Zero 

Interrupt Return 

Jump 

Jump Relative 

Return from Procedure 

System Call 



This group consists of the instructions that 
affect the Program Counter (PC) and thereby 
control program flow. General-purpose 
registers and memory are not altered except 
for the processor stack pointer and the pro- 
cessor stack, which play a significant role in 
procedures and interrupts. (An exception is 
Decrement and Jump if Not Zero (DJNZ), which 
uses a register as a loop counter.) The flags 
are also preserved except for IRET which 
reloads the program status, including the 
flags, from the processor stack. 

The Jump (JP) and Jump Relative (JR) 
instructions provide a conditional transfer of 
control to a new location if the processor flags 



Functional Summary (Continued) 



stati'sfy the condition specified in the condition 
code field of the instruction. Jump 
Relative is a one-word instruction that will 
jump to any instruction within the range -254 
to +256 bytes from the current location. Most 
conditional, jumps in programs are made to 
locations only a few bytes away; the Jump 
Relative instruction exploits this fact to 
improve code compactness and efficiency. 

Call and Call Relative are used for calling 
procedures; the current contents of the PC are 
pushed onto the processor stack, and the effec- 
tive address indicated by the instruction is 
loaded into the PC. The use of a procedure 
address stack in this manner allows straight- 
forward implementation of nested and recur- 
sive procedures. Like Jump Relative, Call 
Relative provides a one^word instruction for 
calling nearby subroutines. However, a much 
larger range, -4092 to +4098 bytes for CALR 
instruction, is provided since subroutine, calls 
exhibit less locality than normal control 
transfers. 

Both Jump and Call instructions are 
available with the indirect register, indexed 
and relative address modes in addition to the 
direct address mode. These can be useful for 
implementing complex control structures such 
as dispatch tables. 

The Conditional Return instruction is a com- 
panion to the Call instruction; if the condition 
specified in the instruction is satisfied, it loads 
the PC from the stack and pops the stack. 

A special instruction, Decrement and Jump 
if Not Zero (DJNZ, DBJNZ), implements the 
control part of the basic PASCAL FOR loop in 
a one- word instruction. 

System Call (SC) is used for controlled 
access to facilities provided by the operating 
system. It is implemented identically to a trap 
or interrupt: the current program status is 
pushed onto the system processor stack fol- 
lowed by the instruction itself, and a new pro- 
gram status is loaded from a dedicated part of 
the Program Status Area. An 8-bit immediate 
source field in the instruction is ignored by the 
CPU hardware. It can be retrieved from the 
stack by the software which, handles system 
calls and interpreted as desired, for example 
as an index into a dispatch table to implement 
a call to one of the services provided by the 
operating system. 



Interrupt Return (IRET) is used for returning 
from interrupts and traps, including system 
calls, to the interrupted routines. This is a 
privileged instruction. 

Bit Manipulation Instructions 

Instruction Operand(s) Name of Instruction 

BIT dst, src Bit Test 

BITB 

Reset Bit 



Set Bit 



Test and Set 



Test condition code 



RES dst, src 

RESB 

SET dst, src 

SETB 

TSET dst 

TSETB 

TCC cc, dst 

TCCB 

The instructions in this group are useful for 
manipulating individual bits in registers or 
memory. In most computers, this has to be 
done using the logical instructions with suit- 
able masks, which is neither natural nor 
efficient. 

The Bit Set (SET, SETB) and Bit Reset (RES, 
RESB) instructions set or clear a single bit in 
the destination byte or word, which can be in 
a register or in a memory location specified by 
any of the five basic addressing modes. The 
particular bit to be manipulated may be speci- 
fied statically by a value (0 to 7 for byte, to 
15 for word) in the instruction itself or it may 
be specified dynamically by the contents of a 
register, which could have been computed by 
previous instructions. In the latter case, the 
destination is restricted to a register. These 
instructions leave the flags unaffected. The 
companion Bit Test instruction (BIT, BITB) 
similarly tests a specified bit and sets the Z flag 
according to the state of the bit. 

The Test and Set instruction (TSET, TSETB) 
is useful in multiprogramming and multipro- 
cessing environments. It can be used for 
implementing synchronization mechanisms 
between processes on the same or differ- 
ent CPUs. 

Another instruction in this group, Test Con- 
dition Code (TCC, TCCB) sets a bit in the des- 
tination register based on the state of the flags 
as specified by the condition code in the 
instruction. This may be used to control sub- 
sequent operation of the program after the 
flags have been changed by intervening 



Functional Summary (Continued) 



instructions. It may also be used by language 
compilers for generating boolean values. 



Rotate and 
Instruction 

RL 
RLB 

RLC 
RLCB 

RLDB 

RR 
RRB 

RRC 
RRCB 

RRDB 

SDA 

SDAB 

SDAL 

SDL 

SDLB 

SDLL 

SLA 

SLAB 

SLAL 

SLL 

SLLB 

SLLL 

SRA 
SRAB 
SRAL v 

SRL 

SRLB 

SRLL 



Shift Instructions. 
Operandi s) Name of Instruction 

dst, src Rotate Left 



dst, 


src 


Rotate Left through 
Carry 


dst, 


src 


Rotate Left Digit 


dst, 


src 


Rotate Right 


dst, 


src 


Rotate Right through 
Carry 


dst, 


src 


Rotate Right Digit 


dst, 


src 


Shift Dynamic Arithmetic 



dst, src 



dst, src 



Shift Dynamic Logical 



Shift Left Arithmetic 



dst, src Shift Left Logical 



dst, src Shift Right Arithmetic 



dst, src Shift Right Logical 



This group contains a rich repertoire of 
instructions for shifting and rotating data 
registers. 

Instructions for shifting arithmetically or 
logically in either direction are available. 
Three operand lengths are supported: 8, 16 
and 32 bits. The amount of the shift, which 
may be any value up to the operand length, 
can be specified statically by a field in the 
instruction or dynamically by the contents of a 
register. The ability to determine the shift 
amount dynamically is a useful feature, which 
is not available in most minicomputers. 

The rotate instructions will rotate the con- 
tents of a byte or word register in either direc- 
tion by one or two bits; the carry bit can be 
included in the rotation. A pair of digit rota- 
tion instructions (RLDB, RRDB) are especially 
useful in manipulating BCD data. 



Block Transfer And String Manipulation 

Instructions. 

Instruction Operandi s) Name of Instruction 

CPD dst, src, r, cc Compare and Decrement 



CPDB 










CPDRB 


dst, 


src, r, 


cc 


Compare, Decrement and 
Repeat 


CPI 
CPIB 


dst, 


src, r, 


cc 


Compare and Increment 


CPIR 
CPIRB 


dst, 


src, r, 


cc 


Compare, Increment and 
Repeat 


CPSD 
CPSDB 


dst, 


src, r, 


cc 


Compare String and 
Decrement 


CPSDR 
CPSDRB 


dst, 


src, r, 


cc 


Compare String, 
Decrement and Repeat 


CPSI 
CPSIB 


dst, 


src, r, 


cc 


Compare String and 
Increment 


CPSIR 
CPSIRB 


dst, 


src, r, 


cc 


Compare String, 
Increment and Repeat 


LDD 
LDDB 


dst, 


src, r 




Load and Decrement 


LDDR 
LDRB 


dst, 


src, r 




Load, Decrement and 
Repeat 


LDI 
LDIB 


dst, 


src, r 




Load and Increment 


LDIR 
LDIRB 


dst, 


src, r 




Load, Increment and 
Repeat 


TRDB 


dst, 


src, r 




Translate and Decrement 


TRDRB 


dst, 


src, r 




Translate, Decrement and 
Repeat 


TRIB 


dst, 


src, r 




Translate and Increment 


TRIRB 


dst, 


src, r 




Translate, Increment and 
Repeat 


TRTDB 


srcl 


, src2, 


r 


Translate, Test and 
Decrement 


TRTDRB 


srcl 


, src2, 


r 


Translate, Test, 
Decrement and Repeat 


TRTIB 


srcl 


, src2, 


r 


Translate, Test and 
Increment 


TRTIRB 


srcl 


, src2, 


r 


Translate, Test, Increment 
and Repeat 



This is an exceptionally powerful group of 
instructions that provides a full complement of 
string comparison, string translation and block 
transfer functions. Using these instructions, a 
byte or word block of any. length up to 64K 
bytes can be moved in memory; a byte or word 
string can be searched until a given value is 
found; two byte "or word strings can be com- 
pared; and a byte string can be translated by 
using the value of each byte as the address of 



Functional Summary (Continued) 



its own replacement in a translation table. The 
more complex Translate and Test instructions 
skip over a class of bytes specified by a 
translation table, detecting bytes with values 
of special interest. 

All the operations can proceed through the 
data in either direction. Furthermore, the 
operations may be repeated automatically 
while decrementing a length counter until it is 
zero, or' they may operate on one storage unit 
per execution with the length counter decre- 
mented by one and the source and destination 
pointer registers properly adjusted. The latter 
form is useful for implementing more complex 
operations in software by adding other instruc- 
tions within a loop containing the block 
instructions. 

Any word register can be used as a length 
counter in most cases. If the execution of the 
instruction causes this register to be decre- 
mented to zero, the P/V flag is set. The auto- 
repeat forms of these instructions always leave 
this flag set. 

The D and H flags are not affected by any of 
these instructions. The C and S flags are 
preserved by all but the compare instructions. 

These instructions use the Indirect Register 
(IR) addressing mode: the source and destina- 
tion operands are addressed by the contents of 
general-purpose registers (word registers in 
nonsegmented mode and register pairs in seg- 
mented mode). Note that in the segmented 
mode, only the low-order half of the register 
pair gets incremented or decremented as with 
all address arithmetic in the Z8000. 

The repetitive forms of these instructions are 
interruptible. This is essential since the repeti- 
tion count can be as high as 65,536 and the 
instructions can take 9 to 14 cycles for each 
iteration after the first one. The instruction can 
be interrupted after any iteration. The address 
of the instruction itself, rather than the next 
one, is saved on the stack, and the contents of 
the operand pointer registers, as well as the 
repetition counter, are such that the instruc- 
tion can simply be reissued after returning 
from the interrrupt without any visible dif- 
ference in its effect. 

This group consists of instructions for trans- 
ferring a byte, word or block of data between 
peripheral devices and the CPU registers or 
memory. Two separate I/O address spaces with 



16-bit addresses are recognized, a Standard 
I/O address space and a Special I/O address 
space. The latter is intended for use with 
special Z8000 Family devices, typically the 
Z-MMU. Instructions that operate on the 
Special I/O address space are prefixed with 
the word "special." Standard I/O "and Special 
I/O instructions generate different codes on 
the CPU status lines. Normal 8-bit peripherals 

Input/Output Instructions. 

Instruction Oporand(s) Name of Instruction 

IN dst, src Input 

INB 

IND dst, src, r Input and Decrement 

INDB 

INDR dst, src, r Input, Decrement and 

INDRB Repeat 

INI dst, src, r Input and Increment 

INIB 

INIR dst, src, r Input, Increment and 

INIRB Repeat 

OTDR dst, src, r Output, Decrement and 

OTDRB Repeat 

OTIR dst, src, r Output, Increment and 

OTIRB Repeat 

OUT dst, src Output 

OUTB 

OUTD dst, src, r Output and Decrement 

OUTDB 

OUTI dst, src, r Output and Increment 

OUTIB 

SIN dst, src Special Input 

SINB 

SIND dst, src, r Special Input and 

SINDB Decrement 

SINDR dst, src, r Special Input, Decrement 

SINDRB and Repeat 

SINI dst, src, r Special Input and 

SINIB Increment 

SINIR dst, src, r Special Input, Increment 

SINIRB and Repeat 

SOTDR dst, src, r Special Output, 

SOTDRB Decrement and Repeat 

SOTIR dst, src, r Special Output, 

SOTIRB Increment and Repeat 

SOUT dst, src Special Output 

SOUTB 

SOUTD dst, src, r Special Output and 

SOUTDB Decrement 

SOUTI dst, src, r Special Output and 

SOUTIB Increment 



Functional Summary (Continued) 



are connected to bus lines AD0-AD7. Standard 
I/O byte instructions use odd addresses only. 
Special 8-bit peripherals such as the MMU, 
which are used with special I/O instructions, 
are connected to bus lines ADq-ADjs. Special 
I/O byte instructions use even addresses only. 

The instructions for transferring a single 
byte or word (IN, INB, OUT, OUTB, SIN, 
SINB, SOUT, SOUTB) can transfer data 
between any general-purpose register and any 
port in either address space. For the Standard 
I/O instructions, the port number may be 
specified statically in the instruction or dynam- 
ically by the contents of the CPU register. For 
the Special I/O instructions the port number is 
specified statically. 

The remaining instructions in this group 
form a powerful and complete complement of 
instructions for transferring blocks of data 
between I/O ports and memory. The operation 
of these instructions is very similar to that of 
the block move instructions described earlier, 
with the exception that one operand is always 
an I/O port which remains unchanged as the 
address of the other operand (a memory loca- 
tion) is incremented or decremented. These 
instructions are also interruptible. 



CPU Control Instructions 




Instruction 


Operand(s) 


Name of Instruction 


COMFLG 


flag 


Complement Flag 


DI 


int 


Disable Interrupt 


EI 


int 


Enable Interrupt 


HALT 




Halt 


LDCTL 


dst, src 


Load Control Register 


LDCTLB 






LDPS 


src 


Load Program Status 


MBIT 




Multi-Micro Bit Test 


MREQ 


dst 


Multi-Micro Request 


MRES 




Multi-Micro Reset 


MSET 




Multi-Micro Set 


NOP 




No Operation 


RESFLG 


flag 


Reset Flag 


SETFLG 


flag 


Set Flag 



All I/O instructions are privileged, i.e. they 
can only be executed in system mode. The 
single byte/word I/O instructions don't alter 
any flags. The block I/O instructions, includ- 
ing the single iteration variants, alter the Z and 
P/V flags. The latter is set when the repetition 
counter is decremented to zero. 

The instructions in- this group relate to the 
CPU control and status registers (FCW, PSAP, 
REFRESH, etc.), or perform other unusual 
functions that do not fit into any of the other 
groups, such as instructions that support multi- 
microprocessor operation. Most of these 
instructions are privileged, with the exception 
of NOP and the instructions operating on the 
flags (SETFLG, RESFLG, COMFLG, 
LDCTLB). 

Extended Instructions. The Z8000 
architecture includes a powerful mechanism 
for extending the basic instruction set through 
the use of external devices known as Extended 
Processing Units (EPUs). A group of 
six opcodes, OE, OF, 4E, 4F, 8E and 8F (in 
hexadecimal), is dedicated for the implemen- 
tation of extended instructions using this facil- 
ity. The five basic addressing modes (R, IR, 
DA, IM and X) can be used by extended 
instructions for accessing data for the EPUs. 

There are four types of extended instructions 
in the Z8000 CPU instruction repertoire: EPU 
internal operations; data transfers between 
memory and EPU; data transfers between EPU 
and CPU; and data transfers between EPU flag 
registers and CPU flag and control word. The 
last type is useful when the program must 
branch based on conditions determined by the 
EPU. The action taken by the CPU upon 
encountering extended instructions is depen- 
dent upon the EPA control bit in the CPU's 
FCW. When this bit is set, it indicates that the 
system configuration includes EPUs; therefore, 
the instruction is executed. If this bit is clear, 
the CPU traps (extended instruction trap) so 
that a trap handler in software can emulate the 
desired operation. 



Processor Flags 



The processor flags are a part of the pro- 
gram status, They provide a 
link between sequentially executed instructions 
in the sense that the result of executing one 
instruction may alter the flags, and. the 
resulting value of the flags may be used to 
determine the operation of a subsequent 
instruction, typically a conditional jump 
instruction. An example is a Test followed by a 
Conditional Jump: 

TEST Rl !sets Z flag if Rl = 0! 

JR Z, DONE !go to DONE if Z flag is 

set! 



DONE: 

The program branches to DONE if the TEST 
sets the Z flag, i.e., if Rl contains zero. 

The program status has six flags for the use 
of the programmer and the Z8000 processor: 

■ Carry (C) 
B Zero (Z) 

■ Sign (S) 

■ Parity/Overflow (P/V) 

■ Decimal Adjust (D) 

■ Half Carry (H) 

The flags are. modified by many instructions, 
including the arithmetic and logical 
instructions. 

Appendix C lists the instructions and the 
flags they affect. In addition, there are Z8000 
CPU control instructions which allow the pro- 
grammer to set, reset (clear), or complement 
any or all of the first four flags. The Half-Carry 
and Decimal-Adjust flags are used by the 
Z8000 processor for BCD arithmetic correc- 
tions. They are not used explicitly by the pro- - 
grammer. 

The FLAGS register can be separately 
loaded by the Load Control Register (LDCTLB) 
instruction without disturbing the control bits 
in the other byte of the FCW. The contents of 
the flag register may also be saved in a reg- 
ister or memory. 

The Carry (C) flag, when set, generally indi- 
cates a carry out of or a borrow into the high- 
order bit position of a register being used as 
an accumulator. For example, adding the 8-bit 



numbers 225 and 64 causes a carry out of bit 7 

and sets the Carry flag: 

Bit 
7 6 5 4 3 2 10 



225 
+ 64 


1 



1 1 
1 














1 



289 


It? 


1 
= Carry flag 











1 



The Carry flag plays an important role in the 
implementation of multiple-precision arithmetic 
(see the ADC, SBC instructions). It is also 
involved in the Rotate Left Through Carry 
(RLC) and Rotate Right Through Carry (RRC) 
instructions. One of these instructions is used 
to implement rotation or shifting of long strings 
of bits. 

The Zero (Z) flag is set when the result reg- 
ister's contents are zero following certain 
operations. This is often useful for deter- 
mining when a counter reaches zero. In addi- 
tion, the block compare instructions use the Z 
flag to indicate when the specified comparison 
condition is satisfied. 

The Sign (S) flag is set to one when the most 
significant bit of a result register contains a 
one (a negative number in two's complement 
notation) following certain operations. 

The Overflow (V) flag, when set, indicates 
that a two's complement number in a result 
register has exceeded the largest number or is 
less than the smallest number that can be 
represented in a two's complement notation. 
This flag is set as the result of an arithmetic 
operation. Consider the following example: 
Bit 
7 6 5 4 3 2 10 



120 

+ 105 



1 









225 



-1 



1 



1 



1 



^•►l = Overflow flag 

The result in this case (-95 in two's comple- 
ment notation) is incorrect, thus the overflow 
flag would be set. 

The same bit acts as a Parity (P) flag follow- 
ing logical instructions on byte operands. The 
number of one bits in the register is counted 
and the flag is set if the total is even (that is, 
P = 1). If the total is odd (P = 0), the flag is 
reset. This flag is often referred to as the 
P/V flag. 



Processor Flagi (Continued) 



The Block Move and String instructions and 
the Block I/O instructions use the P/V flag to 
indicate the repetition counter has decre- 
mented to 0. 

The Decimal-Adjust (D) flag is used for BCD 
arithmetic. Since the algorithm for correcting 
BCD operations is different for addition and 
subtraction, this flag is used to record whether 
an add or subtract instruction was executed so 
that the subsequent Decimal Adjust (DAB) 
instruction can perform its function correctly 
(See the DAB instruction for further discussion 



on the use of this flag). 

The Half-Carry (H) flag indicates a carry out 
of bit 3 or a borrow into bit 3 as the result of 
adding or subtracting bytes containing two 
BCD digits each. This flag is used by the DAB 
instruction to convert the binary result of a 
previous decimal addition or subtraction into 
the correct decimal (BCD) result. 

Neither the Decimal-Adjust nor the Half- 
Carry flag is normally accessed by the pro- 
grammer. 



Condition Codes 

The first four flags, C, Z, S, and P/V, are 
used to control the operation of certain xx condi- 
tional" instructions such as the Conditional 
Jump. The operation of these instructions is a 
function of whether a specified boolean condi- 
tion on the four flags is satisfied or not. It 
would take 16 bits to specify any of the 65,536 
(216) boolean functions of the four flags. Since 
only a very small fraction of these are general- 
ly of interest, this procedure would be very 
wasteful. Sixteen functions of the flag settings 
found to be frequently useful are encoded in a 
4-bit field called the condition code, which 



forms a part of all conditional instructions. 

The condition codes and the flag settings 
they represent are listed in Section 6.6. 

Although there are sixteen unique condition 
codes, the assembler recognizes more than six- 
teen mnemonics for the conditional codes. 
Some of the flag settings have more than one 
meaning for the programmer, depending on 
the context (PE & OV, Z & EQ, C & ULT, 
etc.). Program clarity is enhanced by having 
separate mnemonics for the same binary value 
of the condition codes in these cases. 



Instruction Interrupts and Traps 

This section looks at the relation-ship between in- 
structions ans interrupts. 

When the CPU receives an interrupt 
request, and it is enabled for interrupts of that 
class, the interrupt is normally processed at 
the end of the current instruction. However, 
certain instructions which might take a long 
time to complete are designed to be interrupt - 
ible so as to minimize the length of time it 
takes the CPU to respond to an interrupt. 
These are the iterative versions of the String 
and Block instructions and the Block I/O 
instruction. If an interrupt request is received 
during one of these interruptible instructions, 
the instruction is suspended after the current 
iteration. The address of the instruction itself, 
rather than the address of the following 
instruction, is saved on the stack, so that the 
same instruction is executed again when the 
interrupt handler executes an IRET. The con- 



tents of the repetition counter and the registers 
which index into the block operands are such 
that after each iteration when the instruction is 
reissued upon returning from an interrupt, the 
effect is the same as if the instruction were not 
interrupted. This assumes, of course, the inter- 
rupt handler preserved the registers, which is 
a general requirement on interrupt handlers. 

The longest noninterruptible instruction that 
can be used in normal mode is Divide Long 
(749 cycles in the worst case). Multi-Micro- 
Request, a privileged instruction, can take 
longer depending on the contents of the des- 
tination register. 

Traps are synchronous events that result 
from the execution of an instruction. The 
action of the CPU in response to a trap condi- 
tion is similar to the case of an interrupt (see 
Section 7). Traps are non-maskable. 



Instruction Interrupts and Traps (Continued) 



The Z8000 CPUs implement four kinds of 
traps: 

■ Extended Instruction 

■ Privileged Instruction in normal mode 

■ Segmentation violation 

■ System Call 

The Extended Instruction trap occurs when 
an Extended Instruction is encountered, but 
the Extended Processor Architecture Facility is 
disabled, i.e., the EPA bit in the FCW is a 
zero. This allows the same software to be run 
on Z8000 system configurations with or without 
EPUs. On systems without EPUs, the desired 
extended instructions can be emulated by soft- 
ware which is invoked by the Extended 
Instruction trap. 



The privileged instruction trap serves to pro- 
tect the integrity of a system from erroneous or 
unauthorized actions of arbitrary processes. 
Certain instructions, called privileged instruc- 
tions, can only be executed in system mode. 
An attempt to execute one of these instructions 
in normal mode causes a privileged instruction 
trap. All the I/O instructions and most of the 
instructions that operate on the FCW are 
privileged, as are instructions like HALT 
and IRET. 

The System Call instruction always causes a 
trap. It is used to transfer control to system 
mode software in a controlled way, typically to 
request supervisor services. 



Notation and Binary Encoding 

The rest of this chapter consists of detailed 
descriptions of each instruction, listed in 
alphabetical order. This section describes the 
notational conventions used in the instruction 
descriptions and the binary encoding for some 
of the common instruction fields (e.g., reqister 
designation fields). 

The description of an instruction begins with 
the instruction mnemonic and instruction name 
in the top part of the page. Privileged instruc- 
tions are also identified at the top. 

The assembler language syntax is then given 
in a single generic form that covers all the 
variants of the instruction, along with a list of 
applicable addressing modes. 

Example: 

AND dst, src dst: R 

ANDB src: R, IM, IR, DA, X 

The operation of the instruction is presented 
next, followed by a detailed discussion of the 
instruction. 

The next part specifies the effect of the 
instruction on the processor flags. This is 
followed by a table that presents all the 
variants of the instruction for each applicable 
addressing mode and operand size. For each 
of these variants, the following information is 
provided: 

A. Assembler Language Syntax. The syntax 
is shown for each applicable operand width 



(byte, word or long). The invariant part of the 
syntax is given in UPPER CASE and must 
appear as shown. Lower case characters repre- 
sent the variable part of the syntax, for which 
suitable values are to be substituted. The syn- 
tax shown is for the most basic form of the 
instruction recognized by the assembler. For 
example, 

ADD Rd,#data 

represents a statement of the form 
ADD R3,#35. The assembler will also accept 
variations like ADD TOTAL, #NEW-DELTA 
where TOTAL, NEW and DELTA have been 
suitably defined. 

The following notation is used for register 
operands: 

Rd, Rs, etc.: a word register in the 

range R0-R15 
Rbd Rbs: a byte register RHn or 

RLn where n = - 7 
RRd RRs: a register pair RRO, RR2, 

... RR14 
RQd: a register guadruple 

RQO, RQ4, RQ8 or RQ12 

The V or u d" represents a source or destina- 
tion operand. Address registers used in 
Indirect, Base and Base Index addressing 
modes represent word registers in nonseg- 
mentedmode and register pairs in segmented 
mode. A one-word register used in segmented 



10 



Notation and Binary Encoding (Continued) 



mode is flagged and a footnote explains the 
situation. 

B. Instruction Format. The binary encoding of 
the instruction is given in each case for both 
the nonsegmented and segmented modes.. 
Where applicable, both the short and long 
forms of the segmented version are given (SS 
and SL). 

The instruction formats for byte and word 
versions of an instruction are usually com- 
bined. A single bit, labeled "w," distinguishes 
them: a one indicates a word instruction, while 
a zero indicates a byte instruction. 

Fields specifying register operands are 
identified with the same symbols (Rs, RRd, 
etc.) as in Assembler Language Syntax. In 
some cases, only nonzero values are permitted 
for certain registers, such as index registers. 
This is indicated by a notation of the form 
"RS * 0." 

The binary encoding for register fields is as 
follows: 

Rogistor Binary 

RQO RRO R0 RHO 0000 

Rl RH1 0001 

RR2 R2 RH2 0010 

R3 RH3 0011 



Register 



Binary 



RQ4 



RQ8 



RQ12 



RR4 



RR6 



RR8 



RR10 



RR12 



RR14 



R4 


RH4 


0100 


R5 


<RH5 


0101 


R6 


RH6 


0110 


R7 


RH7 


0111 


R8 


RL0 


1000 


R9 


RL1 


1001 


R10 


RL2 


1010 


Rll 


RL3 


1011 


R12 


RL4 


1100 


R13 


RL5 


1101 


R14 


RL6 


1110 


R15 


RL7 


1111 



For easy cross-references, the same symbols 
are used in the Assembler Language Syntax 
and the instruction format. In the case of ad- 
dresses, the instruction format in segmented 
mode uses "segment" and "offset" to corres- 
pond to "address," while the instruction format 
contains "displacement," indicating that the 
assembler has computed the displacement and 
inserted it as indicated. 

A condition code is indicated by "cc" in 
both the Assembler Language Syntax and the 
instruction formats. The condition codes, the 
flag settings they represent, and the binary 
encoding in the instruction are as follows: 



Notation and Binary Encoding (Continued) 



Code 

F 

Z 

NZ 

C 

NC 

PL 

MI 

NE 

EQ 

OV 

NOV 

PE 

PO 

GE 

LT 
GT 
LE 

UGE 



ULT 
UGT 
ULE 



Meaning 

Always false 
Always true 
Zero 
Not zero 
Carry 
No carry 
Plus 
Minus 
Not equal 
Equal 
Overflow 
No overflow 
Parity even 
Parity odd 
Greater than 
or equal 
Less than 
Greater than 
Less than or 
equal 
Unsigned 
greater than 
or equal 
Unsigned 
less than 
Unsigned 
greater than 
Unsigned less 
than or equal 



Flag Setting 



Z = 1 
Z = 
C = 1 
C = 
S = 
S = 1 
Z = 
Z = 1 

V = 1 

V = 

p = 1 

P = 

(S XOR V) = 

(S XOR V) = 1 

(Z OR (S XOR V)) = 

(Z OR (S XOR V)) = 1 



C = 



Binary 

0000 
1000 
0110 
1110 
0111 

mi 

1101 
0101 
1110 
0110 
0100 
1100 
0100 
1100 
1001 

0001 
1010 
0010 

mi 



C = 1 




0111 


((C =0) AND(Z = 


0)) = 1 


1011 


(C OR Z) = 1 




0011 



Note that some of the condition codes correspond to identical flag settings: i.e., Z-EQ, NZ-NE, 
NC-UGE, PE-OV, PO-NOV. 



C. Cycles. This line gives the execution time 
of the instructions in CPU cycles. 



D. Example. A short assembly language 
example is given showing the use of the 
instruction. 



12 



Z8000 

Instruction 
Descriptions 
and Formats 



ADC 

Add With Carry 



ADC dst, src 
ADCB 



dst: R 
src: R 



Operation: 



dst -<- dst + src + c 



the source operand, along with the setting of the carry flag, is added to the destina- 
tion operand and the sum is stored in the destination. The contents of the source are 
not affected. Two's complement addition is performed. In multiple precision arith- 
metic, this instruction permits the carry from the addition of low-order operands to 
be carried into the addition of high-order operands. 



Flags: 



C: Set if thereus a carry from the most significant bit of the result; cleared 

otherwise 
Z: Set if the result is zero; cleared otherwise 
S: Set if the result is negative; cleared otherwise 
V: Set if arithmetic overflow occurs, that is, if both operands were of the same sign 

and the result is of the opposite sign; cleared otherwise 
D: ADC— unaffected; ADCB— cleared 
H: ADC — unaffected; ADCB — set if there is a carry from the most significant bit of 

the low-order four bits of the result; cleared otherwise 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


ADC Rd, Rs 
ADCB Rbd, Rbs 




5 






|lo|l101o|w| Rs | Rd | 


|io|noio|w| Rs | Rd | 


5 











Example: Long addition can be done with the following instruction sequence, assuming RO, Rl 

contain one operand and R2, R3 contain the other operand: 

ADD R1,R3 !add low-order words! 

ADC R0,R2 !add carry and high-order words! 

If RO contains %0000, Rl contains %FFFF, R2 contains %4320 and R3 contains 
%0001, then the above two instructions leave the value %4321 in RO and %0000 
inRl. 



13 



ADD 

Add 



ADD dst, src 

ADDB 

ADDL 



dst: R 

src: R, IM, IR, DA, X 



Operation: dst •*- dst + src 

The source operand is added to the destination operand and the sum is stored in the 
destination. The contents of the source are not affected. Two's complement addition 
is performed. 



Flags: 



C: Set if there is a carry from the most significant bit of the result; cleared otherwise 

Z: Set if the result is zero; cleared otherwise 

S: Set if the result is negative; cleared otherwise 

V: Set if arithmetic overflow occurs, that is, if both operands were of the same sign 

and the result is of the opposite sign; cleared otherwise 
D: ADD, ADDL— unaffected; ADDB— cleared 
H: ADD, ADDL — unaffected; ADDB — set if there is a carry from the most significant 

bit of the low-order four bits of the result; cleared otherwise 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


ADD Rd, Rs 
ADDB Rbd, Rbs 

ADDL RRd, RRs 
ADD Rd, #data 

ADDB Rbd, #data 

ADDL RRd, #data 

ADD Rd, @Rsi 
ADDB Rbd, @Rsi 

ADDL RRd, @Rsi 








4 
8 

7 
7 

14 

7 
14 










10|00000|w| Rs | Rd 


10|00O00|w| Rs | Rd 


4 












10| 101 10 | RRs | RRd 


1 o| 101 10 | RRs | RRd 


8 










IM: 




00|000001|0000| Rd 






| 000001 | oooo | Rd 




7 




data 


data 






















00 | 000000 


| Rd 






| 000000 


| Rd 




7 




data 


data 


data 


data 






















00| 0101 10 | 0000 | RRd 






0| 010110 | 00 | RRd 








31 data (high) 16 


31 data (high) 16 


14 




15 data (low) 


15 data (low) 




















IR: 


00|00000|w| Rs*0 | Rd 


00|00000|W| Rs*0 | Rd 


7 












00| 010110 | Rs*0 | RRd 


0| 010110 | Rs*0 | RRd 


14 















14 



ADD 

Add 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


DA: 


ADD Rd, address 
ADDB Rbd, address 

ADDL RRd, address 

ADD Rd, addr(Rs) 
ADDB Rbd, addr(Rs) 

ADDL RRd, addr(Rs) 








9 

15 
10 
16 










1 |00000|w| 0000 | Rd 




SS 


oi|ooooo|w 


| Rd 


10 




address 


segment 


offset 




















SL 


oi|ooooo|w 


I Rd 






1 | segment 


00000000 


12 




offset 






















0l| 010110 | 0000 | RRd 




SS 


1 1 010110 


000 | RRd 


16 




address 


segment 


offset 




















SL 


Oil 010110 


0000 I RRd 






1 segment 


00000000 


18 




offset 




X: 
















0l|00000|w| Rs*0 | Rd 




SS 


oi|ooooo|w 


Rs*0 | Rd 


10 




address 


segment 


offset 




















SL 


oi|oopoo|w 


Rs*0 I Rd 






1 segment 


00000000 


13 




offset 






















1 1 010110 | Rs*0 | RRd 




SS 


01010110 


Rs*0 | RRd 


16 




address 


segment 


offset 




















SL 


01010110 


Rs*0 I RRd 






1 segment 


00000000 


19 




offset 



















Example: 



ADD R2, AUGEND laugend A located at %1254! 

Before instruction execution: 



1252 
1254 
1256 



Memory 


R2 


Flags 




| B D 2 1 J 


CZSP/VDH 


6 4 4 




czspdh 







After instruction execution: 

Momory 
1252 
1254 
1256 



6 4 4 



R2 
|C 3 6 5| 



Flags 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



15 



AND 

And 



AND dst ; src 
ANDB 



dst: R 

src: R, IM, IR, DA, X 



Operation: 



dst ■*- dst AND src 



A logical AND operation is performed between the corresponding bits of the source 
and destination operands, and the result is stored in the destination. A one bit is 
stored wherever the corresponding bits in the two operands are both ones; otherwise 
a zero bit is stored. The source contents are not affected. 



Flags: 



C: Unaffected 

Z: Set if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 

P: AND — unaffected; ANDB — set if parity, of the resujt is even; cleared otherwise 

D: Unaffected 

H: Unaffected 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




AND Rd, Rs 
ANDB Rbd, Rs 

AND Rd, #data 
ANDB Rbd, #data 

AND Rd, @R S 1 
ANDB Rbd, @R S 1 

AND Rd, address 
ANDB Rbd, address 

AND. Rd, addr(Rs) 
ANDB Rbd, addr(Rs) 








4 
7 
7 
7 
9 

10 








R: 


1 o |o 1 1 |w | Rs | Rd 


1 o|o001 l|w| Rs | Rd | 


4 










IM: 




OOJ 0001 1 1 | 0000 | Rd 






00| 000111 | 0000 |- Rd 


7 




data 


data 




















00 I 0001 1 


| Rd 






| 0001 10 


00 | Rd 






data 


data 


data 


data 




IR: 














1 1 1 [ W | Rs * | Rd 


00|0001 l|w| Rs*0 | Rd | 


7 










DA: 




01 |o 00 1 1 1 W | 0000 | Rd 




SS 


1 |o 00 1 i|w 


| Rd 


10 




address 




segment 


offset 




















SL 


o 1 |ooo 1 1 1 w 


00 00 I Rd 






1 segment 


0000 0000 


12 




offset 




X: 
















Ol|o001l|w|Rs*o| Rd 




SS 


01I0001 ilw 


Rs*0 I Rd 


10 




address 


segment 


offset 




















SL 


010001 i|w 


Rs*0 | Rd 






1 segment 


0000 0000 


13 




offset 





















16 



AND 

And 



Example: 



ANDB RL3, # %CE 



Before instruction execution: 

RL3 

I 1110 111 



Flags 






C Z S P/V 


D 


H 


c z s p 


d 


h 



After instruction execution: 

RL3 

I 110 110 I 



Flags 



C Z S P/V D H 



c 1 1 d h 



Note 1 : Word register in nonsegmented mode, register pair in segmented mode. 



17 



BIT 

Bit Test 



BIT dst, src 
BITB 



dst: R, IR, DA, X 
src: IM 

or 

dst: R 
src: R 



Operation: 



Z -«- NOT dst (src) 



The specified bit within the destination operand is tested, and the Z flag is set to one 
if the specified bit is zero; otherwise the Z flag is cleared to zero. The contents of the 
destination are not affected. The bit number (the source) can be specified statically 
as an immediate value, or dynamically as a word register whose contents are the bit 
number. In the dynamic case, the destination operand must be a register, and the 
source operand must be RO through R7 for BITB, or RO through R15 for BIT. The bit 
number is a value from to 7 for BITB, or to 15 for BIT, with indicating the least 
significant bit. Note that only the lower four bits of the source operand are used to 
specify the bit number for BIT, while only the lower three bits of the source operand 
are used for BITB. 



Flags: 



C: Unaffected 

Z: Set if specified bit is zero; cleared otherwise 

S: Unaffected 

V: Unaffected 

D: Unaffected 

H: Unaffected 



Bit Test Static 



Destination 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycle 



Segmented Mode 



Instruction Format 



Cycles 



R: 
IR: 
DA: 



BIT Rd, b 
BITB Rbd, b 

BIT @Rdi , b 
BITB&Rdl, b 

BIT address, b 
BITB address, b 



1010011 W Rd b 



00 1001 1 W Rd*0 b 



011001 1 W 0000 b 



10 



1010011 W Rd 



00 1001 1 W Rd*0 b 



ss 



SL 



01 1001 i|w 


000 | b 


segment 


offset 



01 |l 001 ilw 


OOOOJ b 


1 segment 


0000 0000 


offset 



13 



18 



BIT 

Bit Test 



Bit TeSt Static (Continued) 



Source 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format Cycles 



X: 



R: 



BIT addr(Rd), b 
BITB addr(Rd), b 



BIT Rd, Rs 
BITB Rbd, Rs 



011001 1 W Rd*0 



SS 



SL 



01 |l 001 i|w 


Rd*0 | b 


segment 


offset 



01 10011 W Rd*0 



1 segment 



0000 0000 



oo|i 001 i|w 


0000 


Rs 


000 | Rd 


0000 


0000 



10 



1 1 1 1 | w 


0000 


Rs 


| Rd 


0000 


0000 



11 



14 



10 



Example: If register RH2 contains %B2 (10110010), the instruction 

BITB RH2 ; #0 
will leave the Z flag set to 1 . 

Note 1: Word register in. nonsegmented mode, register pair in segmented mode. 



19 



CALL 

Call 



CALL dst 



dst: IR, DA, X 



Operation: 



Nonsegmented 
SP <- SP - 2 
C -+ SP — PC 
PC +- dst 



Segmented 
SP «- SP - 4 
@SP *- PC 
PC «- dst 



Flags: 



The current contents of the program counter (PC) are pushed onto the top of the 
processor stack. The stack pointer used is R15 in nonsegmented mode, or RR14 in 
segmented mode. (The program counter value used is the address of the first instruc- 
tion byte following the CALL instruction.) The specified destination address is then 
loaded into the PC and points to the first instruction of the called procedure. 
At the end of the procedure a RET instruction can be used to return to original pro- 
gram. RET pops the top of the processor stack back into the PC. 

No flags affected 



Destination 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycle 



IR: 
DA: 



CALL <H Rd! 
CALL address 



00| 01 1 1 1 1 | Rd 


0000 




1 1 01 1 1 1 1 | 0000 


0000 


address 



10 



CALL addr(Rd) 



01011111 Rd *0 0000 



I 


0| 01 1 1 1 1 | Rd | 00 00 | 




ss 


1 | 01 1 1 1 1 


0000 | 0000 


segment 


offset 








Oil 01 1 1 1 1 


000 I 0000 


SL 


1 segment 


0000 000 




offset 






SS 


01 1 01 1 1 1 1 


Rs*0 | 0000 


segment 


offset 








01 | 01 1 1 1 1 


Rs*0 | 0000 


SL 


1 segment 


0000 0000 




offset 



15 



18 



20 



18 



21 



Example: In nonsegmented mode, if the contents of the program counter are %1000 and the 

contents of the stack pointer (R15) are %3002, the instruction 

CALL %2520 

causes the stack pointer to be decremented to %3000, the value % 1004 (the address 
following the CALL instruction with direct address mode specified) to be loaded into 
the word at location %3000, and the program counter to be loaded with the value 
%2520. The program counter now points to the address of the first instruction in the 
procedure to be executed. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



20 



CALR 

Call Relative 



CALRdst 



dst: RA 



Operation: Nonsegmented 

SP +- SP - 2 
@SP «- PC 
PC -+- PC - (2 x displacement) 



Segmented 

SP *- SP - 4 

@SP **- PC 

PC *- PC - (2 x displacement) 



The current contents of the program counter (PC) are pushed onto the top of the 
processor stack. The stack pointer used is R15 if nonsegmented, or RR14 if 
segmented. (The program counter value used is the address of the first instruction 
byte following the CALR instruction.) The destination address is calculated and then 
loaded into the PC and points to the first instruction of a procedure. 

At the end of the procedure a RET instruction can be used to return to the original 
program flow. RET pops the top of the processor stack back into the PC. 

The destination address is calculated by doubling the displacement in the 
instruction, then subtracting this value from the current value of the PC to derive the 
destination address. The displacement is a 12-bit signed value in the range -2048 to 
+2047. Thus, the destination address must be in the range -4092 to +4098 bytes 
from the start of the CALR instruction. In segmented mode, the PC segment number 
is not affected. The assembler automatically calculates the displacement by 
subtracting the PC value of the following instruction from the address given by the 
programmer. 



Flags: 


No flags affected 










Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




CALR address 


1 




10 






RA: 


110 1 displacement I 


| 1 1 1 J displacement | 


15 











Example: 



In nonsegmented mode, if the contents of the program counter are %1000 and the 
contents of the stack pointer (R15) are %3002, the instruction 

CALR PROC 

causes the stack pointer to be decremented to %3000, the value %1004 (the address 
following the CALR instruction) to be loaded into the word location %3000, and the 
program counter to be loaded with the address of the first instruction in procedure 
PROC. 



21 



CLR 

Clear 



CLR dst 
CLRB 



dst: R, IR, DA, X 



Operation: 



Flags: 



dst -+- 

The destination is cleared to zero. 
No flags affected. 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




CLRRd 
CLRB Rbd 

CLR @Rdf 
CLRB @Rdi 

CLR address 
CLRB address 

CLR addr(Rd) 
CLRB addr(Rd) 






I 
I 


7 
8 

11 
12 








R: 


1 o |o 1 io|w|Rd * | 1 000 


1 o|oo 1 10|w|Rd* o| 1 00 | 


7 


IR: 








00 |00 1 10|w|Rd * o| 1 000 


00|001 1o|w|Rd*o|lOOo| 


8 


DA: 










oi|oono|w|oooo|iooo 




SS 


o 1 |oo 1 io|w 


oooo|iooo 


12 




address 


segment 


offset 




















SL 


o 1 |oo i io|w 


0000 |l ooo 






1 segment 


0000 0000 


14 




offset 




X: 
















1 J00 1 10|w| Rd*0 | 1000 




SS 


o 1 |oo 1 io|w 


Rd*0 | 1000 


12 




address 


segment 


offset 




















SL 


o 1 (oo 1 io|w 


Rd*0 1 1 000 






1 segment 


0000 0000 


15 




offset 



















Example: If the word at location %ABBA contains 13, the statement 

CLR %ABBA 
will leave the value in the word at location %ABBA. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



22 



COM 

Complement 



COM dst 
COMB 



dst: R, IR, DA, X 



Operation: 



Flags: 



(dst - NOT dst) 

The contents of the destination are complemented (one's complement); all one bits 
are changed to zero, and vice- versa. 

C: Unaffected 

Z: Set if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 

P: COM — unaffected; COMB — set if parity of the result is even; cleared otherwise 

D: Unaffected 

H: Unaffected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


COMRd 
COMB Rbd 

COM c«Rdi 
COMB a Rdi 

COM address 
COMB address 

COM addr(Rd) 
COMB addr(Rd) 


1 






7 
12 

15 
16 








1 0|00 1 1 1 W | Rd * 0|0000 


io|ooi io|w|Rd * o| 0000 | 


7 


IR: 








Q0|001 1 0|w| Rd * 0|0000 


oo|ooi io|w|Rd *o|oooo| 


12 


DA: 








o 1 |oo 1 io|w| oooo|oooo 




SS 


o 1 |oo 1 io|w 


oooo loooo 


16 




address 


segment 


offset 




















SL 


01 |ooi io|w 


000 | 00 






1 segment 


0000 0000 


18 




offset 




X: 
















01 |o 1 1 o| w| Rd*0 | 0000 




SS 


01 |o o 1 io|w 


Rd*0 | 0000 


16 




address 


segment 


offset 




















SL 


o 1 |o o 1 io|w 


Rd*0 |0000 






1 segment 


0000 000 


19 




offset 



















Example: If register Rl contains %2552 (0010010101010010), the statement 

COM Rl 
will leave the value %DAAD (1101 101010101 101). in Rl. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



23 



COMFLG 

Complement Flag 



COMFLG flag Flag: C, Z, S, P, V 

FLAGS (4:7) -«- FLAGS (4:7) XOR instruction (4:7) 



Operation: 



Flags: 



Any combination of the C, Z, S, P or V flags is complemented (each one bit is 
changed to zero, and vice- versa). The flags to be complemented are encoded in a 
field in the instruction. If the bit in the field is one, the corresponding flag is com- 
plemented; if the bit is zero, the flag is left unchanged. Note that the P and V flags 
are represented by the same bit. There may be one, two, three or four operands in 
the assembly language statement, in any order. 

C: Complemented if specified; unaffected otherwise 
Z: Complemented if specified; unaffected otherwise 
S: Complemented if specified; unaffected otherwise 
P/V: Complemented if specified; unaffected otherwise 
D: Unaffected 
H: Undefined 





Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 




Instruction Format 


Cycles 


Instruction Format 


Cycles 




COMFLG flags 




7 








| 10001101 |czsp/v|oioi | 


| 10001101 |czsp/v(oioi | 


7 









Example: 



If the C, Z, and S flags are all clear ( =0), and the P flag is set ( = 1), the statement 

COMFLG P, S, Z, C 
will leave the C, Z, and S flags set ( = 1), and the P flag cleared ( =0). 



24 



CP 

Compare 



CP dst, src 

CPB 

CPL 



dst: R 

src: R, IM, IR, DA, X 

or 

dst: IR, DA, X 

src: IM 



Operation: dst - src 

The source operand is compared to (subtracted from) the destination operand, and 
the appropriate flags set accordingly, which may then be used for arithmetic and 
logical conditional jumps. Both operands are unaffected, with the only action being 
the setting of the flags. Subtraction is performed by adding the two's complement of 
the source operand to the destination operand. There are two variants of this instruc- 
tion: Compare Register compares the contents of a register against an operand 
specified by any of the five basic addressing modes; Compare Immediate performs a 
comparison between an operand in memory and an immediate value. 

Flags: C: Cleared if there is a carry from the most significant bit of the result; set other- 

wise, indicating a "borrow" 

Z: Set if the result is zero; cleared otherwise 

S: Set if the result is negative; cleared otherwise 

V: Set if arithmetic overflow occurs, that is, if both operands were of opposite signs 
and the sign of the result is the same as the sign of the source; cleared otherwise 

D: Unaffected 

H: Unaffected 

Compare Register 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


CP Rd, Rs 
CPB Rbd, Rbs 

CPL RRd, RRs 
CP Rd, #data 

CPB Rbd, #data 

CPL RRd, #data 

CP Rd, @Rsl 
CPB Rbd, @Rsi 

CPL RRd, @Rsi 








4 
8 

7 

7 

14 

7 
14 










1 1 1 1 1 W | Rs | Rd 


1 |00 1 0l|w| Rs | Rd- 


4 












10| 100.00 | Rs | Rd 


10| 10000 | Rs | Rd 


8 


IM: 










00| 001011 |0000| Rd 






| 001011 | | Rd 




7 




data 


data 






















| 001010 


| Rd 






| 001010 


Rd 




7 




data 


data 


data 


data 






















oo| 01 0000 | 0000 | Rd 






1 019000 I I Rd 








31 data (high) i 6 


31 data (high) i6 


14 




15 data (low) 


15 data (low) 




IR: 
















00|0010l|w| Rs*0 | Rd 


|o 1 l| W| Rs*0 | Rd 


7 












| 01 0000 | Rs*0 | Rd 


I 10000 I Rs*0 | Rd 


14 











25 



CP 

Compare 



Source 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycles 



DA: 



CP Rd, address 
CPB Rbd, address 



CPL RRd, address 



CP Rd, addr(Rs) 
CPB Rbd, addr(Rbs) 



CPL RRd, addr(Rs) 



01 00101 W 0000 Rd 



010100000000 Rd 



01001 01 W Rs*0 Rd 



01 010000 Rs^O Rd 



15 



10 



16 



ss 



SL 



SS 



SL 



SS 



SL 



SS 



SL 



0l|0010l|w|0000| Rd 


segment offset 




1 |o 1 oi|w 


I Rd 


1 segment 


0000 0000 


offset 




1 1 01 0000 


I Rd 


segment 


offset 




Oil 01 0000 


00 00 | Rd 


1 segment 


0000 0000 


offset 




01 001 01 1 w 


Rs*o| Rd 


segment 


offset 




1 lo 1 oilw 


Rs*0 | Rd 


1 segment 


0000 0000 


offset 




1 t 1 0000 


Rs*o| Rd 


segment 


offset 




01 | 01 0000 


Rs*0 I Rd 


1 segment 


0000 0000 


offset 



10 



16 



18 



13 



16 



Compare Immediate 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




CP @Rdl , #data 
CPB @Rdl , #data 








11 
11 








IR: 




oo|ooi io|w| Rd*o| 0001 






00]001 1 o|wJRd * | 000 1 


11 




data 


data 




















o oto o 1 1 olw 


Rd*0 | 000 1 






o o|o o 1 1 olw 


Rd*0 ] 00 1 


11 




data 


data 


data 


data 





















26 



CP 

Compare 



Destination 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycle 



DA: 



CP address, #data 



CPB address, #data 



CP addr(Rd), #data 



CPB addr(Rd), #data 



010011 W 0000 0001 



01 


001 1 o|w 


0000 | 0001 


address 




data 






data 



010011 W Rd * 0001 



010011 W Rd*0 0001 



14 



15 



15 



SS 



SL 



SS 



SL 



SS 



SL 



SS 



SL 



o 1 |o o 1 1 o|w 


0000 | 0001 


segment 


offset 


data 



o 1 |o o 1 1 o|w 


ooool 0001 


1 segment 


0000 0000 


offset 


data 



01 |o o 1 1 o|w 


0000 | 1 


segment 


offset 


data 


data 



o 1 |o o 1 1 o|w 


000 | 00 1 


1 segment 


00 0000 


offset 


data - data 



01001 10 W Rd * 0001 



segment 



o 1 |o o 1 1 o|w 


Rd* | 0001 


1 segment 


0000 0000 


offset 


data 



o 1 lo o 1 1 olw 


Rd*0 | 1 


segment 


offset 


data 


data 



o i|ooi 1 o|w 


Rd*0 | 0001 


1 segment 


0000 0000 


offset 


data data 



15 



17 



15 



15 



18 



15 



18 



Example: If register R5 contains %0400, the byte at location %0400 contains 2, and the source 

operand is the immediate value 3, the statement 

CPB @R5,#3 
will leave the C flag set, indicating a borrow, the S flag set, and the Z and V flags 
cleared. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



27 



CPD 

Compare and Decrement 



CPD dst, src ; r, cc 
CPDB 



dst: IR 
src: IR 



Operation: 



Flags: 



dst — src 

AUTODECREMENT src (by 1 if byte, by 2 if word) 

r«- r - 1 

This instruction is<used to search a string of data for an element meeting the 
specified condition. The contents of the location addressed by the source register are 
compared to (subtracted from) the destination operand, and the Z flag is set if the 
condition code specified by "cc" would be set by the comparison; otherwise the Z 
flag is cleared. See list of condition codes. Both operands are unaffected. 

The source register is then decremented by one if CPDB, or by two if CPD, thus 
moving the pointer to the previous element in the strings The word register specified 
by u r" (used as a counter) is then decremented by one. 

C: Undefined 

Z: Set if the condition code generated by the comparison matches cc; cleared 

otherwise 
S: Undefined 

V: Set if the result of decrementing r is zero; cleared otherwise 
D: Unaffected 
H: Unaffected 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


CPD Rd, @R s l, r, cc 
CPDB Rbd,.@Rsl, r, cc 








20 












1 01 1 1 01 |w 


Rs * 


1000 






1 1 1.1 1 | w 


R8 * 


1000 




20 




0000 | r 


Rd *0 


cc 


0000 | r 


Rd * 


cc 



















Example: 



If register RH0 contains %FF, register Rl contains %4001, the byte at location 
%4001 contains %00, and register R3 contains 5, the instruction 

CPDB RH0, @R1, R3, EQ 

will leave the Z flag cleared since the condition code would not have been "equal.' 
Register Rl will contain the value %4000 and R3 will contain 4. For segmented 
mode, Rl must be replaced bv a register pair. 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



28 



CPDR 

Compare Decrement and Repeat 



Operation: 



CPDR dst, src, 


r, cc 




dst: 


IR 




CPDRB 






src: 


IR 




dst - src 












AUTODECREMENT src (by 1 


if byte 


; by 2 if 


word) 


r*- r - 1 












repeat until cc 


is true 


orR = 










Flags: 



This instruction is used to search a string of data for an element meeting the 
specified condition. The contents of the location addressed by the source register are 
compared to (subtracted from) the destination operand, and the Z flag is set if the 
condition code specified by "cc" would be set by the comparison; otherwise the Z 
flag is cleared. See list of condition codes. Both operands are unaffected. 

The source register is then decremented by one if CPDRB, or by two if CPDR, thus 
moving the pointer to the previous element in the string. The word register specified 
"r" (used as a counter) is decremented by one. The entire operation is repeated until 
either the. condition is met or the result of decrementing r is zero. This instruction 
can search a string from 1 to 65536 bytes or 32768 words long (the value of r must 
not be greater than 32768 for CPDR). 

This instruction can be interrupted after each execution of the basic operation. The 
program counter value of the start of this instruction is saved before the interrupt 
request is accepted, so that the instruction can be properly resumed. Seven more 
cycles should be added to this instruction's execution time for each interrupt request 
that is accepted. 

C: Undefined 

Z: Set if the condition code generated by the comparison matches cc; cleared 

otherwise 
S: Undefined 

V: Set if the result of decrementing r is zero; cleared otherwise 
D: Unaffected 
H: Unaffected 



Source 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format Cycles 2 



Segmented Mode 



Instruction Format Cycles 2 



IR: 



CPDRRd, @Rsl, r, cc 
CPDRB Rbd, @Rsl, r, cc 



1 01 1 101 |w 


Rs * 


1 100 


0000| r 


Rd* 


cc 



11 +9n 



101 1 1 01 |w 


Rs * 


1 100 


000 | r 


Rd * 


cc 



Example: If the string of words starting at location %2000 contains the values 0, 2, 4, 6 and 8, 

register R2 contains %2008, R3 contains 3, and R8 contains 8, the instruction 

CPDR R3, @R2, R8, GT 

will leave the Z flag set indicating the condition was met. Register R2 will contain the 
value %2002, R3 will still contain 5, and R8 will contain 5. For segmented mode, a 
register pair would be used instead of R2. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of data elements compared. 



29 



CPI 

Compare and Increment 



CPI dst, src, r, cc 
CPIB 



dst: IR 
src: IR 



Operation: dst - src 

AUTOINCREMENT src (by 1 if byte; by 2 if word) 

r •*- r - 1 



Flags: 



This instruction is used to search a string of data for an element meeting the 
specified condition. The contents of the location addressed by the source register are 
compared to (subtracted irom) the destination operand and the Z flag is set if the 
condition code is specified by "cc" would be set by the comparison; otherwise the Z 
flag is cleared. See list of condition codes. Both operands are unaffected. 

The source register is then incremented by one if CPIB, or by two if CPI, thus 
moving the pointer to the next element in the string. The source, destination, and 
counter registers must be separate and non-overlapping registers. The Word register 
specified by V (used as a counter) is then decremented by one. 

C: Undefined 

Z: Set if the condition code generated by the comparison matches cc; cleared 

otherwise 
S: Undefined 

V: Set if the result of decrementing r is zero; cleared otherwise 
D: Unaffected 
H: Unaffected 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


CPI Rd, @Rsl, r, cc 
CPIBRbd, @Rsl, r, cc 








20 












1011101 |w 


R» * 


0000 






1011101 |w 


Rs * 


0000 




20 




0000 | r 


Rd*0 


cc 


0000| r 


Rd *0 


cc 





















30 



CPI 

Compare and Increment 



Example: 



This instruction can be used in a "loop" of instructions that searches a string of data 
for an element meeting the specified condition, but an intermediate operation on 
each data element is required. The following sequence of instructions (to be 
executed in non-segmented mode) "scans while numeric," that is, a string is 
searched until either an ASCII character not in the range u 0" to "9" (see Appendix 
C) is found, or the end of the string is reached. This involves a range check on each 
character (byte) in the string. For segmented mode, Rl must be changed to a 
register pair. 



LOOP: 



LD 


R3, #STRLEN 


Unitialize counter! 


LDA 


Rl, STRSTART 


!load start address! 


LD 


RL0,f9' 


! largest numeric char! 


CPB 


@Rl,fO' 


!test char < x 0'! 


JR 


ULT,NONNUMERIC 




CPIB 


RLO, @R1, R3, ULT 


Itest char > x 0'! 


JR 


Z, NONNUMERIC 




JR 


NOV, LOOP 


[repeat until counter = 0! 



DONE: 



NONNUMERIC: 



{handle non-numeric char! 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



31 



CPIR 

Compare, Increment and Repeat 



CPIR dst, src, r, cc 
CPIRB 



dst: R 
src: IR 



Operation: 



Flags: 



dst - src 

AUTOINCREMENT src (by 1 if byte; by 2 if word) 

r^-r - 1 

repeat until cc is true or R = 

This instruction is used to search a string of data for an element meeting the 
specified condition. The contents of the location addressed by the source register are 
compared to' (subtracted from) the destination operand, and the Z flag is set if the 
condition code specified by n cc" would be set by the comparison; otherwise the Z 
flag is cleared. See list of condition codes. Both operands are unaffected. 

The source register is then incremented by one if CPIRB, or by two if CPIR, thus 
moving the pointer to the next element in the string. The word register specified by 
"r" (used as a counter) is then decremented by one. The entire operation is repeated 
until either the condition is met or the result of decrementing r is zero. This instruc- 
tion can search a string from 1 to 65536 bytes or 32768 words long (the value of r 
must not be greater than 32768 for CPIR). The source, destination, and counter 
registers must be separate and non-overlapping registers. 

This instruction can be interrupted after each execution of the basic operation. The 
program counter value of the start of this instruction is saved before the interrupt 
request is accepted, so that the instruction can be properly resumed. Seven more 
cycles should be added to this instruction's execution time for each interrupt request 
that is accepted. 

C: Undefined 

Z: Set if the condition code generated by the comparison matches cc; cleared 

otherwise 
S: Undefined 

V: Set if the result of decrementing r is zero; cleared otherwise 
D: Unaffected 
H: Unaffected 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 2 


Instruction Format 


Cycles 2 




CPIR Rd, @Rsl , r, cc 
CPIRB Rbd,@Rsi, r, cc 






11+9n 










IR: 




1011101 |w 


Rs * 


01 00 




1011101 | w 


Rs * 


0100 




11 +9n 




0000 | r 


Rd * 


cc 


0000 | 1 


Rd * 


cc 



















32 



CPIR 

Compare, Increment and Repeat 



Example: The following sequence of instructions (to be executed in nonsegmented mode) can 

be used to search a string for an ASCII return character. The pointer to the start of 
the string is set, the string length is set, the character (byte) to be searched for is 
set, and then the search is accomplished. Testing the Z flag determines whether the 
character was found. For segmented mode, Rl must be changed to a register pair. 

LDA R1,STRSTART 

LD R3, #STRLEN 

LDB RLO, #% D !hex code for return is D! 

CPIRB RL0 ; @R1, R3, EQ 

JR Z, FOUND 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of data elements compared. 



33 



CPSD 

Compare String and Decrement 



CPSD dst ; src, r, cc 
CPSDB 



dst: IR 
src: IR 



Operation: dst - src 

AUTODECREMENT dst and src (by 1 if byte; by 2 if word) 

r «- r - 1 



Flags: 



This instruction can be used to compare two strings of data until the specified condi- 
tion is true. The contents of the location addressed by the source register are com- 
pared to (subtracted from) the contents of the location addressed by the destination 
register. The Z flag is set if the condition code specified by u cc" would be set by the 
comparison; otherwise the Z flag is'cfeared. See list of condition codes. Both ope- 
rands are unaffected. 

The source and destination registers are then decremented by one if CPSDB, or by 
two if CPSD, thus moving the pointers to the previous elements in the strings. The 
word register specified by u r" (used as a counter) is then decremented by one. 

C: Cleard if there is a carry from the most significant bit of the result of the com- 
parison; set otherwise, indicating a "borrow". Thus this flag will be set if the 
destination is less than the source when viewed as unsigned integers. 

Z: Set if the condition code generated by the comparison matches cc; cleared 
otherwise 

S: Set is the result of the comparison is negative; cleared otherwise 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




CPSD<«Rdl, ^Rsl, r, cc 
CPSDB ^Rdi,C«Rsi,r,cc 








25 










IR: 




1011101 |w 


Rs * 


1010 






101 1 101 |w 


Rs * 


1010 




25 




0000 | r 


Rd * 


cc 


0000 | r 


Rd *0 


cc 



















Example: 



If register R2 contains ft /o2000, the byte at location %2000 contains %FF, register R3 
contains %3000, the byte at location %3000 contains %00, and register R4 contains 
1, the instruction (executed in nonsegmented mode) 

CPSDB @R2, @R3, R4, UGE 

will leave the Z flag set to 1 since the condition code would have been "unsigned 
greater than or equal", and the V flag will be set to 1 to indicate that the counter R4 
now contains 0. R2 will contain %1FFF, and R3 will contain %2FFF. For segmented 
mode, R2 and R3 must be changed to register pairs. 



Note 1: Word 



register in nonsegmented mode, register pair in segmented mode. 



34 



CPSDR 

Compare String, Decrement and Repeat 



CPSDR dst, src,r, cc 
CPSDRB 



dst: IR 
src: IR 



Operation: dst -src 

AUTODECREMENT dst and src (by 1 if byte; by 2 if word) 

r -•- r -* 1 

repeat until cc is true or r = 



Flags: 



This instruction is used to compare two strings of data until the specified condition is 
true. The contents of the location addressed by the source register are compared to 
(subtracted from) the contents of the location addressed by the destination register. 
The Z flag is set if the condition code specified by "cc" would be set by the compar- 
ison; otherwise the Z flag is cleared. See list of condition codes. Both operands 
are unaffected. 

The source and destination registers are then decremented by one if CPSDRB* or by 
two if CPSDR, thus moving the pointers to the previous elements in the strings. The 
word register specified by "r" (used as a counter) is then decremented by one. The 
entire operation is repeated until either the condition is met or the result of decre- 
menting r is zero. This instruction can compare strings from 1 to 65536 bytes or from 
1 to 32768 words long (the value of r must not be greater than 32768 for CPSDR). 

This instruction can be interrupted after each execution of the basic operation. The 
program counter of the start of this instruction is saved before the interrupt request 
is accepted, so that the instruction can be properly resumed. Seven more cycles 
should be added to this instruction's execution time for each interrupt request that is 
accepted. 

C: Cleared if there is a carry from the most significant bit of the result of the com- 
parison; set otherwise, indicating a "borrow". Thus this flag will be set if the 
destination is less than the source when viewed as unsigned integers 

Z: Set if the conditon code generated by the Comparison matches cc; cleared 
otherwise 

S: Set if the result of the comparison is negative; cleared otherwise 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycles 



IR: 



CPSDR@Rdl,@Rsl,r,cc 
CPSDRB@Rdi,@Rsi,r,cc 



1 01 1 1 01 |w 


Rs 


1110 


OOOol r 

1, 


Rd 


cc 



1 01 1 1 01 |w 


Rs 


1110 


00 00 | r 


Rd 


cc 



11+14n 



35 



CPSDR 

Compare String, Decrement and Repeat 



Example: If the words from location %1000 to %1006 contain the values 0, 2, 4, and 6, the 

words from location %2000 to %2006 contain the values 0, 1, 1,0, register R13 con- 
tains °/o 1 006 , register R14 contains %2006, and register R0 contains 4, the instruc- 
tion (executed in nonsegmented mode) 

CPSDR @R13, @R14, R0, EQ 

leaves the Z flag set to 1 since the condition code would have been u egual" (loca- 
tions % 1000 and %2000 both contain the value 0). The V flag will be set to 1 indi- 
cating r was decremented to 0. R13 will contain %0FFE, R14 will contain %1FFE, 
and R0 will contain 0. For segmented mode, R13 and R14 must be changed to 
register pairs. 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of data elements compared. 



36 



CPSI 

Compare String and Increment 



CPSI dst, src, r, cc 
CPSIB 



dst: IR 
src: IR 



Operation: dst - src 

AUTOINCREMENT dst and src (by 1 if byte, by 2 if word) 
r •«- r - 1 

This instruction can be used to compare two strings of data until the specified condi- 
tion is true. The contents of the location addressed by the source register are com- 
pared to (subtracted from) the contents of the location addressed by the destination 
register. The Z flag is set if the condition code specified by "cc" would be set by the 
comparison; otherwise the Z flag is cleared. See list of condition codes. Both ope- 
rands are unaffected. 

The source and destination registers are then incremented by one if CPSIB, or by 
two if CPSI, thus moving the pointers to the next elements in the strings. The word 
register specified by X V (used as a counter) is then decremented by one. 

Flags: C: Undefined 

Z: Set if the condition code generated by the comparison matches cc; cleared 

otherwise 
S: Undefined 

V: Set if the result of decrementing r is zero; cleared otherwise 
D: Unaffected 
H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




CPSI (SRdl,@Rsl,r,cc 
CPSIB &Rdi,@Rsl,r,cc 








25 










IR: 




1 01 1 1 01 |w 


Rs * 


0010 






101110 1 |w 


Rs * 


001 








0000 | r 


Rd * 


cc 


0000| r 


Rd * 


cc 


25 



















37 



CPSI 

Compare String and Increment 



Example: 



This instruction can be used in a "loop" of instructions which compares two strings 
until the specified condition is true, but where an intermediate operation on each 
data element is required. The following sequence of instructions, to be executed in 
nonsegmented mode, attempts to match a given source string to the destination 
string which is known to contain all upper-case characters. The match should suc- 
ceed even if the source string contains some lower-case characters. This involves a 
forced conversion of the source string to upper-case (only ASCII alphabetic letters 
are assumed, see Appendix C) by resetting bit 5 of each character (byte) to before 
comparison. 



LOOP: 



DONE: 



LDA 


Rl, SRCSTART 


!load start addresses! 


LDA 


R2, DSTSTART 




LD 


R3, #STRLEN 


Unitialize counter! 


RESB 


@R1,#5 


! force upper-case! 


CFSIB 


@R1,@R2, R3, NE 


Jcompare until not equal! 


JR 


Z, NOTEQUAL 


!exit loop if match fails! 


JR 


NOV, LOOP 


! repeat until counter = 0! 
! match succeeds! 



NOTEQUAL: • ! match fails! 

In segmented mode, Rl and R2 must both be register pairs. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



38 



CPSIR 

Compare String, Increment and Repeat 



CPSIR dst,src,r,cc 
CPSIRB 



dst: IR 
src: IR 



Operation: dst - src 

AUTOINCREMENT dst and src (by 1 if byte, by 2 if word) 

r -*- r - 1 

repeat until cc is true or r = 

This instruction is used to compare two strings of data until the specified condition is 
true. The contents of the location addressed by the source register are compared to 
(subtracted from) the contents of the location addressed by the destination register. 
The Z flag is set if the condition code specified by "cc" would be set by the com- 
parison; otherwise the Z flag is cleared. See list of condition codes. 
Both operands are unaffected. The source and destination registers are then 
incremented by one if CPSIRB, or by two if CPSIR, thus moving the pointers to the 
next elements in the strings. The word register specified by "r" (used as a counter) is 
then decremented by one. The entire operation is repeated until either the condition 
is met or the result of decrementing r is zero. This instruction can compare strings 
from 1 to 65536 bytes or from 1 to 32768 words long (the value of r must not be 
greater than 32768 for CPSIR). 

This instruction can be interrupted after each execution of the basic operation. The 
program counter value of the start of this instruction is saved before the interrupt 
request is accepted, so that the instruction can be properly resumed. Seven cycles 
should be added to this instruction's execution time for each interrupt request that is 
accepted. The source, destination, and counter registers must be separate and non- 
overlapping registers. 

Flags: C: Cleared if there is a carry from the most significant bit of the result of the last 

comparison made; set otherwise, indicating a "borrow". Thus this flag will be set 
if the last destination element is less than the last source element when viewed as 
unsigned integers. 

Z: Set if the condition code generated by the comparison matches cc; cleared 
otherwise 

S: Set if the result of the last comparison made is negative; cleared otherwise 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 2 


Instruction Format 


Cycles 2 




CPSIR fcRdl.&Rsl.r.cc 
CPSIRB <&Rdi,#Rsl,r,cc 








11 + 14n 










IR: 




101 1 101 |w 


Rs*0 


01 10 






101 1 101 |w 


Rs * 


01 10 




11 + 14n 




0000J r 


Rd * 


cc 


0000 | r 


Rd * 


cc 



















39 



CPSIR 

Compare String, Increment and Repeat 



Example: The CPSIR instruction can be used to compare test strings for lexicographic order. 

(For most common character encoding — for example, ASCU and EBCDIC — lexi- 
cographic order is the same as alphabetic order for alphabetic test strings that do 
not contain blanks.) 

Let SI and S2 be text strings of lengths LI and L2. According to lexicographic 
ordering, SI is said to be "less than" or "before" S2 if either of the following is true: 

■ At the- first character position at which SI and 
S2 contain different characters, the character 
code for the SI character is less than the 
character code for the S2 character. 

■ SI is shorter than S2 and is equal, character for 
charaoter, to an initial substring of S2. 

For example, using the ASCII character code, the following strings are ascending 
lexicographic order: 

A 

AU A 
ABC 
A BCD 
A'BD 

Let us assume that the address of SI is in RR2, the address of S2 is in RR4, the 
lengths LI and L2 of SI and S2 are in RO and Rl, and the shorter of LI and L2 is in 
R6. The the following sequence of instructions will determine whether SI is less than 
S2 in lexicographic order: 

!Scan to first unequal character! 

!The following flags settings are possible: 
Z = 0, V = 1: Strings are equal through LI 
character. (Z = 0, V = cannot occur). 
Z = 1 , V = or 1 : A character position was 
found at which the strings are unequal. 
C = 1 (S = or 1): The character in the RR2 
string was less (viewed as numbers from to 
255, not as numbers from -128 to -I- 127). 
C = (S = or 1): The character in the RR2 
string was not less! 

!If Z= 1, compare the characters! 

{Otherwise, compare string lengths! 



CPSIRB @RR2, 9 RR4 ; R6, NE 



_COMPARE 



JR Z,CHAR. 

CP R0,R1 

JR'LT, S1_IS_LESS 
JR Sl_NOT__Less 

CHAR_COMPARE: 
JR ULT, S1_IS_LESS 
Sl_NOT LESS: 



!ULT is another name for C = 1 ! 



S1_IS_LESS: 



40 



DAB 

Decimal Adjust 



DAB dst 



dst: R 



Operation: 



Flags: 



dst '<- DA dst 

The destination byte is adjusted to form two 4-bit BCD digits following an addition or 
subtraction operation. For addition (ADDB ; ADCB) or subtraction (SUBB, SBCB), 
the following table indicates the operation performed: 





Carry 


Bits 4-7 


HFlag 


Bits 0-3 


Number 


Carry 




Before 


Value 


Before 


Value 


Added 


After 


Instruction 


DAB 


(Hex) 


DAB 


(Hex) 


To Byte 


DAB 







0-9 





0-9 


00 










0-8 





A-F 


06 





ADDB 





0-9 


1 


0-3 


06 





ADCB 





A-F 





0-9 


60 


1 







9-F 





A-F 


66 


1 







A-F 


1 


0-3 


66 


1 




1 


0-2 





0-9 


60 


1 




1 


0-2 





A-F 


66 


1 


SUBB 





0-9 





0-9 


00 





SBCB 





0-8 


1 


6-F 


FA 







1 


7-F 





0-9 


A0 


1 




1 


6-F 


1 


6-F 


9A 


1 



The operation is undefined if the destination byte was not the result of a valid addi- 
tion or subtraction of BCD digits. 

C: Set or cleared according to the table above 

Z: Set if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 

V: Unaffected 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


DAB Rbd 




5 






1 1 | 1 1 | Rd | | 


1 1 1 1 1 | Rd | | 


5 









41 



DAB 

Decimal Adjust 



Example: If addition is performed using the BCD values 15 and 27, the result should be 42. 

The sum is incorrect, however, when the binary representations are added in the 
destination location using standard binary arithmetic. 

0001 0101 
+ 0010 0111 



0011 1100 = %3C 
The DAB instruction adjusts this result so that the correct BCD representation is 
obtained. 

0011 1100 
+ 0000 0110 



0100 0010 = 42 



42 



DEC 

Decrement 



DEC dst, src 
DECB 



dst: R, IR, DA, X 
src: IM 



Operation: 



Flags: 



dst -«- dst - src (where src = 1 to 16) 

The source operand (a value from 1 to 16) is subtracted from the destination operand 
and the result is stored in the destination. Subtraction is performed by adding the 
two's complement of the source operand to the destination operand. The source 
operand may be omitted from the assembly language statement and defaults to the 
value 1. 

The value qi the source field in the instruction is one less than the actual value of the 
source operand. Thus, the coding in the instruction for the source ranges from to 
15, which corresponds to the source values 1 to 16. 

C: Unaffected 

Z: Set if the result is zero; cleared otherwise 

S: Set if the result is negative; cleared otherwise 

V: Set if arithmetic overflow occurs, that is, if the operands were of opposite signs, 

and the sign of the result is the same as the sign of the source; cleared otherwise 
D: Unaffected 
H: Unaffected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


DEC Rd, #n 
DECB Rbd, #n 

DEC&Rdi, #n 
DECB &Rdi , #n 

DEC address, #n 
DECB address, #n 

DEC addr(Rd), #n 
DECB addr(Rd), #n 








4 
11 

13 
14 










10|l 01 Oljw| Rd | n - 1 


1 1 1 1 1 1 W | Rd | n - 1 


4 


IR: 








00|l010l|w| Rd*0 | n - 1 


o|l 1 1 1 w| Rd*0 | n - 1 | 


11 












DA: 




0l|l010l|w| 0000 | n - 1 




SS 


0l|l 010l|w 


00 | n - 1 




14 




address 


segment 


offset 






















SL 


0l|l 01 oi|w 


0000| n - 1 








1 segment 


0000 0000 


16 




offset 




















X: 




0l|l010l|w| Rd^O | n - 1 




SS 


01 |l 01 oi|w 


Rd*0,| n - 1 




14 




address 


segment 


offset 






















SL 


01 |l 1 oi|w 


Rd*0 | n - 1 








1 1 ttgment 


0000 00 00 


17 




offset 





















Example: 



If register R10 contains %002A, the statement 

DEC R10 
will leave the value %0029 in R10. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



43 



DI 

Disable Interrupt 



Privileged 



Dllnt 



Int: VI, NVI 



Operation: If instruction (0) = then NVI •*- 

If instruction (1) = then VI -.- 

Any combination of the Vectored Interrupt (VI) or Non- Vectored Interrupt (NVI) 
control bits in the Flags and Control Word (FCW) are cleared to zero if the cor- 
responding bit in the instruction is zero, thus disabling the appropriate type of inter- 
rupt. If the corresponding bit in the instruction is one, the control bit will not be 
affected. All other bits in the FCW are not affected. There may be one or two 
operands in the assembly language statement, in either order. 



Flags: 


No flags affected. 












Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 




Instruction Format 


Cycles 


Instruction Format 


Cycles 




DI int 


1 




7 








01111100 | oooooo | Y | y l 


| 01111100 | oooooo |Y|y| 


7 











Example: If the NVI and VI control bits are set (1) in the FCW, the instruction: 

DI VI 

will leave the NVI control bit in the FCW set (1) and will leave the VI control bit in 
the FCW cleared (0). 



44 



DIV 

Divide 



DIV dst, src dst: R 

DIVL src: R, IM, IR, DA, X 

Operation: Word: (dst is register pair, src is word): 

dst (0:31) is divided by src (0:15) 
(dst (0:31) = quotient x src (0:15) + remainder) 
dst (16:31) «*- quotient 
dst (0:15) •*- remainder 

Lonp;: (dst register quadruple, src is long word or register pair): 
dst (0:63) is divided by src (0:31) 
(dst (0:63) = quotient x src (0:31) + remainder) 
dst (32:63) -+- quotient 
dst (0:31) -+- remainder 

The destination operand (dividend) is divided by the source operand (divisor), the 
quotient is stored in the low-order half of the destination and the remainder is stored 
in the high-order half of the destination. The contents of the source are not affected. 
Both operands are treated as signed, two's complement integers and division is per- 
formed so that the remainder is of the same sign as the dividend. For DIV, the 
destination is a register pair and the source is a word value; for DIVL, the destina- 
tion is a register quadruple and the source is a long word value. 

There a four possible outcomes of the Divide instruction, depending on the division, 
and the resulting quotient: 

CASE 1. If the quotient is within the range -2 15 to 2 15 - 1 inclusive for DIV or 
-2 31 to 2 31 - 1 inclusive for DIVL, then the quotient and remainder are left in the 
destination register as defined above, the overflow and carry flags are cleared to 
zero, and the sign and zero flags are set according to the value of the quotient. 

CASE 2. If the divisor is zero, the destination register remains unchanged, the 
overflow and zero flags are set to one and the carry and sign flags are cleared to 
zero. 

CASE 3. If the quotient is outside the range -2 16 to 2 16 - 1 inclusive for DIV or -2 32 
to 2 32 - 1 inclusive for DIVL, the destination register contains an undefined value, 
the overflow flag is set to one, the carry and zero flags are cleared to zero, and the 
sign flag is undefined. 

CASE 4. If the quotient is inside the range of case 3 but outside the range of case 
1, then all but the sign bit of the quotient and all of the remainder are left in the 
destination register, the overflow and carry flags are set to one, and the sign and 
zero flags are set according to the value of the quotient. In this case, the sign flag 
can be replicated by subsequent instruction into the high-order half of the destina- 
tion to produce the two's complement representation of the quotient in the same 
precision as the original dividend. 

Flags: C: Set if V is set and the quotient lies in the range. from -2 16 to 2 16 - 1 inclusive for 

DIV or in the range from -2 32 to 2 32 - 1 inclusive for DIVL; cleared otherwise 
Z: Set if the quotient or divisor is zero; cleared otherwise 
S: Undefined if V is set and C is clear (overflow); otherwise set if the quotient is 

negative, cleared if the quotient is non-negative. 
V: Set if the divisor is zero or if the computed quotient lies outside the range from 

-2 15 to 2 15 - 1 inclusive for DIV or outside range from -2 31 to 2 31 - 1 inclusive 

for DIVL; cleared otherwise 
D: Unaffected 
H: Unaffected 



45 



DIV 

Divide 



Source 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles? 



Segmented Mode 



Instruction Format 



Cycles2 



DIV RRd, Rs 
DIVL RQd, RRs 
DIV RRd, #data 

DIVL RQd, #data 

DIV RRd, @R S 1 
DIVL RQd, @Rsi 

DIV RRd, address 



DIVL RQD, address 



DIV RRd, addr(Rs) 



DIVL RQd, addr(Rs) 



10 011011 Rs Rd 



10 011010 Rs Rd 



000110110000 Rd 



00 


01 101 | 0000 | 


Rd 


31 


data (high) 


16 


15 


data (low) 






00 011011 Rs*0 Rd 



00 011010 Rs*0 Rd 



010110110000 Rd 



010110100000 Rd 



01 011011 Rs*0 Rd 



01011010 Rs*0 Rd 





10| 01 1 01 1 | Rs 


Rd | 






1 | 1 1 1 | Rs 


Rd | 








| 011011 | 0000 


Rd 




data 










| 01 1 01 | 0000 


Rd 




31 data (high) 


16 




15 data (low) 











00| 011011 | Rs*0 | 


Rd | 






1 01 1 01 | Rs*0 


Rd | 






ss 


-I | 01 1 01 1 


0000 


Rd 


segment 


offset 










01 j 011011 


0000 


Rd 


SL 


1 segment 


0000 


0000 




offset 








SS 


1 1 011010 


0000 


Rd 


segment 


offset 










1 1 0110 10 


0000 


Rd 


SL 


1 segment 


0000 


0000 




offset 








SS 


0l| 011011 


Rs*0 


Rd 


segment 


offset 










1 1 011011 


Rs*0 


Rd 


SL 


1 segment 


0000 


0000 




offset 








SS 


0l| 011010 


Rs*0 


Rd 


segment 


offset 








1 1 011010 


Rs*0 


Rd 


SL 


1 segment 


0000 


0000 




offset 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: Execution times for each instruction are given in the table under Example. 



46 



DIV 

Divide 



Example: The following table gives the DIV instruction execution times for word and long 

word operands in all possible addressing modes. 



src 




Word 




Long Word 






NS 


SS 


SL 


NS 


SS 


SL 


R 


107 


— 


— 


744 


— 


— 


IM 


107 


— 


— 


744 


— 


— 


IR 


107 


107 


107 


744 


744 


744 


DA 


108 


108 


111 


745 


746 


748 


X 


109 


109 


112 


746 


746 


749 


(Divisor is 


zero) 












R 


13 


13 


13 


30 


30 


30 


IM 


13 


13 


13 


30 


30 


30 


IR 


13 


13 


13 


30 


30 


30 


DA 


14 


15 


17 


31 


32 


34 


X 


15 


15 


18 


32 


32 


35 


(Absolute value of the high-order half of the dividend 


is larger than the 


absolute value of the divisor) 










R 


25 


25 


25 


51 


51 


51 


IM 


25 


25 


25 


51 


51 


51 


IR 


25 


25 


25 


51 


51 


51 


DA 


26 


27 


29 


52 


53 


55 


X 


27 


27 


30 


53 


53 


56 



Note that for proper execution, the "dst field" in the instruction format encoding 
must be even for DIV, and must be a multiple of 4 (0, 4, 8, 12) for DIVL. If the 
source operand in DIVL is a register, the u src field" must be even. 

If register RR0 (composed of word register. R0 and Rl) contains %00000022 and 
register R3 contains 6, the statement 

DIV RR0,R3 
will leave the value %00040005 in RR0 (Rl contains the quotient 5 and R0 contains 
the remainder 4). 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 

Note 2: The execution time for the instruction will be lower than indicated for divide by zero and certain 
overflow conditions. 



47 



DJNZ 

Decrement and Jump if Not Zero 



DJNZ R, dst 
DBJNZ 



dst: RA 



Operation: 



R «■- R - 1 

If R * then PC ■ 



PC - (2 x displacement) 



The register being used as a counter is decremented. If the contents of the register 
are not zero after decrementing, the destination address is calculated and then 
loaded into the program counter (PC). Control will then pass to the instruction 
whose address is pointed to by the PC. When the register counter reaches zero, con- 
trol falls through to the instruction following DJNZ or DBJNZ. This instruction pro- 
vides a simple method of loop control. 

The relative addressing mode is calculated by doubling the displacement in the 
instruction, then subtracting this value from the updated value of the PC to derive 
the destinatiop address. The updated PC value is taken to be the address of the 
instruction byte following the DJNZ or DBJNZ instruction, while the displacement is a 
7-bit positive value in the range to 127. Thus, the destination address must be in 
the range -252 to 2 bytes from the start of the DJNZ or DBJNZ instruction. In the 
segmented mode, the PC segment number is not affected. The assembler automatic- 
ally calculates the displacement by subtracting the PC value of the following instruc- 
tion from the address given by the programmer. Note that DJNZ or DBJNZ cannot be 
used to transfer control in the forward direction, nor to another segment in 
segmented mode operation. 



Flags: 


No flags affected 










Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




DJNZ R, displacement 
DBJNZ Rb, displacement 






11 






RA: 


1 1 1 1 | r | w] disp | 


| 1 1 1 1 | r |w| disp | 


11 











Example: 



DJNZ and DBJNZ are typically used to control a "loop" of instructions. In this exam- 
ple for nonsegmented mode, 100 bytes are moved from one buffer area to another, 
and the sign bit of each byte is cleared to zero. Register RHO is used as the counter. 

iinitalize counter! 
Iload start address! 



LOOP: 



LDB 


RHO, #100 


LDA 


Rl, SRCBUF 


LDA 


R2, DSTBUF 


LDB 


RL0,@R1 


RESB 


RL0,#7 


LDB 


@R2, RLO 


INC 


Rl 


INC 


R2 


DBJNZ 


RHO, LOOP 



NEXT: 



!load source byte! 
!mask off sign bit! 
! store into destination! 
! advance pointers! 

•repeat until counter = 0! 



For segmented mode, Rl and R2 must be changed for register pairs. 



Privileged 



EI 

Enable Interrupts 



EI int 



Int: VI, NVI 



Operation: 



If instruction (0) = then NVI -*- 1 
If instruction (1) = then VI <«- 1 



Any combination of the Vectored Interrupt (VI) or Non-Vetored Interrupt (NVI) con- 
trol bits in, the Flags and Control Word (FCW) are set to one if the corresponding bit 
in the instruction is zero, thus enabling the appropriate type of interrupt. If the cor- 
responding bit in the instruction is one, the control bit will not be affected. All other 
bits in the FCW are not affected. There may be one or two operands in the assembly 
language statement, in either order. 



Flags: 


No flags affected 












Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 




Instruction Format 


Cycles 


Instruction Format 


Cycles 




EI int 


1 




7 








01111100 | 000001 |y|y| 


| 01111100 | 000001 |y|y| 


7 



Example: 



If the NVI contol bit is set (1) in the FCW, and the VI control bit is clear (0), the 
instruction 

EI VI 

will leave both the NVI and VI control bits in the FCW set (1) 



49 



EX 

Exchange 



EX dst, src 
EXB 



dst: R 

src: R, IR, DA, X 



Operation: tmp -*- src (tmp is a temporary internal register) 

src *«- dst 

dst ■*- tmp 

The contents of the source operand are exchanged with the contents of the destina- 
tion operand. 

Flags: No flags affected 



Source 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycles 



R: 
IR: 
DA: 



X: 



EX Rd, Rs 
EXB Rbd, Rbs 



EX Rd, @R s l 
EXB Rbd, @Rsi 



EX Rd, address 
EXB Rbd, address 



1010110 W Rs Rd 



00 101 1 W Rs*0 Rd 



01 10110 W 0000 Rd 



6 
12 

15 



EX Rd, addr(Rs) 
EXB Rbd, addr(Rs) 



011011 W Rs*0 Rd 



16 





1 |l 1 1 o| w| Rs | Rd | 




Oo]l011o|w|Rs*o| Rd 




ss 


o 1 1 1 o 1 1 o|w 


000 | Rd 


segment 


offset 








o 1 |i o 1 io|w 


000 | Rd 


SL 


1 segment 


0000 0000 




offset 






SS 


oi|i 01 1 o|w 


Rs*0 | Rd 


segment 


offset 








01 |i 01 1 o|w 


Rs*0 | Rd 


SL 


1 segment 


0000 0000 




offset 



12 



16 



18 



16 



19 



Example: If register R0 contains 8 and register R5 contains 9, the statement 

EX R0,R5 
will leave the values 9 in R0, and 8 in R5. The flags will be left unchanged. 

Note l: Word register in nonsegmented mode, register pair in segmented mode. 



50 



EXTS 

Extend Sign 



EXTSB dst 

EXTS 

EXTSL 



dst: R 



Operation: 



Byte 

if dst (7) = then dst (8:15) «- 000... 000 
else dst (8:15) *- 111. ..Ill 

Word 

if dst (15) = then dst (16:31) +- 000.. .000 

else dst (16:31) +- 111. ..Ill 
Long 
if dst (31) ?= then dst (32:63) *- 000.. .000 

else dst (32:63) — 111. ..Ill 

The sign bit of the low-order half of the destination operand is copied into all bit 
positions of the high-order half of the destination. For EXTS, the destination is a 
register pair; for EXTSL, the destination is a register guadruple. 

This instruction is useful in multiple precision arithmetic or for conversion of small 
signed operands to larger signed operands (as,. for example, before a divide). 



Example: 



Flags: 


No flags affected 








Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


EXTSB Rd 
EXTS RRD 
EXTSL RQd 




11 
11 
11 






|l o| 1 10001 | Rd | 0000| 


|lo| 1 10001 | Rd | 0000 | 


11 












|l 1 10001 | Rd | 1 1 | 


|l 1 10001 | Rd | 1 010 | 


11 










|l o| 1 1000 1 | Rd | 01 1 1 | 


|l o| 1 10001 | Rd | 01 1 1 | 


11 











If register pair RR2 (composed of word registers R2 and R3) contains % 12345678, 
the statement 

EXTS. RR2 

will leave the value %00005678 in RR2 (because the sign bit of R3 was 0). 



51 



HALT 

Halt 



Privileged 



Operation: The CPU operation is suspended until an interrupt or reset request is received. This 

instruction is used to synchronize the Z8000 with external events, preserving its state 
until an interrupt or reset request is honored. After an interrupt is serviced, the 
instruction follo wing HA LT is executed. While halted, memory refresh cycles will 
still occur, and BUSREQ will be honored. 

Flags: No flags affected 





Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 




Instruction Format 


Cycles 1 


Instruction Format 


Cycles 1 




HALT 




8 + 3n 








| 01111010 | 00000000 | 


| 01111010 | 00000000 | 


8 + 3n 



Note 1: Interrupts are recognized at the end of each'3-cycle period; thus n = number of periods without 
interruption. 



52 



Privileged 



IN (SIN) 

(Special) Input 



IN dst, src 
INB 

SIN dst, src 
SINB 



dst: R 

src: ffi, DA 

dst: R 
src: DA 



Operation dst -«- src 

The contents of the source operand, an Input or Special Input port, are loaded into 
the destination register. IN and INB are used for normal I/O operation; SIN and 
SINB are used for Special I/O operation. 

Flags: No flags affected 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


IN Rdi, @Rs 
INB Rbdi, @Rs 

IN Rd, port 
INB Rbd, port 

SIN Rd, port 
SINB Rbd, port 








10 
12 










00|l1110|w| Rs | Rd 


00|l1110|w| Rs | Rd 


10 


DA: 










00|l110l|w| Rd | 1 OS 






00|l110l|w| Rd | 1 OS 




12 




port 


port 



















Example: 



If register R6 contains the I/O port address %0123 and the port %0123 contains 
%FF, the statement 

INB RH2, @R6 

will leave the value %FF in register RH2. 



Note 1. Word register in nonsegmented mode; register pair in segmented mode. 



53 



INC 

Increment 



INC dst, src 
INCB 



dst: R, IR, DA, X 
src: IM 



Operation: 



dst •*- dst + src (src = 1 to 16) 



Flags: 



The source operand (a value from 1 to 16) is added to the destination operand and 
the sum is stored in the destination. Two's complement addition is performed. The 
source operand may be omitted from the assembly language statement and defaults 
to the value 1 . 

The value of the source field in the instruction is one less than the actual value of the 
source operand . Thus, the coding in the instruction for the source ranges from 
to 15, which corresponds to the source values 1 to 16. 

C: Unaffected 

Z: Set if the result is zero; cleared otherwise 

S: Set if the result is negative; cleared otherwise 

V: Set if arithmetic overflow occurs, that is, if both operands were of the same sign 

and the result is of the opposite sign; cleared otherwise 
D: Unaffected 
H: Unaffected 



Addressing 
Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycle 



Segmented Mode 



Instruction Format 



Cycles 



R: 

IR: 

DA: 



X: 



INC Rd, #n 
INCB Rbd, #n 

INC @Rdi , #n 
INCB@Rdl, #n 

INC address, #n 
INCB address, #n 



R 


10100 


|w 


Rd 


n - 


' 




|oo 


10100 


« 


Rd*0 


„- 


i 




., 


10100 


w 


0000 


n - 


1 


address 



11 



13 



INC addr(Rd), #n 
INCB addr(Rd), #n 



01 10100 W Rd*0 n • 



14 





|l o|l 01 00|w| Rd | n - 1 | 




00|l 010o|w| Rd*0 | n - 1 | 




SR 


oi|ioioo|w 


0000 | n - 1 




segment 


offset 








oi|ioioo|w 


0000 | n - 1 


SL 


1 | segment 


0000 0000 




offset 






SS 


oi|ioioo|w 


Rd*0 | n - 1 


J segment 


offset 








oi|ioioo|w 


Rd*0 | n - 1 


SL 


1 segment 


0000 0000 




offset 



14 



16 



17 



Example: If register RH2 contains %21, the statement 

INCB RH2,#6 
will leave the value %27 in RH2. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



54 



Privileged IND (SIND) 

(Special) Input and Decrement 



IND dst, src, r 
INDB 
SIND 
SINDB 



dst: IR 
src: IR 



Operation: dst ■+- src 

AUTODECREMENT dst (by 1 byte, by 2 if word) 

r «*- r - 1 



Flags: 



This instruction is used for block input of strings of data. IND and INDB are used for 
normal I/O operation; SIND and SINDB are used for special I/O operation. The con- 
tents of tHe I/O port addressed by the source word register are loaded into the 
memory location addressed by the destination register. I/O port addresses are 16 
bits. The destination register is then decremented by one if a byte instruction or by 
two if a word instruction, thus moving the pointer to the previous element of the 
string in memory. The word register specified by u r" (used as a counter) is then 
decremented by one. The address of the I/O port in the source register is 
unchanged. 

C: Unaffected 

Z: Unaffected 

S: Unaffected 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




IND @Rdl, <L»Rs,r 
INDBSRdi, <&Rs, r 
SIND&Rdi, @Rs, r 
SINDB <&>Rdl, <&Rs, r 








21 










IR: 




001 1 101 |w 


Rs * 


OOOS 






001 1 101 |w 


Rs * 


OOOS 




21 




0000J r 


Rd * 


1000 


OOOol r 


Rd *0 


1000 



















Example: 



In segmented mode, if register RR4 contains %02004000 (segment 2, offset %4000), 
register R6 contains the I/O port address %0228, the port % 0228 contains %05B9, 
and register R0 contains %0016, the instruction 

IND @RR4, @R6, R0 

will leave the value %05B9 in location %02004000, the value %02003FFE in RR4, 
and the value %0015 in R0. The V flag will be cleared. Register R6 still contains the 
value %0228. In nonsegmented mode, a word register would be used instead of 
RR4. 



Note 1 : Word register in nonsegmented mode, register pair in segmented mode. 



55 



INDR (SINDR) Privileged 

(Special) Input, Decrement and Repeat 



Operation: 



Flags: 



INDR dst, src, r 


dst: IR 


INDRB 


src: IR 


SINDR 




SINDRB 




dst **- src 




AUTODECREMEN r 


1 dst (by 1 if byte, by 2 if word) 


r -*- r - 1 




repeat until r = 





This instruction is used for block input of strings of data. INDR and INDRB are used 
for normal I/O operation; SINDR and SINDRB are used for special I/O operation. 
The contents of the I/O port addressed by the source word register are loaded into 
the memory location addressed by the destination register. I/O port addresses are 16 
bits. The destination register is then decremented by one if a byte instruction, or by 
two if a word instruction, thus moving the pointer to the previous element of the 
string in memory. The word register specified by u r" (used as a counter) is then 
decremented by one. The address of the I/O port in the source register is 
unchanged. The entire operation is repeated until the result of decrementing r is 
zero. This instruction can input from 1 to 65536 bytes or 32768 words (the value for r 
must not be greater than 32768 for INDR or SINDR). 

This instruction can be interrupted after each execution of the basic operation. The 
program counter value of the start of this instruction is saved before the interrupt 
reguest is accepted, so that the instruction can be properly resumed. Seven more 
cycles should be added to this instruction's execution time for each interrupt reguest 
that is accepted. 

C: Unaffected 
Z: Undefined 
S: Unaffected 
V: Set 

D: Unaffected 
H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 2 


Instruction Format 


Cycles 2 


IR: 


INDR @Rdl , @Rs, r 
INDRB @Rdi , @Rs, r 
SINDR @Rdi, @Rs, r 
SINDRB @Rdi, @Rs, r 








11+10n 












0011101 |w 


Rs*0 


100S 






0011 101 |w 


Rs*0 


100S 




11+10n 




oooo| r 


Rd*0 


0000 


0000 | r 


Rd*0 


0000 





















56 



Privileged INDR (SINDR) 

(Special) Input, Decrement and Repeat 



Example: If register Rl contains %202A, register R2 contains the Special I/O address %0AFC, 

and register R3 contains 8, the instruction 

SINDRB @R1, @R2, R3 

will input 8 bytes from the special I/O port OAFC and leave them in descending 
order from %202A to %2023. Register Rl will contain /o2022, and R3 will contain 0. 
R2 wil) not be affected. The V flag will be set. This example assumes nonsegmented 
mode; in segmented mode, Rl would be replaced by a register pair. 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of data elements transferred. 



57 



INI (SINI) Privileged 

(Special) Input and Increment 



INI dst, src, r 

INIB 

SINI 

SINIB 



dst: IR 
src: IR 



Operation: dst «*- src 

AUTOINCREMENT dst (by 1 if byte, by 2 if word) 

r -«- r - 1 



Flags: 



This instruction is used for block input of strings of data. INI, INIB are used for nor- 
mal I/O operation; SINI, SINIB are used for special I/O operation. The contents of 
the I/O port addressed by the source word register are loaded into the memory loca- 
tion addressed by the destination register. I/O port addresses are 16 bits. The 
destination register is then incremented by one if a byte instruction, or by two if a 
word instruction, thus moving the pointer to the next element of the string in 
memory. The word register specified by V (used as a counter) is then decremented 
by one. The address of the I/O port in the source register is unchanged. 

C: Unaffected 

Z: Undefined 

S: Unaffected 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


INI @Rdi, @Rs, r 
INIB @Rdl, @Rs, r 
SINI@Rdl, @Rs, r 
SINIB @Rdl, @Rs, r 








21 












001 1 101 |w 


Rs * 


100S 






0011101 |w 


Rs * 


100S 




21 




0000 | r 


Rd * 


1000 


0000| r 


Rd * 


1000 





















Example: 



In nonsegmented mode, if register R4 contains %4000, register R6 contains the I/O 
port address %0229, the port %0229 contains %B9, and register R0 contains %0016, 
the instruction 

INIB @R4, @R6, R0 

will leave the value °/oB9 in location %4000, the value %4001 in R4, and the value 
%0015 in R0. Register R6 still contains the value %0229. The V flag is cleared. In 
segmented mode, R4 would be replaced by a register pair. 



Note 1 : Word register in nonsegmented mode, register pair in segmented mode. 



58 



Privileged INIR (SINIR) 

(Special) Input, Increment and Repeat 



Operation: 



INIR dst, src, r 
INIRB 
SINIR 
SINIRB 




dst: IR 
src: IR 


dst ^— src 

AUTOINCREMENT dst (by ] 
r •*- r — 1 
repeat until r = 0, 


if byte, by 2 if word) 



Flags: 



This instruction is used for block input of strings of data. INIR and INIRB are used 
for normal I/O operation; SINIR and SINIRB are used for special I/O operation. The 
contents of the I/O port addressed by the source word register are loaded into the 
memory location addressed by the destination register. I/O port addresses are 16 
bits. The destination register is then incremented by one if a byte instruction, or by 
two if a word instruction, thus moving the pointer to the next element in the string. 
The word register specified by n r" (used as a counter) is then decremented by one. 
The address of the I/O port in the source register is unchanged. The entire operation 
is repeated until the result of decrementing r is zero. This instruction can input from 
1 to 65536 bytes or 32768 words (the value for r must not be greater than 32768 for 
INIR or SINIR). 

This instruction can be interrupted after each execution of the basic operation. The 
program counter value of the start of this instruction is saved before the interrupt 
request is accepted, so that the instruction can be properly resumed. Seven more 
cycles should be added to this instruction's execution time for each interrupt request 
that is accepted. 

C: Unaffected 
Z: Unaffected 
S: Unaffected 
V: Set 

D: Unaffected 
H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


INIR @Rdi, @Rs, r 
INIRB @Rdl , @Rs, r 
SINIR @Rdl , @Rs, r 
SINIRB @Rdi , @Rs, r 








11 + 10n 












001 1101 |w 


Rs*0 


OOOS 






0011 101 |w|rs*o 


OOOS 




11+10n 




0000| r 


Rd*0 


0000 


000 1 r 


Rd *0 


0000 





















59 



INIR (SINIR) Privileged 

(Special) Input, Increment and Repeat 



Example: In nonsegmented mode, if register Rl contains %2023, register R2 contains the I/O 

port address %0551, and register R3 contains 8, the statement 

INIRB @R1, @R2, R3 

will input 8 bytes from port %0051 and leave them in ascending order from %2023 
to %202A. Register Rl will contain 0/02026, and R3 will contain 0. R2 will not be 
affected. The V flag will be set. In segmented mode, a register pair must be used 
instead of Rl. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of data elements transferred. 



60 



Privileged 



IRET 

Interrupt Return 



IRET 



Operation: Nonsegmented 

SP +- SP + 2 (Pop "identifier") 

PS «*- @SP 
SP ^ SP + 4 



Segmented 

SP +- SP + 2 (Pop "identifier" 

PS «*- @SP 
SP -•- SP + 6 



Flags: 



This instruction is used to return to a previously executed procedure at the end of a 
procedure entered by an interrupt or trap (including a System Call instruction). 
First, the "identifier" word associated with the interrupt or trap is popped from the 
system processor stack and discarded. Then contents of the location addressed by 
the system processor stack pointer are popped into the program status (PS), loading 
the Flags and Control Word (FCW) and the program counter (PC). The new value 
of the FCW is not effective until the next instruction, so that the status pins will not 
be affected by the new control bits until after the IRET instruction execution is com- 
pleted. The next instruction executed is that addressed by the new contents of the 
PC. The system stack pointer (R15 if nonsegmented, or RR14 if segmented) is used to 
access memory. When using a Z8001, the operation of IRET in nonsegmented mode 
is undefined. A Z8001 must be in segmented mode when an IRET instruction is 
performed. 

C: Loaded from processor stack 
Z: Loaded from processor stack 
S: Loaded from processor stack 
P/V: Loaded from processor stack 
D: Loaded from processor stack 
H: Loaded from processor stack 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




IRET 




13 








| 01111011 | 00000000 | 


| 01111011 | oooooooo | 


16 









Example: 



In the nonsegmented Z8002 version, if the program counter contains %2550, the 
system stack pointer (R15) contains %3000, and locations %3000, %3002 and %3004 
contain %7F03, a saved FCW value, and %1004, respectively, the instruction 

IRET 

will leave the value %3006 in the system stack pointer and the program counter will 
contain %1004, the address of the next instruction to be executed. The program 
status will be determined by the saved FCW value. 



61 



IP 

Jump 



JP cc, dst 



dst: IR, DA, X 



Operation: If cc is satisfied, then PC «•- dst 

A conditional jump transfers program control to the destination address if the 
condition specified by w cc" is satisfied by the flags in the FCW. See list of condi- 
tion codes. If the condition is satisfied, the program counter (PC) is loaded with 
the designated address; otherwise, the instruction following the IP instruction is 
executed. 



Flags: 



No flags affected 



Example: 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 2 


Instruction Format 


Cycles 2 


IR: 


JP cc, @Rdl 
JP cc, address 

JP cc, addr(Rd) 








10/7 
7/7 

8/8 








0| 01 11 10 | Rd*0 | cc 


00| 01 1 1 10 | Rd*0 | cc | 


15/7 


DA: 








0l| 011110 | 0.0 | cc 




SS 


1 1 011110 


cc 


8/8 




address 


1 segment 


offset 






















SL 


1 ( 011110 


cc 






1 segment 


0000 0000 


10/10 




offset 




X: 
















01 1 01 11 10 | Rd*0 | cc 




SS 


01 1 011110 


Rd*0 J cc 


11/11 




address 




1 segment 


offset 




















SL 


1 1 011110 


Rd*0 | cc 






1 1 segment 


0000 0000 


11/11 




offset 



















If the carry flag is set, the statement 

JP C, %1520 

replaces the contents of the program counter with %1520, thus transferring control 
to that location. 



Note 1 : Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: The two values correspond to jump taken and jump not taken. 



62 



JR 

Jump Relative 



JR cc, dst 



dst: RA 



Operation: 



Flags: 



if cc is satisfied then PC ■*- PC + (2 x displacement) 

A conditional jump transfers program control to the destination address if the condi- 
tion. specified by "cc" is satisfied by the flags in the FCW. See list of condition codes. 
If the condition is satisfied, the program counter (PC) is loaded 

with the designated address; otherwise, the instruction following the JR instruction is 
executed. The destination address is calculated by doubling the displacement in the 
instruction, then adding this value to the updated value of the PC to derive the 
destination address. The updated PC value is taken to be the address of the instruc- 
tion byte following the JR instruction, while the displacement is an 8-bit signed value 
in the range -128 to + 127. Thus, the destination address must be in the range -254 
to +256 bytes from the start of the JR instruction. In the segmented mode, the PC 
segment number is not affected. 

The assembler automatically calculates the displacement by subtracting the PC value 
of the following instruction from the address given by the programmer. 

No flags affected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


RA: 


JR cc, address 




6 






1 1 1 1 cc displacement I 


1110 cc displacement 


6 



Example: 



If the result of the last arithmetic operation executed is negative, the following four 
instructions (which occupy a total of twelve bytes) are to be skipped. This can be 
accomplished with the instruction 

JR MI, $ +14 
If the S flag is not set, execution continues with the instruction following the JR. 
A byte-saving form of a jump to the label LAB is 

JR LAB 

where LAB must be within the allowed range. The condition code is "blank" in this 
case, and indicates that the jump, is always taken. 



63 



LD 

Load 



LD dst, src 

LDB 

LDL 



Operation: 



dst: R 

src: R, IR, DA, X, BA, BX 



dst: IR, DA, X, BA, BX 

src: R 

or 

dst: R, IR, DA, X 

src: IM 



dst •*- src 

The contents of the source are loaded into the destination. The contents of the source 
are not affected. 

There are three versions of the Load instruction: Load into a register, load into 
memory and load an immediate value. 



Flags: 



No flags affected 



Load Register 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


LD Rd, Rs 
LDB Rbd, Rbs 

LDL RRd, RRs 

LD Rd, @Rsi 
LDB Rbd, @Rsi 

LDL RRd, @Rsi 

LD Rd, address 
LDB Rbd, address 

' LDL RRd, address 








3 
5 
7 
11 

9 
12 








10|l0000|w| Rs | Rd 


10|l0000|w| Rs | Rd | 


3 












1 o| 10100 | RRs | RRd 


1 o| 01 01 00 | RRs | RRd | 


5 


IR: 








00|l0000| W | Rs*0 | Rd 


00|l 0000| W | Rs*0 | Rd | 


7 












00| 01 01 00 | Rs*0 | RRd 


00| 010100 | Rs*0 | RRd | 


11 


DA: 










0l|l 0000|w| 0000 | Rd 




SS 


oi|i oooo|w 


| Rd 


10 




address 


segment 


offset 






















SL 


o 1 1 1 oooo|w 


0000 | Rd 






1 segment 


0000 0000 


12 




offset 






















1 1 01010-0 | 000 | RRd 




SS 


1 1 01 01 00 


00 I RRd 


13 




address 


segment 


offset 




















SL 


0l| 01 01 00 


00 | RRd 






1 segment 


0000 0000 


15 




offset 















Note 1 : Word register in nonsegmented mode, register pair in segmented mode. 



64 



LD 

Load 



Load Register (Continued) 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




LD Rd, addr(Rs) 
LDB Rbd, addr(Rs) 

LDL RRd, addr(Rs) 

LD Rd, Rsi(#disp) 
LDB Rbd, Rsl(#disp) 

LDL RRd, Rsl(#disp) 

LDRd, Rsl(Rx) 
LDBRd, Rsi(Rx) 

LDL RRd, Rsi(Rx) 








10 

13 

14 
17 

14 
17 








X: 




0l| 1 0000|w| Rs*0 | Rd 




SS 


o 1 1 1 oooolw 


Rs*0 | Rd 


10 




address 


segment 


offset 




















SL 


o 1 1 1 oooo|w 


Rs*0 Rd 






1 segment 


0000 0000 


13 




offset 






















1 1 010100 | Rs*0 | RRd 




SS 


01 I 010100 


Rs*0 | RRd 


13 




address 


segment 


offset 




















SL 


Oil 010100 


Rs*0 | RRd 






1 segment 


0000 0000 


16 




offset 


















BA: 




o| 1 1 000 |w| Rs*0 | Rd 






o| 1 1 000|w| Rs*0 Rd 


14 




displacement 


displacement 




















00| 1 1 01 01 | Rs*0 | Rd 






00| 110 10 1 | Rs*0 Rd 


17 




displacement 


displacement 


BX: 
















oih iooo|w 


Rs*0 Rd 






1 1 1 1 Q I.W 


Rs*0 | Rd 


14 




| Rx 


0000 0000 


00 00 | Rx 


0000 0000 




















1 1 1 1 01 o| 1 


Rs*0 | Rd 






1 1 1 1 01 o| 1 


Rs*0 | Rd 


17 




00 | Rx 


0000 0000 


| Rx 


0000 0000 

















Load Memory 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




LD @Rdi , Rs 
LDB@Rdi, Rbs 

LDL@Rdi, RRs 




8 
11 






IR: 


|oo|ioi 1 i|w|rci*o[ Rs | 


|00|l01 1 1 | W | Rd * o| Rs | 


8 












1 1 1 1 101 |r<j * o| RRs | 


| 1 1 1 1 1 | Rd * o| RRs | 


11 









Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



65 



LD 

Load 

Load Memory (Continued) 



Destination 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycle 



Segmented Mode 



Instruction Format 



DA: 



DA: 



BA: 



BX: 



LD address, Rs 
LDB address, Rbs. 



LDL address, RRs 



LD addr(Rd), Rs 
LDB addr(Rd), Rbs 



LDR addr(Rd), RRs 



LDRdi(#disp), Rs 
LDBRdi(#disp), Rbs 

LDLRdi(#disp), RRs 



LDRdi(Rx), Rs 
LDBRdi(Rx), Rbs 



LDLRdi(Rx), RRs 



01 10111 W 0000 Rs 



0101110 10 RRs 



01101 1 1 W Rd*0 Rs 



01 011101 Rd*0 RRs 



00 1 1 001 W Rd*0 Rs 



displacement 



00110111 Rd*0 RRs 



displacement 



1 1 1 iooi|w 


Rd*0 | Rs 


| Rx 


0000 0000 



01 110111 



Rd*0 RRs 



14 



12 



15 



14 



17 



14 



17 



ss 


0l|l01 1 i|w 


00 00 | Rs 


segment 


offset 








1 1 1 1 1 1 1 w 


| Rs 


SL 


1 segment 


0000 00 




offset 






SS 


0l| 011101 


00 00 RRs 


segment 


offset 








0l| 011101 


00 00 | RRs 


SL 


1 segment 


0000 0000 




offset 






SS 


1 1 1 1 1 1 |w 


Rd*0 Rs 


segment 


offset 








1 1 1 1 1 i|w 


Rd*0 Rs 


SL 


1 I segment 


i 0000 0000 




offset 






SS 


0l| 011101 


Rd*0 | RRs 


segment 


offset 








0l| 011101 


Rd*0 | RRs 


SL 


1 segment 


0000 0000 




offset 








00|l 1 1 1 w| Rd*0 | Rs 




displacement 








00| 1 1 01 1 1 Rd*o | RRs 




displacement 








l|l 1 o i|w 


Rd>0 Rs 




| Rx 


0000 0000 








01] 1101 11 


Rd*0 I RRs 




| Rx 


000 00 00 



Note 1 : Word register in nonsegmented mode, register pair in segmented mode 



66 



LD 

Load 



Load Immediate Value 



Destination 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycles 



LD Rd, #data 



LDB Rbd, #data2 



LDL RRd, #data 



LD @Rdl , #data 



LDB@Rdi,#data 



LD address, #data 



LDB address, #data 



00 


100001 joooo 


Rd 


data 




To] 


100000 


0000 


Rd 


data 


data 




1" 


00 | Rd | data 




00 


010100 |oooo 


RRd 


31 


data (high) 


16 


15 


data (low) 







00 


01101 | Rd * 


0101 


data 




00 


001 100 


Rd *0 


0101 


data 


data 




1] 


001101 I 0000 


0101 


address 


data 



01001100 00000101 



11 



11 



14 



14 





| 100001 | | Rd 




data 








ool 1 00000 


| Rd 




data 


data 






| 1100 | Rd | data 






0| 010100 | 000 | RRd 




31 data (high) 16 




15 data (low) rj 








00| 001 101 | Rd * o| 0101 




data 








oo| 001 100 


Rd*0|0101 




data 


data 








Oil 001101 


ooool 01 01 


ss 


segment 


offset 




data 








Oil 001 1 01 


oooo| 01 01 


SL 


1 segment 


0000 0000 


offset 




data 








Oil 001100 


oooo| 0101 


SS 


segment 


offset 




data 


data 






Oil 001100 


0000I01 01 




1 segment 


0000 0000 




offset 




data data 



11 



11 



11 



15 



17 



15 



17 



Note 1 : Word register in nonsegmented mode, register pair in segmented mode. 

Note 2: Although two formats exist for "LDB R, IM", the assembler always uses the short format. In this case, the 
"src field" in the instruction format encoding contains the source operand. 



67 



LD 

Load 



Load Immediate Value 


(Continued) 














Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




LD addr(Rd), #data 
LDB addr(Rd), #data 








15 
15 








X: 




0l| 001 1 01 | Rd*0 | 0101 




SS 


0l| 001 1.01 


Rd*0 I 01 01 






address 


segment 


offset 


15 




data 


data 






















SL 


1 1 1 1 1 


Rd*0 | 01 01 






1 segment 


0000 0000 


18 




offset 




data 






















1 | 110 | Rd * | 1 1 




SS 


1 J 11 00 


Rd*0 | 01 01 






address 


segment 


offset 


15 




data J data 


data 


data 






















SL 


Oil 001 1 00 


Rd*0 | 1 01 






1 segment 


0000 0000 


18 




offset 




data data 



















Example: 



Several examples of the use of the Load instruction are treated in detail in Chapter 4 
under addressing modes. 



68 



LDA 

Load Address 



LDA dst, src 



dst: R 

src: DA, X, BA, BX 



Operation: 



dst ■+- address (src) 



Flags: 



The address of the source operand is computed and loaded into the destination. The 
contents of the source are not affected. The address computation follows the rules for 
address arithmetic. The destination is a word register in nonsegmented mode, and a 
register pair in segmented mode. 

In segmented mode, the address loaded into the destination has an undefined value 
in all reserved bits (bits 16-23 and bit 31). However, this address may be used by 
subsequent instructions in the indirect based or base- index addressing modes 
without any modification to the reserved bits. 

No flags affected 



Source 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycles 



DA: 



LDA Rdl , address 



011101100000 Rd 



12 



X: 



LDA Rdl, addr(Rs) 



01110110 Rs*0 



BA: 



BX: 



LDA Rdl, Rsl (#disp) 



LDA Rdl-, Rsl (Rx) 



00110100 | Rs*0 | Rd 


displacement 




01110100 


Rs*0 I Rd 


| Rx 


0000 0000 



15 



15 



ss 


01 


110110 


0000 


RRd 


ol 


segment 


offset 












01 


110110 


0000 


RRd 


SL 


1 1 


segment 


0000 


0000 




offset 










SS 


4 


110110 


Rs*0 


RRd 





segment 


offset 












01 


110110 


Rs*0 


RRd 


SL 


1 segment 


0000 


0000 




offset 












00110100 | Rs*0 


Rd 




displacement 












01110100 


Rs*0 


Rd 




0000 | Rx 


0000 


0000 



13 



13 



16 



15 



69 



LDA 

Load Address 



Examples: LDA R4, STRUCT 



LDA RR2, «3» 8(R4) 



LDA RR2,RR4(#8) 



!in nonsegmented mode, register R4 is loaded! 
!with the nonsegmented address of the location! 
Inamed STRUCT! 

!in segmented mode, if index register R4! 

! contains %20, then register RR2 is loaded! 

!with the segmented address («3» , offset %28)! 

!in segmented mode, if base register RR4! 

{contains %01000020, then register RR2 is loaded! 

!with the segment address « 1 » %28! 

!( segment 1, offset %28)! 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



70 



LDAR 

Load Address Relative 



LDAR dst, src 



dst: R 
src: RA 



Operation: 



dst -*- ADDRESS (src) 



Flags: 



The address of the source operand is computed and loaded into the destination. The 
contents of the source are not affected. The destination is a word register in 
nonsegmented mode, and a register pair in segmented mode. In segmented mode, 
the address loaded into the destination has all "reserved" bits (bits 16-23 and bit 31) 
cleared to zero. 

The relative addressing mode is calculated by adding the displacement in the 
instruction to the updated value of the program counter (PC) to derive the address. 
The updated' PC value is taken to be the address of the instruction byte following the 
LDAR instruction, while the displacement is a 16-bit signed value in the range 
-32768 to +32767. The addition is performed following the rules of address 
arithmetic, v/ith no modifications to the segment number in segmented mode. Thus 
in segmented mode, the source operand must be in the same segment as the LDAR 
instruction. 

The assembler automatically calculates the displacement by subtracting the PC value 
of the following instruction from the address given by the programmer. 

No flags affected 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


RA: 


LDAR Rdi , address 








15 












00110100 | | Rd 






00110100 | | Rd 




15 




displacement 


displacement 



















Example: 



LDAR R2, TABLE 
LDAR RR4, TABLE 



!in nonsegmented mode, register R2 is loaded! 
"with the address of TABLE! 

Sin segmented mode, register pair RR4 is! 

! loaded with the segmented address of TABLE,! 

! which must be in the same segment as the program! 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



71 



LDCTL 

Load Control 



Privileged 



Operation: 



LDCTL dst, src 



dst -*- src 



dst: CTLR 
src: R 
or 

dst: R 
src: CTLR 



This instruction loads the contents of a general purpose register into a control 
register, or loads the contents of a control register into a general-purpose register. 
The control register may be one of the following CPU registers: 

FCW Flag and Control Word 

REFRESH Refresh Control 

PSAPSEG Program Status Area Pointer - segment number 

PSAPOFF Program Status Area Pointer - offset 

NSPSEG Normal Stack Pointer - segment number 

NSPOFF Normal Stack Pointer - offset 

The operation of each of the variants of the instruction is detailed below. The ones 
which load data into a control register are described first, followed by the variants 
which load data from a control register into a general purpose register. Whenever 
bits are marked reserved, the corresponding bit in the source register must be either 
or the value returned by a previous load from the same control register. For com- 
patibility with future CPUs, programs should not assume that memory copies of con- 
trol registers contain Os, nor should they store data in reserved fields of memory 
copies of control registers. 



Load Into Control Register 

LDCTL FCW, Rs 



Operation: 



FCW (2:7) «*- Rs (2:7) 
FCW (11:15) *- Rs (11:15) 



15 14 13 12 11 10 9 


8 7 6 5 4 3 2 1 





Rs: I 


H | | V | 


Mini 




;W : |seg|s/n|epa| vi |nvi[||j|J1 


fill C I Z I S [p/vl D I H |v 


1 



LDCTL REFRESH, Rs 



Operation: REFRESH (1:15)-*- Rs ( 1 : 15) 

Rs: 
REFRESH: 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 



I I I I I I I I I 


IIHHIIIl- 


■ III 


re rate cou 


nter Kd 



-*- reserved 



72 



Privileged 



LDCTL 

Load Control 



Operation: 



Operation: 



LDCTL NSPSEG, Rs 
NSPSEG (0:15) +- Rs(0:15) 



15 14 13 12 11 10 9 8 7 

Rs:| 


5 5 4 3 2 10 

i 


If V | V | | | u \< < 


\ » 1 - 1 H 


5G:| i i i , i . i i 1 



In segmented mode, the NSPSEG register is the normal mode R14 and contains the 
segment number of the normal mode processor stack pointer which is otherwise 
inaccessible for system mode. 

In nonsegmented mode, R14 is not used as part of the normal processor stack 
pointer. This instruction may not be used in nonsegmented mode. 

LDCTL NSPOFF, Rs 
NSP, Rs 

NSPOFF (0:15) +- Rs (0:15) 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 



Rs: 


I , 




i i i i i 








I'M 


r v \ } jr ' 


■\\\\\ 


\'W 




•NSPOFF: 


I , . 


i i i i i' 


L 1 1 1 L_ 


, i 


, 1 



Operation: 



*NSP in nonsegmented mode 

In segmented mode, the NSPOFF register is R15 in normal mode and contains the 

offset part of the normal processor stack pointer. In nonsegmented mode, R15 is the 

entire normal processor stack pointer. 

In nonsegmented Z8002, the mnemonic "NSP" should be used in the assembly 

language statement, and indicates the same control register as the mnemonic 

"NSPOFF" 

LDCTL PSAPSEG, Rs 

PSAPSEG(8:14) ^- Rs(8:14) 



U 14 13 12 11 10 


3 8 7 6 


5 4 3 2 10 


Rs:| I 


' 


f j * 


' 1 


' y 


' ' 


■ 


PSAPSEG: I j 


segment number j * 


'^£\M$y&?&\ 



J 



The PSAPSEG register may not be used in the nonsegmented Z8002. In the 
segmented Z8001, care must be exercised when changing the two PSAP register 
values so that an interrupt occurring between the changing of PSAPSEG and 
PSAPOFF is handled correctly. This is typically accomplished by first disabling 
interrupts before changing PSAPSEG and PSAPOFF. 



73 



LDCTL 

Load Control 



Privileged 



LDCTL PSAPOFF, Rs 
PSAP, Rs 



Operation: 



PSAPOFF (8:15) *- Rs (8:15) 



15 14 13 12 11 10 9 


J 7 6 5 4 


3 2 10 


Rs: I , I I 


r'l" In v 


PSAPOFF: | offset (upper byte) 


1 ' 


liiiiiii 



*PSAP in nonssgmented mode 

In the nonsegmented Z8002, the mnemonic "PSAP" should be used in the assembly 
language statement and indicates the same control register as the mnemonic 
"PSAPOFF". In the segmented Z8001, care must be exercised when changing the 
two PSAP register values so that an interrupt occurring between the changing of 
PSAPSEG and PSAPOFF is handled correctly. This is typically accomplished by first 
disabling interrupts before changing PSAPSEG and PSAPOFF. The low order byte 
of PSAPOFF should be 0. 

Load From Control Register 

LDCTL Rd, FCW 



Operation: Rd (2:7) *- FCW (2:7) 

Rd (11:15) -*- FCW (11:15) (Z8001 only) 
Rd (11:14) -*- FCW (11:14) (Z8002 only) 
Rd(0:l) *- UNDEFINED 
Rd(8:10) <- UNDEFINED 
Rd(15) — 0(Z8002only) 





1 


5 14 


13 12 


11 


10 


9 


8 7 6 5' 


I 3 


2 1 


FCW: 


seg|s/n 


EFftlvi 


NVI 






j cTz S JP/V D 


H 

I 


Rd: 








1 HI- 


r " 


I 


I , , , . I 






1 ...... 1 1 












♦ 


undefin 


ed- 


♦ 



LDCTL Rd, REFRESH 

Operation: Rd ( 1 :8) - REFRESH (1:8) 

Rd (0) +- UNDEFINED 
Rd(9:15) «- UNDEFINED 



15 14 13 12 11 10 9 


3 7 e 


5 4 3 2 





SH: | re rate | 


counter | | 


' 


r f i 


' T 1 T T ' 


r 


Rd: | ,,, «»! (l * ll **♦ <, I 


i i i i i i i I ° I 



74 



Privileged 



LDCTL 

Load Control 



LDCTL Rd, PSAPSEG 

Operation: Rd (8: 14) *- PSAPSEG (8: 14) 

Rd (0:7) — UNDEFINED 
Rd(15) *- UNDEFINED 



15 14 13 12 11 10 


3 8 7 6 5 4 3 2 


1 


PSAPSEG:) ;j segment number | , ; . > , , ■ 


sil 


' 


r T T T ▼ v T 


Rd=l I I I 



L 



J 



This instruction may not be used in the nonsegmented version. 

LDCTL Rd, PSAPOFF 
Rd, PSAP 



Operation: Rd (8: 15) — PSAPOFF (8:15) 

Rd (0:7) +- UNDEFINED 



15 14 13 12 11 10 


9 8 7 


6 5 4 3 2 


1 


PSAPOFF: [ offset (upper byte) i 


iilllllllllilil 


I 


TV- 


' i 


- . 


' < 


'\ 


Rd: | | 


undefined 


I 



Operation: 



*PSAP in nonsegmented mode 

In nonsegmented mode, the mnemonic PSAP should be used in the assembly 
language statement, and it indicates the same control register as the mnemonic 
PSAPOFF. 

LDCTL Rd, NSPSEG 
Rd(0:15) ♦- NSPSEG (0:15) 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0- 



:l I 


1 J 

\i }t V V H W \f }f f < 


. . 


r | i 


\\ 


• L i i i i i i i i i ..i ..i . i _ i _ j — i — 1 



This instruction is not available in nonsegmented mode. 



75 



LDCTL 

Load Control 



Privileged 



Operation: 



LDCTL Rd, NSPOFF 
Rd, NSP 

Rd(0:15) -.- NSPOFF (0:15) 
* NSPOFF 



Rd: 



15 14 13 12 11 10 9 8 7 

I . . 


6 5 4 


3 2 10 

, , , I 


V " v V | | M M v 


u | u 


"ITT 


1 1 I 1 1 1 1 1 1 1 j 1 1 1 1 1. 1 



Flags: 



*NSP in nonsegmented mode 

In nonsegmented mode, the mnemonic NSP should be used in the assembly 
language statement, and it indicates the same control register as the mnemonic 
NSPOEF. 

No flags affected, except when the destination is the Flag and Control Word (LDCTL 
FCW, Rs), in which case all the flags are loaded from the source register. 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




LDCTL FCW, Rs 

LDCTL REFRESH, Rs 

LDCTL PSAPSEG, Rs 

LDCTL PSAPOFF, Rs 
PSAP, Rs 

LDCTL NSPSEG, Rs 

LDCTL NSPOFF, Rs 
NSP, Rs 




7 
7 

7 

7 








| 1 1 1 1 1 1 | Rs | 1 1 | 


| 1 1 1 1 1 1 | Rs | 1 1 | 












| 1 1 1 1 1 1 | Rs | 1 1 1 | 


| 1 1 1 1 1 1 | Rs | 1 1 1 | 














| 1 11 11 1 | Rs | 1 1 | 












| 111110 1 ] Rs | 1 1 1 | 


| 1 1 1 1 1 1 | Rs | 1 1 1 ( 














| 1 1 1 1 1 1 | Rs | 1 1 1 | 












| 01 1 1 1 1 01 | Rs | 1 1 1 1 | 


| 01 1 1 1 101 | Rs | 1 1 1 1 | 












Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




LDCTL Rd, FCW 

LDCTL Rd, REFRESH 

LDCTL Rd, PSAPSEG 

LDCTL Rd, PSAPOFF 
LDCTL Rd, PSAP 
LDCTL Rd, NSPSEG 

LDCTL Rd, NSPOFF 
Rd, NSP 




7 
7 

7 

7 








| 01111101 | Rd | 1 | 


| 01111101 | -Rd | 1 | 














| 01111101 | Rd | 001 1 | 


| 0111110 1 | Rd | 001 1 | 














| 01111101 | Rd | 1 | 












| 01111101 | Rd | 01 01 | 


| 1 1 1 1 1 1 | Rd | 1 1 | 














| 1 1 1 1 1 1 | Rd | 1 1 | 












| 1 1 1 1 1 1 | Rd | 1 1 1 | 


| 1 1 1 1 1 1 | Rd | 1 1 1 | 













76 



LDCTLB 

Load Control Byte 



LDCTLB dst, src 



dst: FLAGS 

src: R 

or 

dst: R 

src: FLAGS 



Operation: 



dst • 



This instruction is used to load the FLAGS register or to transfer its contents into a 
general-purpose register. Note that this is- not a privileged instruction. 



Load Into FLAGS Register 

LDCTLB FLAGS, Rbs 

FLAGS (2:7) V src (2:7) 



The contents of the source (a byte register) are loaded into the FLAGS register. The 
lower two bits of the FLAGS register and the entire source register are unaffected. 



Rbs: 



FLAGS: 



7 6 5 4 3 2 1 

I I» 





H | j \t j M 


| C | Z | S |p/v| D | H [;• . ' | 



reserved 



Load From FLAGS Register 

LDCTLB Rbd, FLAGS 

dst (2:7) +- FLAGS (2:7) 
dst (0:1) *- 



The contents of the upper six bits of the FLAGS register are loaded into the destina- 
tion (a byte register). The lower two bits of the destination register are cleared to 
zero. The FLAGS register is unaffected. 



FLAGS: 



Rbd: 



7 


5 5 4 3 2 10 

I | S |p/v| D | H [ | 


Tl 


llll 


| | ° i ° | 



Flags: 



When the FLAGS register is the destination, all the flags are loaded from the 
source. When the FLAGS register is the source, none of the flags are affected. 



77 



LDCTLB 

Load Control Byte 





Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 




Instruction Format 


Cycles 


Instruction Format 


Cycles 




LDCTLB FLAGS, Rbs 
LDCTLB Rbd, FLAGS 




7 

7 








| 1 1 1 | Rs | 1 1 | 


] 10001100 | Rs | 1 00 1 | 


7 




| 10001100 | Rd |0001| 


| 10001100 | Rd | 1 | 


7 









78 



LDD 

Load and Decrement 



LDD dst, src, r 
LDDB 



dst: IR 
src: IR 



Operation: dst •*- src 

AUTODECREMENT dst and src (by 1 if byte, by 2 if word) 
r ««- r - 1 



Flags: 



This instruction is used for block transfers of strings of data. The contents of the loca- 
tion addressed by the source register are loaded into the location addressed by the 
destination register. The source and destination registers are then decremented by 
one if LDDB, or by two if LDD, thus moving the pointers to the previous elements in 
the strings. The source destination, and counter registers must be separate and non- 
overlapping registers. The word register specified by V (used as a counter) is then 
decremented by one. 

C: Unaffected 

Z: Undefined 

S: Unaffected 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


LDD @Rsl, @Rdl, r 
LDDB @Rsi, @Rdi, r 








20 












101 1 101 |w 


Rs * 


1001 






1 01 1 1 01 |w 


Rs * 


1 001 




20 




0000 | r 


Rd * 


1000 


000 | r 


Rd * 


1 000 



















Example: 



In nonsegmented mode, if register Rl contains %202A, register R2 contains %404A, 
the word at location %404A contains %FFFF, and register R3 contains 5, 
the instruction 

LDD@R1, @R2, R3 

will leave the value %FFFF at location %202A, the value %2028 in Rl, the value 
%4048 in R2, and the value 4 in R3. The V flag will be cleared. In segmented mode, 
register pairs would be used instead of Rl and R2. 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



79 



LDDR 

Load, Decrement and Repeat 



LDDR dst, src, r 
LDDRB 



dst: IR 
src: IR 



Operation: 



Flags: 



dst -+- src 

AUTODECREMENT dst and src (by 1 if byte, by 2 if word) 

r -*- t - 1 

repeat until r = 

This instruction is used for block transfers of strings of data. The contents of the loca- 
tion addressed by the source register are loaded into the location addressed by the 
destination register. The source and destination registers are then decremented by 
one if LDDRB, or by two if LDDR, thus moving the pointers to the previous elements 
in the strings. The word register specified by "r" (used as a counter) is then 
decremented by one. The entire operation is repeated until the result of decremen- 
ting r is zero. The source, destination, and counter registers must be separate and 
non- overlapping registers. This instruction can transfer from 1 to 65536 bytes or from 
1 to 32768 words (the value for r must not be greater than 32768 for LDDR). 

The effect of decrementing the pointers during the transfer is important if the source 
and destination strings overlap with the. source string starting at a lower memory 
address. Placing the pointers at the highest address of the strings and decrementing 
the pointers ensures that the source string will be copied without destroying the 
overlapping area. 

This instruction can be interrupted after each execution of the basic operation. The 
program counter value of the start of this instruction is saved before the interrupt 
request is accepted, so that the instruction can be properly resumed. Seven cycles 
should be added to this instruction's execution time for each interrupt request that is 
accepted. 

C: Unaffected 
Z: Undefined 
S: Unaffected 
V: Set 

D: Unaffected 
H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 2 


Instruction Format 


Cycles 2 




LDDR @Rdl, @Rsl, r 
LDDRB @Rdi, @Rsi, r 








11+9n 










IR: 




1 01 1 1 01 |w| Rs 


1001 






1 1 1 1 1 | w 


Rs 


1 001 




11+9n 




0000 r 


Rd 


0000 


0000 | r 


Rd 


0000 



















80 



LDDR 

Load, Decrement and Repeat 



Example: In nonsegmented mode, if register Rl contains %202A / register R2 contains %404A, 

the words at locations %4040 through %404A all contain %FFFF, and register R3 
contains 6, the instruction 

LDDR @R1 / @R2 / R3 

will leave the value %FFFF in the words at locations %2020 through %202A, the 
value %201E in Rl, the value %403E in R2, and in R3. The V flag will be set. In 
segmented mode, register pairs would be used instead of Rl and R2. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of data elements transferred. 



81 



LDI 

Load and Increment 



LDI dst, src, r 
LDIB 



dst: IR 
src: IR 



Operation: dst -«- src 

AUTOINCREMENT dst and src (by 1 if byte, by 2 if word) 
r -*- r - 1 



Flags: 



This instruction is used for block transfers of strings of data. The contents of the loca- 
tion addressed by the source register are loaded into the location addressed by the 
destination register. The source and destination registers are then incremented by 
one if LDIB, or by two if LDI, thus moving the pointers to the next elements in the 
strings. The source, destination, and counter registers must be separate and non- 
overlapping registers. The word register specified by u r" (used as a counter) is then 
decremented by one. 

C: Unaffected 

Z: Undefined 

S: Unaffected 

V: Set if the result of decrementing r is zero, cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




LDI@Rdl,@Rsl, r 
LDIB@Rdl, @Rsi, r 








20 










IR: 




1011101 |w 


Rs * 


0001 






101 1 101 |w 


R8 * 


0001 




20 




0000 | r 


Rd * 


1000 


0000 | r 


Rd * 


1000 



















Example: 



This instruction can be used in a "loop" of instructions which transfers a string of 
data from one location to another, but an intermediate operation on each data ele- 
ment is required. The following sequence transfers a string of 80 bytes, but tests for 
a special value (°/oOD, an ASCII return character) which terminates the loop if 
found. This example assumes nonsegmented mode. In segmented mode, register 
pairs would be used instead of Rl and R2. 



LOOP: 



DONE: 



LD 

LDA 

LDA 

CPB 
JR 

LDIB 
JR 



R3, #80 
Rl, DSTBUF 
R 2 , SRCBUF 

@R2, #%0D 
EQ, DONE 
@R1, @R2, R3 
NOV, LOOP 



{initialize counter! 
!load start addresses! 



! check for return character! 
!exit loop if found! 
! transfer next byte! 
'repeat until counter = 0! 



Word register in nonsegmented mode, register pair in segmented mode. 



82 



LDIR 

Load, Increment and Repeat 



LDIR dst, src, r 
LDIRB 



dst: IR 
src: IR 



Operation: 



Flags: 



dst •*- src 

AUTOINCREMENT dst and src (by 1 if byte; by two if word) 

r -*- r - 1 

repeat until R = 

This instruction is used for block transfers of strings of data. The contents of the loca- 
tion addressed by the source register are loaded into the location addressed by the 
destination register. The source and destination registers are then incremented by 
one if LDIRB, or by two if LDIR, thus moving the pointers to the next elements in the 
strings. The word register specified by V (used as a counter) is then decremented 
by one. The entire operation is repeated until the result of decrementing r is zero. 
The source, destination, and counter registers must be separate and non-overlapping 
registers. This instruction can transfer from 1 to 65536 bytes or from 1 to 32768 
words (the value for r must not be greater than 32768 for LDIR). 

The effect of incrementing the pointers during the transfer is important if the source 
and destination strings overlap with the source string starting at a higher memory 
address. Placing the pointers at the lowest address of the strings and incrementing . 
the pointers ensures that the source string will be copied without destroying the 
overlapping area. 

This instruction can be interrupted after each execution of the basic operation. The 
program counter value of the start of this instruction is saved before the interrupt 
request is accepted, so that the instruction can be properly resumed. Seven cycles 
should be added to this instruction's execution time for each interrupt request that is 
accepted. 

C: Unaffected 
Z: Undefined 
S: Unaffected 
V: Set 

D: Unaffected 
H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 2 


Instruction Format 


Cycles 2 


IR: 


LDIR <&Rdl, <&'Rsi, r 
LDIRB @Rdi, @Rsi, r 








11+9n 












101 1101 |w 


R» * 


0001 






101 1101 |w 


Rs *0 


0001 




11+9n 




0000 | r 


Rd * 


0000 


0000 | r 


Rd*0 


0000 



















83 



LDIR 

Load, Increment and Repeat 



Example: The following sequence of instructions can be used in nonsegmented mode to copy a 

buffer of 512 words (1024 bytes) from one area to another. The pointers to the start of 
the source and destination are set, the number of words to transfer is set, and then 
the transfer takes place. 

LDA Rl, DSTBUF 

LDA R2, SRCBUF 

LD R3, #512 

LDIR @R1, @R2 7 R3 

In segmented mode, Rl and R2 must be replaced by register pairs. 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of data elements transferred. 



84 



LDK 

Load Constant 



LDK dst, src 



dst: R 
src: IM 



Operation: 



dst -+- src (src = to 15) 



Flags: 



The source operand (a constant value specified in the src field) is loaded into the 
destination register. The source operand is a value from to 15. It is loaded into the 
four low-order bits of the destination register, while the high-order 12 bits are 
cleared to zero. 

No flags affected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


LDK Rd, #data 




5 






|10| 1 1 1 101 | Rd | data | 


1 1 | 1 1 1 1 1 | Rd | data | 


5 











Example: 



To load register R3 with the constant 9: 
LDK R3,#9 



85 



LDM 

Load Multiple 



LDM dst, src, n dst: R 

src: IR, DA, X 

or 

dst: IR, DA, X 

src: R 

Operation: dst <- src(n words) 

The contents of n source words are loaded into the destination. The contents of the 
source are/iot affected. The value of n lies between 1 and 16, inclusive. This instruc- 
tion moves information between memory and registers; registers are accessed in 
increasing order starting with the specified register; RO follows R15. The instruction 
can be used either to load multiple registers into memory (e.g. to save the contents 
of registers upon subroutine entry) or to load multiple registers from memory (e.g. to 
restore the contents of registers upon subroutine exit). 

The instruction encoding contains values from to 15 in the n num" field correspond- 
ing to values of 1 to 16 for n, the number of registers to be loaded or saved. 

The starting address is computed once at the start of execution, and incremented by 
two for each register loaded. If the original address computation involved a register, 
the register's value will not be affected by the address incrementation during 
execution. Similarly, modifying that register during a load from memory will not 
affect the address used by this instruction. 

Flags: No flags affected 



Load Multiple - Registers From Memory 














Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


LDM Rd, &Rsl, #n 
LDM Rd, address, #n 

LDM Rd, addr(Rs), #n 








11+3n 

14 + 3n 

15 + 3n 










oo| 011100 


Rs*0 


0001 






oo| 011100 


Rs*0 


0001 


11+3n 




| Rd 


0000 


num 


| Rd 


0000 


num 


DA: 
















1 1 011100 


0000 


0001 




SS 


I J 011100 


0000 


0001 






| Rd 


0000 


num 


| Rd 


0000 


num 


15 + 3n 




address 


Oj segment 


offset 






















SL 


1 1 01110 


0000 


0001 






| Rd 


0000 


num 


17 + 3n 




1 1 segment 


0000 0000 






offset 




X: 
















01 1 011100 


Rs*0 


0001 




SS 


01011100 


Rs*0 


0001 






| Rd 


0000 


num 


| Rd 


0000 


num 


15 + 3n 




address 


1 segment 


offset 






















SL 


01011100 


Rs*0 


0001 






| Rd 


0000 


num 


18 + 3n 




1 segment 


0000 0000 




offset 























86 



LDM 

Load Multiple 



Load Multiple - Memory From Registers 



Destination 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycle 



IR: 



DA: 



LDM&Rdi, Rs, #n 



LDM address, Rs, #n 



oo| 011100 


Rd*0 


1001 


| Rs 


0000 


num 




1 | 11100 


0000 


1001 


I Rs 


0000 


num 


address 



11+3n 



14 + 3n 



LDM addr(Rd), Rs, #n 



0l| 01 1 1 00 


Rd*0 


1 001 


| Rs 


0000 


num 


address 



15 + 3n 





0| 1110 


Rd*0 


1 001 




| Rs 


0000 


num . 










Oil 011100 


0000 


1001 


ss 


0000| Rs 


0000 


num 




segment 


offset 










01 | 011100 


0000 


1001 


SL 


| Rs 


0000 


num 


1 segment 


0000 0000 




offset 










1 | 011100 


Rd*0 


1001 


SS 


| Rs 


0000 


num 




segment 


offset 




} 






1 | 011100 


Rd*0 


1 001 


SL 


00 | Rs 


0000 


num 


1 segment 


0000 0000 




offset 



11+3n 



15 + 3n 



17 + 3n 



15 + 3n 



18 + 3n 



Example: In nonsegmented mode, if register R5 contains 5, R6 contains %0100, and R7 con- 

tains 7, the statement 

LDM @R6, R5, #3 • 

will leave the values 5, %0100, and 7 at word locations %0100 ; %0102, and %0104, 
respectively, and none of the registers will be affected. In segmented mode, a 
register pair would be used instead of R6. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of registers. 



87 



LDPS 

Load Program Status 



Privileged 



LDPS src 



src: IR, DA, X 



Operation: 



Flags: 



PS *- src 

The contents of the source operand are loaded into the Program Status (PS), loading 
the Flags and Control Word (FCW) and the program counter (PC). The new value 
of the FCW does not become effective until the next instruction, so that the status 
pins will not be affected by the new control bits until after the LDPS instruction 
execution is completed. The next instruction executed is that addressed by the new 
contents of the PC. The contents of the source are not affected. 
This instruction is used to set the Program Status of a program and is particularly 
useful for setting the System/Normal mode of a program to- Normal mode, or for run- 
ning a nonsegmented program in the segmented Z8001 version. The PC segment 
number is not affected -by the LDPS instruction in nonsegmented mode. 

The format of the source operand (Program Status block) depends on the current 
Segmentation mode (not on the version of the Z8000) and is illustrated in the 
following figure: 



NONSEGMENTED 



LOW ADDRESS 



HIGH ADDRESS 



(shaded area is reserved — must be zero) 



All flags are loaded from the source operand. 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


LDPS @Rsi 
LDPS address 

LDPS addr(Rs) 








12 
16 

17 










00| 1 1 1 001 | Rs*0 | 0000 


& 


1 1 1001 | Rs*0 | 0000| 


16 


DA: 










1 | 111001 | | 




SS 


01 


1 1 1 001 


0000 | 0000 


20 




address 


1 


segment 


offset 






















SL 


01 


1 1 1 001 


oooo |oooo 






1 segment 


0000 0000 


22 




offset 




X: 


















0l| 111001 | Rs*0 | 0000 




SS 


01 


111001 


Rs*0 | 0000 


20 




address 


o| 


segment 


offset 






















SL 


01 


1 1 1 001 


Rs*0 | 0000 






1 I segment 


00 00 000 


23 




offset 





















Privileged LDPS 

Load Program Status 



Example: In the nonsegmented Z8002 version, if the program counter contains %2550, register 

R3 contains %5000, location %5000 contains %1800, and location %5.002 contains 
%A000, the instruction 

LDPS @R3 
will leave the value %A000 in the program counter, and the FCW value will be 
%1800 (indicating Normal Mode, interrupts enabled, and all flags cleared.) In the 
segmented mode, a register pair is used instead of R3. Note: Word register is used 
in nonsegmented mode, register pair in segmented mode. 



89 



LDR 

Load Relative 



LDR dst, src 

LDRB 

LDRL 



dst: R 
src: RA 
or 

dst: RA 
src: R 



Operation: 



dst -*- src 



The contents of the source operand are loaded into the destination. The contents of 
the source are not affected. The relative address is calculated by adding the 
displacement in the instruction to the updated value of the program counter (PC) 
to derive the operand's address. In segmented mode, the segmented number of the 
computed address is the same as the segment number of the PC. The updated PC 
value is taken to be the address of the instruction byte following the LDR, LDRB, or 
LDRL instruction, while the displacement is" a 16-bit signed value in the range 
-32768 to +32767. 

Status pin information during the access to memory for the data operand will be Pro- 
gram Reference, (1100) instead of Data Memory request (1000). 

The assembler automatically calculates the displacement by subtracting the PC value 
of the following instruction from the address given by the programmer. 

This instruction must be used to modify memory locations containing program infor- 
mation, such as the Program Status Area, if program and data space are allocated to 
different segments. 



Flags: No flags affected 

Load Relative Register 



Source 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format- 



Cycles 



RA: 



LDR Rd, address 
LDRB Rbd, address 



LDRL RRd, address 



001 1 ooo|w| 0000 | 


Rd 


displacement 




001 10101 | 0000 | 


Rd 


displacement 



17 



oonooo|w|oooo| 


Rd 


displacement 




001 10101 | 0000 


Rd 


displacement 



14 



17 



90 



LDR 

Load Relative 



Load Relative Memory 


( 
















Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




LDR address, Rs 
LDRB address, Rbs 

LDRL address, RRs 








14 
17 










RA: 




0011001 |w| 0000 | Rs 






001 1001 |w| 0000| Rs 




14 




displacement 


displacement 






















00110111 |0000| Rs 






001 10111 | 0000 | Rs 




■J7 




displacement 


displacement 





















Example: 



LDR R2, DATA 



! register R2 is loaded with the value in the! 
! location named DATA! 



91 



MBIT 

Multi-Micro Bit Test 



Privileged 



MBIT 



Operation: 



1 if MI high (inactive); otherwise 



Flags: 



This instruction is used to synchronize multiple processors' exclusive access to 
shared hardware resources. The multi-micro input pin (MI) is tested, and the S flag 
is cleared if the pin is low (active); otherwise, the S flag is set, indicating that the 
pin is high (inactive). 

After the MBIT instruction is executed, the S flag can be used to determine whether 
a requested resource is available or not. If the S flag is clear, then the resource is 
not available; if the S flag is set. then the resource is available for use by this CPU. 

C: Unaffected 

Z: Undefined 

S: Set if MI is high; cleared otherwise 

V: Unaffected 

D: Unaffected 

H: Unaffected 





Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 




Instruction Format 


Cycles 


Instruction Format 


Cycles 




MBIT 




7 








| 01111011 00001 010 | 


| 0111101 10000101 o | 


7 











Example: 



The following sequence of instructions can be used to wait for the availability of a 
resource. 

LOOP: 

MBIT !test multi-micro input! 

IR PL, LOOP ! repeat until resource is available! 
AVAILABLE: 



92 



Privileged MREQ 

Multi-Micro Request 



MREQ dst dst: R 

Operation: Z -+- 

if MI low (active) then S •«- 

MO forced high (inactive) 
else MO forced low (active) 

repeat dst -*- dst - 1 until dst = 
if MI low (active) then S -*- 1 
else S -+- 

MO forced high (inactive) 
Z*- 1 

This instruction is used to synchronize multiple processors' exclusive access to 
shared hardware resources. A reques t for a resource is signalled through the multi- 
micro input and output pins (MI and MO), with the S and Z flags indicating the 
availability of the resource after the MREQ instruction has been executed. 

First, the Z flag is cleared. T hen the MI pin is tested. If the MI pin is low (active), 
the S flag is cleared and the MO pin is. forced high (inactive), thus indicating that the 
reso urce is not available and removing any previous request by the CPU from the 
MO line. 

If the MI pin is high (inactive), indicating that the reso urce may be available, a 
sequence of machine operations occurs. First, the MO pin is forced low (active), 
signalling a request by the CPU for the resource. Next, a finite delay to allow for 
propagation of the signal to other processors is accomplished by repeatedly 
decrementing the contents of the destination (a word register) until its value is zero. 
Then the MI pin is tested to determine whether the request for the resource was 
acknowledged. If the MI pin is low (active), the S flag is set to one, indicating that 
the resource is available and access i s gr anted. If the MI pin is still high (inactive), 
the S flag is cleared to zero, and the MO pin is forced high (inactive), in dica ting 
that the request was not granted and removing the request signal for the MO. 
Finally, in either case, the Z flag is set to one, indicating that the original test of the 
MI pin caused a request to be made. 

S flag Z flag MO Indicates 



high Request not signalled 

(resource not available) 

1 high Request not granted 

(resource not available) 
1 low Request granted 

(resource available) 



Flags: C: Unaffected 

Z: Set if request was signalled; cleared otherwise 

S: Set if request was signalled and granted; cleared otherwise 

V: Unaffected 

D: Unaffected 

H: Unaffected 



93 



MREQ Privileged 

Multi-Micro Request 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 1 


Instruction Format 


Cycles 1 


R: 


MREQ. Rd 




12 + 7n 






|oi| 11 1011 | Rd | 1 101 | 


|oi| 111011 | Rd | 1101 | 


12 + 7n 











Example: 



TRY: 

LD R0,#50 lallow for propagation delay! 

MREQ R0 ! multi-micro request with delay! 

!in register R0! 
JR MI,AVAILABLE 
JR Z,NOT_GR ANTED 

NOT_A VAIL ABLE: • Iresource not available! 



NOT_GR ANTED: 



JR TRY 



AVAILABLE: 



MRES 



! request not granted! 



•try again after awhile! 
juse resource! 



! release resource! 



Note 1: If the request is made, n = number of times the destination is decremented. If the request is not made, 
n = 0. 



94 



Privileged 



MRES 

Multi-Micro Reset 



MRES 



Operation: 



MO is forced high (inactive) 



This instruction is used to synchronize multiple process ors' e xclusive access to 
shared h ardw are resources. The multi-micro output pin MO is forced high (inactive). 
Forcing MO high (inactive) indicates that a resource controlled by the CPU is 
available for use by other processors. 



Flags: 


No flags affected. 












Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 




Instruction Format 


Cycles 


Instruction Format 


Cycles 




MRES 


1 




5 








01111011 | 00001001 | 


| 01 1 1 101 1 | 00001 001 | 


5 









Example: 



MRES 



! signal that resource controlled by this CPU! 
lis available to other processors! 



95 



MSET 

Multi-Micro Set 



Privileged 



MSET 



Operation: MO is forced low (active) 

This instruction is used to synchronize multiple process ors' e xclusive access to 
shared hardw are resources. The multi-micro output pin MO is forced low (active). 
Forcing MO low (active) is used either to indicate that a resource controlled by the 
CPU is not available to other processors, or to signal a request for a resource con- 
trolled by some other processor. 



Flags: 


No flags affected. 












Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 




Instruction Format 


Cycles 


Instruction Format 


Cycles 




MSET 


I 




5 








01111011 | 00001000 | 


| 01111011 | 00001000 | 


5 











Example: 



MSET 



!CPU controlled resource not available! 



MULT 

Multiply 



MULT dst, src dst: R 

MULTL src: R, IM ; IR, DA, X 

Operation: Word 

dst (0:31) «*- dst (0:15) x src (0:15) 

Long 

dst (0:63) — dst (0:31) x src (0:31) 

The low-order half of the destination operand (multiplicand) is multiplied by the 
source operand (multiplier) and the product is stored in the destination. The con- 
tents of the source are not affected. Both operands are treated as signed, two's com- 
plement integers. For MULT, the destination is a register pair and the source is a 
word value; for MULTL, the destination is a register quadruple and the source is a 
long word value. 

For proper instruction execution, the u dst field" in the instruction format encoding 
must be even for MULT and must be a multiple of 4 (0, 4, 8, 12) for MULTL. If the 
source operand in MULTL is a register, the u src field" must be even. 

The initial contents of the high-order half of the destination register do not affect the 
operation of this instruction and are overwritten by the result. The carry flag is set to 
indicate that the upper half of the destination register is required to represent the 
result; if the carry flag is clear, the product can be correctly represented in the same 
precision as the multiplicand and the upper half of the destination merely holds a 
sign extension. 

The following table gives execution times for word and long word operands in each 
possible addressing mode. 

src Word Long Word 



R 


70 


70 


70 


IM 


70 


70 


70 


IR 


70 


70 


70 


DA 


71 


72 


74 


X 


72 


72 


75 



NS SS SL NS SS SL 

282 + 7*n 282 + 7*n 282 + 7*n 

282 + 7*n 282 + 7*n 282 + 7*n 

282 + 7*n 282 + 7*n 282 + 7*n 

283 + 7*n 284 + 7*n 286 + 7*n 

284 + 7*n 284 + 7*n 287 + 7*n 

(n = number of bits equal to one in the absolute value of the low-order table 32 bits of the destination operand) 



When the multiplier is zero, the execution time of Multiply is reduced to the following times: 
src Word Long Word 





NS 


SS 


SL 


NS 


SS 


SL 


R 


18 


18 


18 


30 


30 


30 


IM 


18 


18 


18 


30 


30 


30 


IR 


18 


18 


18 


30 


30 


30 


DA 


19 


20 


22 


31 


32 


34 


X 


20 


20 


23 


32 


32 


35 



Flags: C: MULT — set if product is less than -2 31 or greater than or equal to 2 15 ; cleared 

otherwise; MULTL — set if product is less than 2 31 or greater than or equal to 2 31 ; 
cleared otherwise 

Z: Set if the result is zero; cleared otherwise 

S: Set if the result is negative; cleared otherwise 

V: Cleared 

D: Unaffected 

H: Unaffected 



97 



MULT 

Multiply 



Source 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 5 



Segmented Mode 



Instruction Format 



Cycles 2 



R: 



IM: 



IR: 



DA: 



X: 



MULT RRd, Rs 
MULTL RQd, RRs 
MULT RRd, #data 

MULTL RQd, #data 

MULT RRd, @Rsi 
MULTL RQd, @Rsi 
MULT RRd, address 



MULTL RQd, address 



MULT RRd, addr(Rs) 



MULTL RQd, addr(Rs) 



10 011001 Rs Rd 



10 110 Rs Rd 



000110010000 Rd 



00 


01 1000 | 0000 | 


Rd 


31 


data (high) 


16 


15 


data (low) 






00 01 1001 Rs*0 Rd 



1 1 01 1000 | Rs*0 | Rd | 



010110 010000 Rd 



010110000000 Rd 



01011001 Rs*0 Rd 



01 01 1 000 Rs*0 Rd 





1 | 1 1 1 | Rs 


Rd | 






io|ohooo|rs 


Rd | 






oo| 01 1 001 | 0000 


Rd 




data 










oo| 01 1 000 | 0000 


Rd 




31 data (high) 


16 




15 data (low) 











oo|oiiooi|rs*o 


Rd | 






00| 01 1000 | Rs*0 


Rd | 






ss 


1 1 11 001 


0000 


Rd 


segment 


offset 










1 I 011001 


0000 


Rd 


SL 


1 segment 


0000 


0000 




offset 








SS 


01 | 011 000 


0000 


Rd 


segment 


offset 










1 I 011 000 


0000 


Rd 


SL 


1 segment 


0000 


0000 




offset 








SS 


1 110 1 


Rs*0 


Rd 


segment 


offset 










01 011 001 


Rs*0 


Rd 


SL 


1 segment 


0000 


0000 




offset 








SS 


1 011000 


Rs*0 


Rd 


1 segment 


offset 










1 1 01 1 000 


Rs*0 


Rd 


SL 


1 segment 


0000 


0000 




offset 



MULT 

Multiply 



Example: If register RQO (composed of register pairs RRO and RR2) contains 

% 2222222200000031 (RR2 contains decimal 49), the statement 

MULTL RQ0J10 
will leave the value % 00000000000001 EA (decimal 490) in RQO. 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: Execution times for each instruction are given in the preceding tables. 



99 



NEG 

Negate 



NEG dst 
NEGB 



dst: R, IR, DA, X 



Operation: 



Flags: 



dst +- dst 

The contents of the destination are negated, that is, replaced by its two's comple- 
ment value. Note that %8000 for NEG and %80 for NEGB are replaced by 
themselves since in two's complement representation the negative number with 
greatest magnitude has no positive counterpart; for these two cases, the V flag is set. 

C: Cleared if the* result is zero; set otherwise, which indicates a "borrow" 

Z: Set if the result is zero; cleared otherwise 

S: Set if the result is negative; cleared otherwise 

V: Set if the result is %8000 for NEG, or %80 for NEGB: cleared otherwise 

D: Unaffected 

H: Unaffected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


NEGRd 
NEGB Rbd 

NEG @Rdi 
NEGB @Rd' 

NEG address 
NEGB address 

NEG addr(Rd) 
NEGB addr(Rd) 








7 
12 

15 
16 








io|oono|w| Rd | 00 1 


10|00110|w| Rd | 1 | 


7 


IR: 








oo|ooi io|w| Rd*0 | 1 


OOJOO 1 10|w| Rd*0 | 1 | 


12 


DA: 










01 lo o 1 io|w| 0000 I 1 




SS 


o 1 |oo 1 io|w 


0000 | 001 


16 




address 


1 segment 


offset 




















SL 


oi|ooiio|w 


0000 | 0010 






1 1 segment 


0000 0000 


18 




offset 




X: 
















01 JO 1 10|w| Rd*0 | 00 1 




SS 


01 |ooi 1 o|w 


Rd*0 | 00 10 


16 




address 


1 segment 


offset 




















SL 


1 1 1 1 1 W 


Rd*0 | 001 






1 I segment 


0000 0000 


19 




offset 



















Example: If register R8 contains %051F, the statement 

NEG R8 
will leave the value %FAE1 in R8. 

Note 1 : Word register.in nonsegmented mode, register pair in segmented mode. 



100 



NOP 

No Operation 



NOP 

Operation: No operation is performed. 
Flags: No flags affected 




Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 




Instruction Format 


Cycles 


Instruction Format 


Cycles 




NOP 




7 








| 10001 101 | 000001 1 1 | 


| 10001101 | 000001 1 1 | 


7 











101 



OR 

Or 



OR dst, src 
ORB 



dst: R 

src: R, IM, IR, DA, X 



Operation: 



dst -*- dst OR src 



Flags: 



The source operand is logically ORed with the destination operand and the result is 
stored in the destination. The contents of the source are not affected. The OR opera- 
tion results in a one bit being stored whenever either of the corresponding bits in the 
two operands is one; otherwise a zero bit is stored. 

C: Unaffected 

Z: Set if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 

P: OR — unaffected; ORB— set if parity of the result is even; cleared otherwise 

D: Unaffected 

H: Unaffected 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


OR Rd, Rs 
ORB Rbd, Rbs 

OR Rd, #data 
ORB Rbd, #data 

OR Rd, @Rsi 
ORB Rbd, @Rsi 

OR Rd, address 
ORB Rbd, address 

OR Rd, addr(Rs) 
ORB Rbd, addr(Rs) 








4 

7 

7 

7 
9 

10 








1 o |ooo 1 o|w| Rs | Rd 


10|00010|w| Rs | Rd | 


4 


IM: 










oo| 000101 | 0000 | Rd 






00| 000101 |0000| Rd 


7 




data 


data 




















oo| 000100 


| Rd 






1 000100 


| Rd 


7 




data 


data 


data 


data 


IR: 














00]00010|w| Rs*0 | Rd 


00|00010|w| Rs*0 | Rd | 


7 


DA: 










01 1000 1 o|w| 0000 | Rd 




SS 


oi|oooio|w 


| Rd 


10 




address 


1 segment 


offset 




















SL 


oi|oooio|w 


| Rd 






1 segment 


0000 0000 


12 




offset 




X: 
















01 1000 1 o|w| Rs*0 | Rd 




SS 


oi|oooio|w 


Rs*0 | Rd 


10 




address 


segment 


offset 




















SL 


oi|oooio|w 


Rs*0 | Rd 






1 J segment 


0000 0000 


13 




address 





















102 



OR 

Or 



Example: If register RL3 contains %C3 (11000011) and the source operand is the immediate 

value %7B (01111011), the statement 

ORB RL3,#°/o7B 

will leave the value %FB (11111011) in RL3. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



103 



OTDR (SOTDR) Privileged 

(Special), Output , Decrement and Repeat 



OTDR dst, src, r 
OTDRB 
SOTDR 
SOTDRB 



dst: IR 
src: IR 



Operation: dst -+- src 

AUTODECREMENT src (by 1 if byte, by 2 if word) 

r«- r- 1 

repeat until r = 

This instruction is used for block output of strings of data. OTDR and OTDRB are 
used for normal I/O operation; SOTDR and SOTDRB are used for special I/O opera- 
tion. The contents of 'the memory location addressed by the source register are 
loaded into the I/O port addresses by the destination word register. I/O port 
addresses are 16 bits. The source register is then decremented by one if a byte 
instruction, or by two if a word instruction, thus moving the pointer to the previous 
element of the string in memory. The word register specified by "r" (used as a 
counter) is then decremented by one. The address of I/O port in the destination 
register is unchanged. The entire operation is repeated until the result of decrement- 
ing r is zero. This instruction can output from 1 to 65536 bytes or 32768 word (\fye 
value for r must not be greater than 32768 for OTDR or SOTDR). 

This instruction can be interrupted after each execution of the basic operation. The 
program counter value of the start of this instruction is saved before the interrupt 
reguest is accepted, so that the instruction can be properly resumed. Seven more 
cycles should be added to this instruction's execution time for each interrupt reguest 
that is accepted. 

Flags: C: Unaffected 

Z: Undefined 
S: Unaffected 
V: Set 

D: Unaffected 
H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 2 


Instruction Format 


Cycles 2 




OTDR @Rd,@Rsl, r 
OTDRB @Rd,@Rsi, r 

SOTDR @Rd,@Rsl, r 
SOTDRB @Rd,@Rsi, r 








11 + 10n 










IR: 




0011101 |w 


Rs *0 


101S 






001 1 101 |w 


Rs *0 


101S 




11+10n 




0000 | r 


Rd* 


0000 


0000| r 


Rd*0 


0000 



















104 



Privileged OTDR (SOTDR) 

(Special), Output , Decrement and Repeat 



Example: In nonsegmented mode, if register Rll contains %0FFF, register R12 contains 

%B006, and R13 contains 6, the instruction 

OTDR @R11, @R12, R13 

will output the string of words from locations %B006 to %AFFC (in descending 
order of address) to port %0FFF. R12 will contain °/oAFFA ; and R13 will contain 0. 
Rll will not be affected. The V flag will be set. In segmented mode, R12 would be 
replaced by a register pair. 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of data elements transferred. 



105 



OUR (SOTIR) Privileged 

(Special) Output, Increment and Repeat 



Operation: 



OTIR dst, src, r 




dst: 


IR 




OTIRB 




src: 


IR 




SOTIR 










SOTIRB 










dst -«- src 










AUTOINCREMENT 


src 


(by 1 if byte 


, by 2 if 


word) 


r «*- r - 1 










repeat until r = 











Flags: 



This instruction is used for block output of strings of data. OTIR and OTIRB are used 
for normal I/O operation; SOTIR and SOTIRB are used for special I/O operation. 
The contents of the memory location addressed by the source register are loaded 
into the I/O port addressed by the destination word register. I/O port addresses are 
16 bits. The source register is then incremented by one if a byte instruction, or by 
two if a word instruction, thus moving the pointer to the next element of the string in 
memory. The word register specified by "r" (used as a counter) is then decremented 
by one. The address of I/O port in the destination register is unchanged. The entire 
operation is repeated until the result of decrementing r is zero. This instruction can 
output from 1 to 65536 bytes or 32768 words (the value for r must not be greater than 
32768 for OTIR or SOTIR). 

This instruction can be interrupted after each execution of the basic operation. The 
program counter value of the start of this instruction is saved before the interrupt 
request is accepted, so that the instruction can be properly resumed. Seven more 
cycles should be added to this instruction's execution time for each interrupt request 
that is accepted. 

C: Unaffected 

Z: Undefined ' 

S: Unaffected 

V: Set 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Npnsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


OTIR @Rd, @Rsl, r 
OTIRB @Rd, @Rsl, r 
SOTIR @Rd, @Rsi , r 
SOTIRB @Rd, @Rsi, r 








11+10n 












001 1101 |w 


Rs * 


001S 






0011 101 |w 


Rs*0 


001S 




11 +10n 




0000J r 


Rd* 


0000 


0000 | r 


Rd * 


0000 





















106 



Privileged OTIR (SOTIR) 

(Special) Output, Increment and Repeat 



Example: In nonsegmented mode, the following sequence of instructions can be used to output 

a string of bytes to the specified I/O port. The pointers to the I/O port and the start 
of the source string are set, the number of bytes to output is set, and then the output 
is accomplished. 



LD 


Rl, #PORT 


LDA 


R2, SRCBUF 


LD 


R3, #LENGTH 


OTIRB 


@R1, @R2, R3 



In segmented mode, a register pair would be used instead of R2. 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n - number of data elements transferred. 



107 



OUT (SOUT) Privileged 
(Special) Output 



OUT dst, src 
OUTB 

SOUT dst, src 
SOUTB 



dst: IR, DA 
src: R 

dst: DA 
src: R 



Operation: dst -*- src 

The contents of the source register are loaded into the destination, an Output or 
Special Output port. OUT and OUTB are used for normal I/O operation; SOUT and 
SOUTB are used for special I/O operation. 



Flags: 


No flags affected 
















Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




OUT &Rd, Rs 
OUTB <&'Rd, Rbs 

OUT port, Rs 
OUTB port, Rbs 
SOUT port, Rs 
SOUTB port, Rbs 








10 
12 










IR: 


0011111 |w|Rd*o| Rs 


001 1 111 | w| Rd * Rs 


10 










DA: 




001 1 101 |w] Rs | 01 IS 






0011101 |w| Rs | 1 1 S 




12 




port 


port 





















Example: 



If register R6 contains %5252, the instruction 

OUT 0/0 1120, R6 
will output the value %5252 to the port %1120. 



108 



Privileged OUTD (SOUTD) 

(Special) Output and Decrement 



OUTD dst, src, r 
OUTDB 
SOUTD 
SOUTDB 



dst: IR 
src: IR 



Operation: dst -*- src 

AUTODECREMENT src (by 1 if byte, by 2 if word) 
r «*- r - 1 



Flags: 



This instruction is used for block output of strings of data. OUTD and OUTDB are 
used for normal I/O operation; SOUTD and SOUTDB are used for special I/O opera- 
tion. The contents of the memory location addressed by the source register are 
loaded into the I/O port addressed by the destination word register. I/O port 
addresses are 16 bits. The source register is then decremented by one if a byte 
instruction, or by two if a word instruction, thus moving the pointer to the previous 
element of the string in memory. The word register specified by u r" (used as a 
counter) is then decremented by one. The address of the I/O port in the destination 
register is unchanged. 

C: Unaffected 

Z: Undefined 

S: Unaffected 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


OUTD@Rd, @Rsi, r 
OUTDB @Rd, @Rsi, r 

SOUTD @Rd, @Rsi, r 
SOUTDB @Rd, @Rsi , r 








21 












0011101 |w 


Rs * 


101S 






001 1 1 01 |w 


Rs * 


1 01S 




21 




0000 | r 


Rd 


1000 


0000| r 


Rd 


1000 



















Example: 



In segmented mode, if register R2 contains the I/O port address %0030, register RR6 
contains % 12005552 (segment %12, offset %5552), the word at memory location 
% 12005552 contains %1234, and register R8 contains %1001, the instruction 

OUTD @R2, @RR6, R8 

will output the value %1234 to port %0030 and leave the value % 12005550 in RR6, 
and %1000 in R8. Register R2 will not be affected. The V flag will be cleared. In 
nonsegmented mode, a word register would be used instead of RR6. 



1: Word register in nonsegmented mode, register, pair in segmented mode. 



109 



OUTI (SOUTI) Privileged 
(Special) Output and Increment 



OUTI dst, src, r 
OUTIB 
SOUTI 
SOUTIB 



dst: IR 
src: IR 



Operation: dst -*- src 

AUTOINCREMENT'src (by 1 if byte, by 2 if word) 
r **- r — 1 

This instruction is used for block output of strings of data. OUTI and OUTIB are 
used for normal I/O operation; SOUTI and SOUTIB are used for special I/O opera- 
tion. The contents of the memory location addressed by the source register are 
loaded into the I/O port addressed by the destination word register. I/O port 
addresses are 16-bit. The source register is then incremented by one if a byte 
instruction, or by two if a word instruction, thus moving the pointer to the next ele- 
ment of the string in memory. The word register specified by u r'' (used as a counter) " 
is then decremented by one. The address of the I/O port in the destination register is 
unchanged. 

Flags: C: Unaffected 

Z: Undefined 
S: Unaffected 

V: Set if the result of decrementing r is zero; cleared otherwise 
D: Unaffected 
H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


OUTI @Rd, @Rsi, r 
OUTIB @Rd, @Rsl, r 
SOUTI @Rd, @Rsl,r 
SOUTIB @Rd, @Rsl, r 








21 












001 1 101|W 


Rs*0 


001S 






001 1 101 |w 


R»* 


001 s 




21 




OOOO'I r 


Rd*0 


1000 


| r 


Rd*0 


1000 



















110 



Privileged OUTI (SOUTI) 

(Special) Output and Increment 



Example: 



This instruction can be used in a "loop" of instructions which outputs a string of 
data, but an intermediate operation on each element is required. The following 
sequence outputs a string of 80 ASCII characters (bytes) with the most significant bit 
of each byte set or reset to provide even parity for the entire byte. Bit 7 of each 
character is initially zero. This example assumes nonsegmented mode. In segmented 
mode, R2 would be replaced with a register pair. 



LOOP: 



EVEN: 



DONE: 



LD 

LDA 

LD 


Rl, #PORT 
R2, SRCSTART 
R3, #80 


!load I/O address! 
!load start of string! 
! initialize counter! 


TESTB 

JR 

SETB 


@R2 

PE, EVEN 

@R2, #7 


!test byte parity! 
! force even parity! 


OUTIB 
JR 


@R1, @R2, R3 
NOV, LOOP 


! output next byte! 

! repeat until counter = 0! 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



Ill 



POP 

Pop 



POP dst, src 
POPL 



dst: R, IR, DA, X 
src: IR 



Operation: 



Flags: 



dst +- src 

AUTOINCREMENT src (by 2 if word, by 4 if long) 

The contents of the location addressed by the source register (a stack pointer) are 
loaded into the destination. The source register is then incremented by a value 
which equals the size in bytes of the destination operand, thus removing the top ele- 
ment of the stack by changing the stack pointer. Any register except RO (or RRO in 
segmented mode) can be used as a stack pointer. 

With the POPL instruction, the same register cannot be used in both the source and 
destination addressing fields. 

No flags affected 



Destination 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycles 



R: 



IR: 



DA: 



POP Rd, @Rsi 
POPL RRd, @Rsl 
POP@Rdi, @Rsi 
POPL @Rdi , @Rsi 
POP address, @Rsl 



POPL address, @Rsl 



|lo| 0101 1 1 |Rs * 0| Rd. | 




[ToJ i 01 1 | Rs * o\~ Rd ] 




00 010111 | Rs*0 JRd *0| 




00 010101 | Rs*0 | Rd =^0 | 




1 1 010111 | Rs^O | 0000 


address 



01 010101 Rs*0 0000 



8 
12 

12 
19 

16 



23 



I 


10| 0101 1 1 |Rs *o| Rd | 




10| 010101 |Rs *0| Rd | 




00 010111 | Rs*0 JRd * o| 




010101 | Rs*0 | Rd *0 | 




ss 


0l| 010111 


Rs*0 | 00 00 




segment 


offset 








0l| 010111 


Rs*0 | 0000 


SL 


1 segment 


0000 0000 




offset 






SS 


0l| 010101 


Rs*0 |0000 


segment 


offset 








0l| 0101 01 


Rs*0 | 0000 


SL 


1 segment 


0000 0000 




offset 



12 
12 
19 

16 
19 

23 
26 



112 



POP 

Pop 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


X: 


POP addr(Rd), @R s i 
POPL addr(Rd), @R S l 








16 
23 










1 | 01 01 1 1 | Rs*0 | Rd*0 




SS 


01 | 01 01 1 1 


Rs*0 Rd^O 


16 




address 


segment 


offset 




















SL 


0l| 010111 


Rs*0 | Rd*0 






1 segment 


0000 0000 


19 




offset 






















0l| 010101 | Rs*0 | Rd*0 




SS 


0l| 010101 


Rs*0 Rd*0 


23 




address 


segment 


offset 




















SL 


1 | 010101 


Rs*0 J Rd*0 






1 I segment 


0000 0000 


26 




offset 



















Example: 



In nonsegmented mode, if register R12 (a stack pointer) contains %1000, the word at 
location %1000 contains %0055, and register R3 contains %0022, the instruction 

POP R3, @R12 

will leave the value %0055 in R3 and the value %1002 in R12. In segmented mode, 
a register pair must be used as the stack pointer instead of R12. 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



113 



PUSH 

Push 



PUSH dst, src 
PUSHL 



dst: IR 

src: R, IM, IR, DA, X 



Operation: 



Flags: 



AUTODECREMENT dst (by 2 if word, by 4 if long) 

dst ««- src 

The contents of the destination register (a stack pointer) are decremented by a value 
which equals the size in bytes of the source operand. Then the source operand is 
loaded into the location addressed by the updated destination register, thus adding a 
new element to the top of the stack by changing the stack pointer. Any register 
except RO (or RRO in segmented mode) can be used as a stack pointer. 

With PUSHL, the same register cannot be used for both the source and destination 
addressing fields. 

No flags affected 



Source 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycles 



R: 



IM: 



IR: 



DA: 



PUSHGRdi, Rs 
PUSHL fcRdi, RRs 
PUSH.&Rdl, #data 

PUSH&Rdi, c«Rsi 
PUSHL C«Rdi, <?'Rsi 
PUSH a Rdi , address 



PUSHLORdi, address 



|l o| 01001 1 | Rd*0 | Rs 




|l o| 010001 | Rd*Q | Rs | 




1 001 101 | Rd*0 | 1 001 


data 




1 1 01001 1 | Rd*0 | Rs * o| 




|00| 1000 1 | Rd*0 |Rs * o| 




1 1 010011 | Rd*0 | 00 


address 



0101 0001 Rd*0 0000 



9 
12 

12 

13 
20 
14 



21 





10| 10011 | Rd*o| Rs | 




1o| 010001 | Rd*0 | Rs | 






0| 001101 | Rd*0 | 1001 




data 






00| 01001 1 | Rd*0 |Rs * 




00| 010001 | Rd*0 |Rs * o| 




ss 


1 1 010011 


Rd*0 | 0000 


segment 


offset 








1 1 01001 1 


Rd*0 | 0000 


SL 


1 | segment 


0000 0000 




offset 






SS 


1 1 10 01 


Rd*0 | 000 


segment 


offset 








1 | 1 0001 


Rd*0 |0000 


SL 


1 segment 


0000 00 00 




offset 



9 
12 

12 



20 



17 



13 - 



24 



114 



PUSH 

Push 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


X: 


PUSH @Rdl , addr(Rs) 
PUSHL@Rdl, addr(Rs) 








14 
21 










1 1 01001 1 | Rd*0 | Rs*0 




SS 


0l| 01001 1 


Rd*0 J Rs*0 


14 




address 


1 segment 


offset 




















SL 


0l| 01001 1 


Rd*0 | Rs*0 






1 J segment 


0000 0000 


17 




offset 






















1 1 010001 | Rd*0 | Rs*0 




SS 


1 1 010001 


Rd*0 J Rs*0 


21 




address 


J segment 


offset 




















SL 


0l| 010001 


Rd*0 | Rs*0 






1 segment 


0000 0000 


24 




offset 



















Example: 



In nonsegmented mode, if register R12 (a stack pointer) contains %1002, the word at 
location %1000 contains %0055, and register R3 contains %0022, the instruction 

PUSH @R12, R3 

will leave the value %0022 in location %1000 and the value % 1000 in R12. In 
segmented mode, a register pair must be used as the stack pointer instead of R12. 



Note 1: Word register is used in nonsegmented mode, register pair in segmented mode. 



115 



RES 

Reset Bit 



RES dst, src 
RESB 



dst: 


R, IR, DA, X 


src: 


IM 


or 




dst: 


R 


src: 


R 



Operation: dst(src) +- 

This instruction clears the specified bit within the destination operand without 
affecting any other bits in the destination. The source (the bit number) can be 
specified as either an immediate value (Static), or as a word register which contains 
the value (Dynamic). In the second case, the destination operand must be a register, 
and the source operand must be RO through R7 for RESB, or RO through R15 for 
RES. The bit number is a value from to 7 for RESB, or to 15 for RES, with 
indicating the least significant bit. 

Only the lower four bits of the source operand are used to specify the bit number for 
RES, while only the lower three bits of the source operand are used with RESB. 
When the source operand is an immediate value, the "src field" in the instruction 
format encoding contains the bit number in the lowest four bits for RES, or the 
lowest three bits for RESB. 

Flags: No flags affected 

Reset Bit Static 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


RES Rd, Jb 
RESB Rbd, #b 

RES @Rdi , #b 
RESB @Rdi , #b 

RES address, #b 
RESB address, #b 

RES addr(Rd), #b 
RESB addr(Rd), #b 








4 
11 

13 
14 








1()|l000l|w| Rd | b 


1 o|l l|w | Rd | b | 


4 


IR: 






00|l 000 l|w| Rd*0 | b 


00|l 000l|w| Rd*o | b | 


11 


DA: 










1 |l 00 l| w| 000 [ b 




SS 


0l|l 0001|W 


0000 b 


14 




address 


segment 


offset 


















• 


SL 


oi|i oooi|w 


0000 | b 






1 segment 


0000 0000 


16 




offset 




X: 
















01 |l 000 l|w| Rd*0 | b 




SS 


oi|i oooi|w 


Rd*0 | b 


14 




address 


segment 


offset 




















SL 


1 |l 000 1 |w 


Rd*0 | b 






1 segment 


0000 0000 


17 




offset 



















116 



RES 

Reset Bit 



Reset Bit Dynamic 


Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




RES Rd, Rs 
RESB Rbd, Rs 








10 










R: 




oo|ioooi|w 


0000 


Rs 






o o 1 1 oooi|w 


0000 


Rs 




10 




| Rd 


0000 


0000 


| Rd 


0000 


0000 



















Example: If register RL3 contains %B2 (10110010), the instruction 

RESB RL3, §\ 
will leave the value %B0 (10110000) in RL3. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



117 



RESFLG 

Reset Flag 



RESFLG flag 



flag: C, Z, S, P, V 



Operation: 



Flags: 



FLAGS (4:7) <*- FLAGS (4:7) AND NOT instruction (4:7) 

Any combination of the C, Z, S, P or V flags are cleared to zero if the corresponding 
bits in the instruction are one. If the bit in the instruction corresponding to a flag is 
zero, the flag will not be affected. All other bits in the FLAGS register are 
unaffected. Note that the P and V flags are represented by the same bit. 

There may be one, two, three, or four operands in the assembly language statement, 
in any order. 

C: Cleared if specified, unaffected otherwise 
Z: Cleared if specified, unaffected otherwise 
S: Cleared if specified, unaffected otherwise 
P/V: Cleared if specified, unaffected otherwise 
D: Unaffected 
H: Unaffected 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycles 



RESFLG flags 



10 001101 CZSP/V 001 1 



|lo|001 101 |C2SP/V| 001 1 | 



Example: If the C, S, and V flags are set (1) and the Z flag is clear (0), the statement 

RESFLG C, V 
will leave the S flag set (1), and the C, Z, and V flags cleared (0). 



118 



RET 

Return 



RETcc 



Operation: 



Nonsegmented 
if cc is true then 
PC *- @SP 
SP + SP + 2 



Segmented 

if cc is true then 

PC «- @SP 

SP «*- SP + 4 



This instruction is used to return to a previously executed procedure at the end of a 
procedure entered by a CALL or CALR instruction. If the condition specified by 
u cc" is satisfied by the flags in the FCW, then the contents of the location addressed 
by the processor stack pointer are popped into the program counter (PC). The next 
instruction executed is that addressed by the new contents of the PC. 1 . 
See list of condition codes. The stack pointer used is R15 in nonsegmented 
mode, or RR14 in segmented mode. If the condition is not satisfied, then the instruc- 
tion following the RET instruction is executed. If no condition is specified, the return 
is taken regardless of the flag settings. 



Flags: 


No flags affected 










Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 1 


Instruction Format 


Cycles 1 




RET cc 


1 




10/7 








1 o| 01 1 1 1 | 0000 | cc | 


|l o| 01 1 1 10 | oooo| cc | 


13/7 









Example: 



In nonsegmented mode, if the program counter contains %2550, the stack pointer 
(R15) contains %3000, location %3000 contains %1004, and the Z flag is clear, then 
the instruction 

RET NZ 

will leave the value %3002 in the stack pointer and the program counter will contain 
%1004 (the address of the next instruction to be executed). 



Note 1: The two values correspond to return taken and return not taken. 



119 



RL 

Rotate Left 



RL dst, src 
RLB 



dst: R 
src: IM 



Operation: Do src times: (src = 1 or 2) 

tmp «*- dst 
c +- tmp (msb) 
dst(O) ♦- tmp (msb) 
dst (n + 1) <*-*tmp (n) (for n = to msb - 1) 



Flags: 



Word 



Byte: EI^HZ 



^ 



? 



The contents of the destination operand are rotated left one bit position if the source 
operand is 1, or two bit positions if the source operand is 2. The most significant bit 
(msb) of the destination operand is moved to the bit position and also replaces the 
C flag. 

The source operand may be omitted from the assembly language statement and thus 
defaults to the value 1 . 

C: Set if the last bit rotated from the most significant bit position was 1; cleared 

otherwise 
Z: Set if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed 

during rotation; cleared otherwise 
D: Unaffected 
H: Unaffected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax^ 


Nonsegmented Mode 


Segmented Mode 


Instruction Format2 


Cycles3 


Instruction Format2 


Cycles3 


R: 


RL Rd ( #n 
RLBRbd, #n 




6/7 






|lo|l100l|w| Rd |oo|s|o| 


[lo|l100l|w| Rd |oo|s|o| 


6/7 









Example: 



If register RH5 contains /o88 (10001000), the statement 

RLB RH5 
will leave the value %11 (00010001) in RH5 and the Carry flag will be set to one. 



Note 1: n = source operand. 

Note 2: s = for rotation by 1 bit; s = 1 for rotation by 2 bits. 

Note 3: The given execution times are for rotation by 1 and 2 bits respectively. 



120 



RLC 

Rotate Left through Carry 



RLC 
RLCB 



dst: R 
src: IM 



Operation: Do src times: (src = 1 or 2) 

tmp ■*- c 
c ■*- dst (msb) 

dst (n + 1) *■- dst (n) (for n = msb- 1 to 0) 
dst (0) <+- tmp 



Flags: 



Word 



Byte: 



: Cq 



K 



vl 



kiHI 



^ 



The contents of the destination operand with the C flag are rotated left one bit posi- 
tion if the source operand is 1, or two bit positions if the source operand is 2. The 
most significant bit (msb) of the destination operand replaces the C flag and the 
previous value of the C flag is moved to the bit position of the destination during 
each rotation. 

The source operand may be omitted from the assembly language statement and thus 
defaults to the value 1. 

C: Set if the last bit rotated from the most significant bit position was 1 ; cleared 

otherwise 
Z: Set. if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed 

during rotation; cleared otherwise 
D: Unaffected 
H: Unaffected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax l 


Nonsegmented Mode 


Segmented Mode 


Instruction Format2 


Cycles3 


Instruction Format? 


Cycles3 




RLC Rd, #n 
RLCB Rbd, #n 




6/7 






R: 


|lo|l100l|w| Rd |lo|s|o| 


[lo|l100l|w| Rd |lOJs|o| 


6/7 











Example: 



If the Carry flag is clear ( = 0) and register R0 contains %800F (1000000000001111), 
the statement 

RLC R0,#2 

will leave the value %003D (0000000000111101) in R0 and clear the Carry flag. 



Note 1 
Note 2: 
Note 3; 



n = source operand. 

s = for rotation by 1 bit; s = 1 for rotation by 2 bits. 

The given execution times are for rotation by 1 and 2 bits respectively. 



121 



RLDB 

Rotate Left Digit 



RLDB link, src 



src: R 
link: R 



Operation: 



tmp (0:3) <*- link (0:3) 
link (0:3) *- src (4:7) 
src (4:7) +- src (0:3) 
src (0:3) ««- tmp (0:3) 



Flags: 



link 



T 



] C 



T 



The low digit of the link byte register is logically concatenated to the source byte 
register. The resulting three-digit quantity is rotated to the left by one BCD digit 
(four bits). The lower digit of the source is moved to the upper digit of the source; 
the upper digit of the source is moved to the lower digit of the link, and the lower 
digit of the link is moved to the lower digit of the source. The upper digit of the link 
is unaffected. In multiple-digit BCD arithmetic, this instruction can be used to shift 
to the left a string of BCD digits, thus multiplying, it by a power of ten. The link 
serves to transfer , digits between successive bytes of the string. This is analogous to 
the use of the Carry flag in multiple precision shifting using the RLC instruction. 

The same byte register must not be used as both the source and the link. 

C: Unaffected 

Z: Set if the link is zero after the operation; cleared otherwise 

S: Undefined 

V: Unaffected 

D: Unaffected 

H: Unaffected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




RLDB Rbl, Rbs 




9 






R: 


|10| 1 1.1 1 10 | Rbs | Rbl | 


|10| 1 1 11 10 | Rbs | Rbl | 


9 











122 



RLDB 

Rotate Left Digit 



Example: 



If location 100 contains the BCD digits 0,1 (00000001), location 101 contains 2,3 
(00100011), and location 102 contains 4,5 (01000101) 



100 



101 



EH 



102 



the sequence of statements 




LD 


R3,#3 


LD 


R2,#102 


CLRB 


RH1 


LOOP: 




LDB 


RL1,@R2 


RLDB 


RH1,RL1 


LDB 


@R2,RL1 


DEC 


R2 


DJNZ 


R3, LOOP 



!set loop counter for 3 bytes! 
!(6 digits)! 

•set pointer to low-order digits! 
! zero-fill low-order digit! 

!get next two digits! 

! shift digits left one position! 

! replace shifted digits! 

ladvance pointer! 

! repeat until counter is zero! 

will leave the digits 1,2 (00010010) in location 100, the digits 3,4 (00110100) in loca- 
tion 101, and the digits 5,0 (01010000) in location 102. 



100 [] 



101 



102 | s | o| 



In segmented mode, R2 would be replaced by a register pair. 



123 



RR 














Rotate Right 














RR dst, src 
RRB 




dst: 
src: 


R 
IM 




Operation: 


Do src 


: times: (src = 
tmp ««- dst 
c ««- tmp (0) 
dot (msb) •*- 
dst (n - 1) - 


1 or 2) 

tmp (0) 
•- tmp (n) (for n 




i to msb) 



Flags: 



Word: 



Byte: 



:L7 



U 



►0 



The contents of the destination operand are rotated right one bit position if the 
source operand is 1, or two bit positions if the source operand is 2. The least signifi- 
cant bit of the destination operand is moved to the most significant bit (msb) and 
also, replaces the C flag. 

The source operand may be omitted from the assembly language statement and thus 
defaults to the value 1. 

C: Set if the last bit rotated from the least significant position was 1 ; cleared 

otherwise 
Z: Set if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed 

during rotation; cleared otherwise 
D: Unaffected 
H: Unaffected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format l 


Cycles 2 


Instruction Format! 


Cycles 2 




RR Rd, #n 
RRB Rbd, #n 




6/7 






R: 


|lo|l100l|w| Rd |oi|s|o| 


|lo|l100l|w| Rd |oi|s|o| 


6/7 









Example: 



If register RL6 contains %31 (00110001), the statement 

RRB RL6 
will leave the value %98 (10011000) in RL6 and the Carry flag will be set to one. 



Note 1: s = for rotation by 1 bit; s = 1 for rotation by 2 bits. 

Note 2: The given execution times are for rotation by 1 and 2 bits respectively. 



124 



RRC 

Rotate Right through Carry 



RRC dst, src 
RRCB 



dst: R 
src: IM 



Operation: Do src times: (src = 1 or 2) 

tmp '*- c 
c +- dst (0) 

dst (n) +- dst (n + 1) (for n = to msb - 1) 
dst (msb) «*- tmp 



Flags: 



Word:. 



Byte: 



G 



EF 



c± 



(7p 



The contents of the destination operand with the C flag are rotated one bit position if 
the source operand is 1, or two bit positions if the source operand is 2. The least 
significant bit of the destination operand replaces the C flag and the previous value 
of the C flag is moved to the most significant bit (msb) position of the destination 
during each rotation. 

The source operand may be omitted from the assembly language statement and thus 
defaults to the value 1 . 

C: Set if the last bit rotated from the least significant bit position was 1; cleared 

otherwise 
Z: Set if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed 

during rotation; cleared otherwise 
D: Unaffected 
H: Unaffected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 1 


Cycles* 


Instruction Format 1 


Cycles* 




RRC Rd, #n 
RRCB Rbd, #n 




6/7 








|io|nooi|w| Rd |n|s|o| 


|lo|l100l|w| Rd |n|s|o| 


6/7 











Example: 



If the Carry flag is clear ( =0) and the register R0 contains %00DD 
(0000000011011101), the statement 

RRC R0,#2 

will leave the value %8037 (10000000110111) in R0 and clear the Carry flag. 



Note 1 : s = for rotation by 1 bit; s = 1 for rotation by 2 bits 

Note 2: The given execution times are for rotation by 1 and 2 bits respectively. 



125 



RRDB 

Rotate Right Digit 



RRDB link, src 



src: R 
link: R 



Operation: 



tmp (0:3) «- link (0:3) 
link (0:3) •«- src (0:3) - 
src (0:3) «- src (4:7) 
src (4:7) +- tmp (0:3) 



Flags: 



link [_ 



T 



] 



The low digit of the link byte register is logically concatenated to the source byte 
register. The resulting three-digit quantity is rotated to the right by one BCD digit 
(four bits). 

The lower digit of the source is moved to the lower digit of the link; the upper digit 
of the source is moved to the lower digit of the source and the lower digit of the link 
is moved to the upper digit of the source. 

The upper digit of the link is unaffected. In multiple-digit BCD arithmetic, this 
instruction can be used to shift to the right a string of BCD digits, thus dividing it by 
a power of ten. The link serves to transfer digits between successive bytes of the 
string. This is analogous to the use of the carry flag in multiple precision shifting 
using the RRC instruction. 
The same byte register must not be used as both the source and the link. 

C: Unaffected 

Z: Set if the link is zero after the operation; cleared otherwise 

S: Undefined 

V: Unaffected 

D: Unaffected 

H: Unaffected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




RRDB Rbl, Rbs 




9 






R: 


|lo| 1 1 1 100 | Rbs | Rbl | 


|lo| 1 1 1 100 | Rbs | Rbl | 


9 









126 



RRDB 

Rotate Right Digit 



Example: If location 100 contains the BCD digits 1,2 (00010010), location 101 contains 3,4 

(00110100), and location 102 contains 5,6 (01010110) 



100 



L 



101 



EH 



102 



LOOP: 



LD 


R2,100 


CLRB 


RH1 


LDB 


RL1,@R2 


RRDB 


RH1,RL1 


LDB 


@R2,RL1 


INC 


R2 


DJNZ 


R3 ; LOOP 



the sequence of statements 

LD R3,#3 !set loop counter for 3 bytes (6 

digits)! 

!set pointer to high-order digits! 
! zero-fill high-order digit! 

!get next two digits! 

! shift digits right one position! 

! replace shifted digits! 

(advance pointer! 

! repeat until counter is zero! 

will leave the digits 0,1 (00000001) in location 100, the digits 2,3 (00100011) in loca- 
tion 101, and the digits 4,5 (01000101) in location 102. RH1 will contain 6 ; the 
remainder from dividing the string by 10. 



100 



EH 



101 



102 



EH 



In segmented mode, R2 would be replaced by a register pair. 



127 



SBC 

Subtract with Carry 



SBC dst, src 
SBCB 



dst: R 
src: R 



Operation: 



Flags: 



dst -*- dst - src - C 

The source operand, along with the setting of the carry flag, is subtracted from the 
destination operand and the result is stored in the destination. The contents of the 
source are not affected. Subtraction is performed by adding the two's complement of 
the source operand to the destination operand. In multiple precision arithmetic, this 
instruction permits the carry ("borrow") from the subtraction of low-order operands 
to be subtracted from the subtraction of high-order operands. 

C: Cleared if there is a carry from the most significant bit of the result; set 

otherwise, indicating a "borrow" 
Z: Set if the result is zero; cleared otherwise 
S: Set if the result is negative; cleared otherwise 
V: Set if arithmetic overflow occurs, that is, if the operands were of opposite signs 

and the sign of the result is the same as the sign of the source; cleared otherwise 
D: SBC— unaffected; SBCB— set 
H: SBC — unaffected; SBCB — cleared if there is a carry from the most significant bit 

of the low-order four bits of the result; set otherwise, indicating a "borrow" 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




SBC Rd, Rs 
SBCB Rbd, Rbs 




5 






R: 


|l0|l101l|w| Rs | Rd | 


|lo|l101l|w| Rs | Rd | 


5 











Example: 



Long subtraction may be done with the following instruction sequence, assuming RO, 
Rl contain one operand and R2, R3 contain the other operand: 

SUB R1,R3 {subtract low-order words! 

SBC R0,R2 [subtract carry and high-order words! 

If RO contains %0038, Rl contains %4000, R2 contains %000A and R3 contains 
%F000, then the above two instructions leave the value %002D in RO and %5000 
inRl. 



128 



Privileged 



sc 

System Call 



SC src 



src: IM 



Operation: 



Nonsegmented 
SP *- SP - 4 
@SP~- PS 
SP^- SP - 2 
@SP '-*- instruction 
PS -+- System Call PS 



Segmented 
SP ^- SP - 6 
@SP -«- PS 
SP *- SP - 2 
@SP -*- instruction 
PS +- System Call PS 



This instruction is used for controlled access to operating system software in a man- 
ner similar to a trap or interrupt. The current program status (PS) is pushed on the 
system processor stack, and then the instruction itself, which includes the source 
operand (an 8-bit value) is pushed. The PS includes the Flag and Control Word 
(FCW), and the updated program counter (PC). (The updated program counter 
value used is the address of the first instruction byte following the SC instruction.) 

The system stack pointer is always used (R15 in nonsegmented mode, or RR14 in 
segmented mode), regardless of whether system or normal mode is in effect. The 
new PS is then loaded from the Program Status block associated with the System 
Call trap (see section 6.2.4), and control is passed to the procedure whose address is 
the program counter value contained in the new PS. This procedure may inspect the 
source operand on the top of'the stack to determine the particular software service 
desired. 

The following figure illustrates the format of the saved program status in the system 
stack: 



N 


ONSEGMENTE 




LOW 
ADDRESS 

HIGH 
ADDRESS 


SP AFTER »► 

SP BEFORE *~ 


SEGMENTED 


LOW 
ADDRESS 


STACK POINTER 
AFTER TRAP ■» 


IDENTIFIER 




IDENTIFIER 


FCW 






FCW 


PC SEGMENT 






PC 


PC OFFSET 




BEFORE TRAP »► 

OR INTERRUPT 








*-1 WORD-*- 


-*-1 WORD-** 


HIGH 
ADDRESS 



Flags: 



The Z8001 version always executes the segmented mode of the System Call instruc- 
tion, regardless of the current mode, and sets the Segmentation Mode bit (SEG) to 
segmented mode ( = 1) at the start of the SC instruction execution. Both the Z8001 
and Z8002 versions set the System/Normal Mode bit (S/N) to system mode ( = 1) at 
the start of the SC instruction execution. The status pins reflect the setting of these 
control bits during the execution of the SC instruction. However, the setting of SEG 
and S/N does not affect the value of these bits in the old FCW pushed onto the stack. 
The new value of the FCW is not effective until the next instruction, so that the status 
pins will not be affected by the new control bits until after the SC instruction execu- 
tion is completed. 

The "src field" in the instruction format encoding contains the source operand. The 
u src field" values range from to 255 corresponding to the source values to 255. 

No flags affected 

Flags loaded from Program Status Area 



129 



sc 

System Call 



Privileged 



Source 

Addressing 

Mod* 




Nonsegmented Mode 


Segmented Mode 


Syntax 


Instruction Format 


Cycles 


Instruction Format 


Cycles 




SC #src 




33 






IM: 


| 1 1 1 1 1 1 1 | src | 


| 1 1 1 1 1 1 1 | src | 


39 











Example: 



In the nonsegmented Z8002, if the contents of the program counter are %1000, the 
contents of the system stack pointer (R 15) are %3006, and the Program Counter and 
FCW values associated with the System Call trap in the Program Status Area are 
%2000 and °/olOOO, respectively, the instruction 

SC #3 ! system call, request code = 3! 

causes the system stack pointer to be decremented to %3000. Location %3000 con- 
tains %7F03 (the SC instruction). Location %3002 contains the old FCW, and loca- 
tion %3004 contains /ol002 (the address of the instruction following the SC instruc- 
tion). System mode is in effect, and the Program Counter contains the value %2000, 
which is the start of a System Call trap handler, and the FCW contains %1000. 



130 



SDA 

Shift Dynamic Arithmetic 



SDA dst, src 

SDAB 

SDAL 



dst: R 
src: R 



Operation: 



Flags: 



Right (src negative) 
Do src times: 

c *- dst (0) 

dst (n) *- dst (n + 1) (for n = to msb - 1) 

dst (msb) *- dst (msb) 
Left (src positive) 
Do src times: 

c <*- dst (msb) 

dst (n + 1) ♦- dst (n) (for n = msb - 1 to 0) 

dst (0) <*- 



Right 



Left 



Byte: 



& 



md eh: 



H° 



Word: 



: & 



3-0 E-C 



Long: r*\ 



Cr 



5 



eh: 



MD 



3— 



n = 0,2,4 14 



n = 0,2,4 14 



The destination operand is shifted arithmetically left or right by the number of bit 
positions specified by the contents of the source operand, a word register. 

The shift count ranges from -8 to +8 for SDAB, from -16 to + 16 for SDA and from 
-32 to +32 for SDAL. If the value is outside the specified range, the operation is 
undefined- The source operand is represented as a 16-bit two's complement value. 
Positive values specify a left shift, while negative values specify a right shift. A shift 
of zero positions does not affect the destination; however, the flags are set according 
to the destination value. The sign bit is replicated in shifts to the right, and the C 
flag is loaded from bit of the destination. The least significant bit is filled with in 
shifts to the left, and the C flag is loaded from the most significant bit (msb) of the 
destination. The setting of the carry bit is undefined for zero shift. 

C: Set if the last bit shifted from the destination was 1 , undefined for zero shift; 

cleared otherwise 
Z: Set if the result is zero; cleared otherwise 
S: Set if the result is negative; cleared otherwise 
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed 

during shifting; cleared otherwise 
D: Unaffected 
H: Unaffected 



13! 



SDA 

Shift Dynamic Arithmetic 



Destination 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 1 



Segmented Mode 



Instruction Format 



Cycles 1 



SDA Rd, Rs 



SDAB Rbd, Rs 



SDAL RRd, Rs 



1 | 110011 


Rd | 1 1 1 


000 | Rs 


0000 0000 




1 | 1 1 1 


Rd 10 11 


000 | Rs 


0000 0000 




1 o| 1 1001 1 


Rd | 1 1 1 1 


| Rs 


0000 0000 



15 + 3n 



15 + 3n 



15 + 3n 



1 | 110011 


Rd | 1 1 1 


000 | Rs 


0000 0000 




1 | 110010 


Rd | 1 1 1 


000 | Rs 


0000 0000 




1 o| 110011 


Rd | 1 1 1 1 


000 | Rs 


0000 0000 



15 + 3n 



15 + 3n 



15 + 3n 



Example: If register R5 contains %C705 (1100011100000101) and register Rl contains -2 

(%FFFE or 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10), the statement 

SDA R5,R1 

performs an arithmetic right shift of two bit positions, leaves the value %F1C1 
(1111000111000001) in R5, and clears the Carry flag. 

Note 1: n = number of bit positions; the execution time for n =0 is the same as for n = 1. 



132 



SDL 

Shift Dynamic Logical 



SDL dst, src 

SDLB 

SDLL 



dst: R 
src: R 



Operation: 



Flags: 



Right 

Do src times 

c *•- dst (0) 

dst (n) **- dst (n + 1) (for n = to msb - 1) 

dst (msb) *- 

Left 

Do src times 

c -*- dst (msb) 

dst (n + 1) ««- dst (n) (for n = msb - 1 to 0) 

dst (0) — 



Right 



Left 



Byte: „-*► |_ \— 


15 







Word: o-H.| [— . 


15 







Long: o — »-| 


Rn 


h 




1 ' 5 







L l 


Rn + 1 


h 



me eh: 



h° 



H3 EM 



H° 



EMC 



k 



]_. 



n = 0,2,4 14 



11 = 0,2,4 14 



The destination operand is shifted logically left or right by the number of bit posi- 
tions specified by the contents of the source operand, a word register. The shift 
count ranges from -8 to +8 for SDL, from -16 to + 16 for SDLB and from -32 to 
+ 32 for SDLL. If the value is outside the specified range, the operation is 
undefined. The source operand is represented as a 16-bit two's complement value. 
Positive values specify a left shift, while negative values specify a right shift. A shift 
of zero positions does not affect the destination; however, the flags are set according 
to the destination value. The most significant bit (msb) is filled with in shifts to the 
right, and the C flag is loaded from bit of the destination. The least significant bit 
is filled with in shifts to the left, and the C flag is loaded from the most significant 
bit of the- destination. The setting of the carry bit is undefined for zero shift. 

C: Set if the last bit shifted from the destination was 1 , undefined for zero shift; 

cleared otherwise 
Z: Set if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 
V: Undefined 
D: Unaffected 
H: Unaffected 



133 



SDL 

Shift Dynamic Logical 



Destination 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycles 



R: 



SDLRd, Rs. 



SDLB Rbd, Rs 



SDLL RRd, Rs 



1 o| 1 1 001 1 


Rd | 00 11 


0000 | Rs 


00 0000 




1 o| 1 1001 


Rd | 1 1 


000 | Rs 


0000 0000 




1 o| 110011 


Rd I 1 1 1 


| Rs 


0000 0000 



15 + 3n 



15 + 3n 



1 | 110011 


Rd | 1 1 


00 | Rs 


0000 0000 




1 | 110 10 


Rd | 1 1 


00 | Rs 


0000 0000 




1 | 110011 


Rd | 1 1 1 


00 | Rs 


0000 oooo 



15 + 3n 



15 + 3n 



Example: If register RL5 contains %B3 (10110011) and register Rl contains 4 

(0000000000000100), the statement 

SDLB RL5,R1 
performs a logical left shift of four bit positions, leaves the value %30 (00110000) in 
RL5, and sets the Carry flag. 



Note"!: n = number of bit positions; the execution time for n = is the same as for n = 1. 



134 



SET 

Set Bit 



SET cist, src 
SETB 



dst: R, IR, DA, X 

src: IM 

or 

dst: R 

src: R 



Operation: 



dst(src) -«- 1 



Sets the specified bit within the destination operand without affecting any other bits 
in the destination. The source (the bit number) can be specified as either an immedi- 
ate value (Static), or as a word register which contains the value (Dynamic). In the 
second case, the destination operand must be a register, and the source operand 
must be RO through R7 for SETB, or RO through R15 for SET. The bit number is a 
value from to 7 for SETB or to 15 for SET, with indicating the least significant 
bit. 

Only the lower four bits of the source operand are used to specify the bit number for 
SET, while only the lower/three bits of the source operand are used with SETB. 
When the source operand is an immediate value, the n src field" in the instruction 
format encoding contains the bit number in the lowest four bits for SET, or the 
lowest three bits for SETB. 



Flags: 



No flags affected 



Set Bit Static 


















Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


SET Rd, #b 
SETB Rbd, #b 

SET @Rdi, #b 
SETB @Rdi , #b 

SET address, #b 
SETB address, #b 

SET addr(Rd), #b 
SETB addr(Rd), #b 






I 


4 
11 

13 
14 








1 o|i 0.01 o|w| Rd | b 


1 |l 00 1 o|w| Rd | b | 


4 


IR: 








00|l 001 o|w| Rd*0 | b 


00|l 0010|w| Rd*0 | b | 


11 


DA: 










o 1 1 1 001 o|w| 0000 | b 




SS 


01 |i 001 o|w 


oooo| b 


14 




address 


segment 


offset 




















SL 


oi|i ooio|w 


0000| b 






1 I segment 


0000 0000 


16 




offset 




X: 
















0l|l001o|w| Rd*0 | b 




SS 


oi|iooio|w 


Rd * | b 


14 




address 


segment 


offset 




















SL 


01 |i 001 o|w 


Rd*o| b 






1 I segment 


0000 0000 


17 




offset 



















135 



SET 

Set Bit 



Set Bit Dynamic 






















Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


SET Rd, Rs 
SETB Rbd, Rs 








10 












oo|iooio|w 


00 | Rs 






oo|iooio|w 


| Rs 




10 




| Rd 


0000 0000 


0000 | Rd 


0000 0000 



















Example: 



If register RL3 contains %B2 (10110010) and register R2 contains the value 6, the 
instruction 

SETB RL3, R2 

will leave the value %F2 (11110010) in RL3. 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



136 



Operation: 



Flags: 



SETFLG 

Set Flag 



SETFLG flag 



Flag: C, Z, S, P, V 



FLAGS (4:7) *- FLAGS (4:7) OR instruction (4:7) 

Any combination of the C, Z, S, P or V flags are set to one if the corresponding bits 
in the instruction are one. If the bit in the instruction corresponding to a flag is zero, 
the flag will not be affected. All other bits in the FLAGS register are unaffected. 
Note that the P and V flags are represented by the same bit. 

There may be one, two, three, or four operands in the assembly language statement, 
in any order. 

C: Set if specified; unaffected otherwise 
Z: Set if specified; unaffected otherwise 
S: Set if specified; unaffected otherwise 
P/V: Set if specified; unaffected otherwise 
D: Unaffected 
H: Unaffected 





Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 




Instruction Format 


Cycles 


Instruction Format 


Cycles 




SETFLG flags 




7 








| 10001101 |czsp/v| 0001 | 


| 10001101 |czsp/v| 0001 | 


7 



Example: If the C, Z, and S flags are all clear (0),and the P flag is set (1), the statement 

SETFLG C 
will leave the C and P flags set (1), and the Z and S flags cleared (0). 



137 



SLA 

Shift Left Arithmetic 



SLA dst, src dst: R 

SLAB src: IM 

SLAL 



Operation: Do src times: 

c -*- dst (msb) 

dst (n + 1) *- dst (n) (for n = msb - 1 to 0) 

dst (0) «- 



Byte: [[]— £ 



Word: | c |-^ 




I—' 


15 







Lona: I c M 


Rn 


l-i 


I 


I " 







H 


Rn + 1 


I— 



n = 0, 2, 4 14 

The destination operand is shifted arithmetically left the number of bit positions 
specified by the source operand. For SLAB, the source is in the range to 8; for 
SLA, the source is in the range to 16; for SLAL, the source is in the range to 32. 
A shift of zero positions does not affect the destination; however, the flags are set 
according to the destination value. The least significant bit of the destination is filled 
with 0, and the C flag is loaded from the sign bit of the destination. The operation is 
the equivalent of a multiplication of the destination by a power of two with overflow 
indication. 

The src field is encoded in the instruction format as the 8- or 16-bit two's comple- 
ment positive value of the source operand. For each operand size, the operation is 
undefined if the source op and is not in the specified range. 

The source operand may be omitted from the assembly language statement and thus 
defaults to the value 1 . 

Flogs: C: Set if the last bit shifted from the destination was 1 , undefined for zero shift; 

cleared otherwise 
Z: Set if the result is zero; cleared otherwise 
S: Set if the result is negative; cleared otherwise 
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed 

during shifting; cleared otherwise 
D: Unaffected 
H: Unaffected 



138 



SLA 

Shift Left Arithmetic 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 1 


Instruction Format 


Cycles^ 


R: 


SLA Rd, §b 
SLAB Rbd, #b 
SLAL RRd, #b 








13 + 3b 
13 + 3b 
13 + 3b 












1 1 1 1 1 1 | Rd | 1 00 1 






1 1 1 1 1 1 | Rd | 1 001 




13 + 3b 




b 


b 
























1 o] 1 10010 


Rd 1 1 1 






1 | 110010 


Rd 


1001 




13 + 3b 







b 





b 
























1 | 1 1 1 1 | Rd | 1 1 1 






1 | 1 1 1 1 | Rd | 1 1 1 




13 + 3b 




b 


b 





















Example: If register pair RR2 contains %1234ABCD, the statement 

SLAL RR2,#8 
will leave the value %34ABCD00 in RR2 and clear the Carry flag. 

Note 1: b = number of bit positions; the execution time for b = is the same as for b = 1. 



139 



SLL 

Shift Left Logical 





SLL dst, src dst: R 




SLB src: IM 




SLLL 


Operation: 


Do src times: 




c -*- dst (msb) 




dst (n- + 1) ■+- dst (n) (for n = msb 




dst (0) - 

7 




Byte: |c |-^-| |^— o 



1 toO) 



Word: | c |^— | 




h- 


15 







Long: | C .HH 


Rn 


hn 


I 


| 15 







H 


Rn + 1 


b-° 



n =. 0, 2, 4, ..., 14 

The destination operand is shifted logically left by the number of bit positions 
specified by the source operand. For SLLB, the source is in the range to 8; for 
SLL, the source is in the range to 16; for SLLL, the source is in, the range to 32. 
A shift of zero positions does not affect the destination; however, the flags are set 
according to the destination value. The setting of the carry bit is undefined for zero 
shift. The least significant bit of the destination is filled with 0, and the C flag is 
loaded from the most significant bit (msb) of the destination. This instruction per- 
forms an unsigned multiplication of the destination by a power of two. 

The src field is encoded in the instruction format as the 8- or 16-bit positive value of 
the source operand. For each operand size, the operation is undefined if the source 
operand is not in the specified range. 

The source operand may be omitted from the assembly language statement and thus 
defaults to the value 1. 

Flags: C: Set if the last bit shifted from the destination was 1 , undefined for zero shift; 

cleared otherwise 

Z: Set if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 
V: Undefined 
D: Unaffected 
H: Unaffected 



140 



SLL 

Shift Left Logical 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 1 


Instruction Format 


Cycles 1 


R: 


SLL Rd, #b 
SLLB Rbd, #b 
SLLL RRd, #b 








13 + 3b 
13 + 3b 
13 + 3b 












1 | 1 1 1 1 | Rd | 000 1 






1 | 1 1 1 1 | Rd | 1 




13 + 3b 




b 


b 
























1 | 1 10010 


Rd | 1 






1 | 1 10010 


Rd | 1 




13 + 3b 







b 





b 
























1 1 1 1 1 1 | Rd | 1 1 






1 | 1 1 1 1 | Rd | 1 1 




13 + 3b 




b 


b 





















Example: If register R3 contains %4321 (0100001100100001), the statement 

SLL R3,#l 
-will leave the value %8642 (1000011001000010) in R3 and clear the carry flag. 

Note 1: b = number of bit positions; the execution time for b =0 is the same as for b = 1. 



141 



SRA 

Shift Right Arithmetic 



SRA dst, src dst: R 

SRAB src: IM 

SRAL 



Operation: Do src times: 

c -*- dst (0) 

dst (n) -«- dst (n + l)(for n = to msb 

dst'(msb) -*- dst (msb) 



Byte: H | h ^R 

15 

Word: H I h — Fl 



Long: r-**[ 



& 



c? 



D-a 



n = 0, 2, 4, ..., 14 

The destination operand is shifted arithmetically right by the number of bit positions 
specified by the source operands. For SRAB, the source is in the range to 8; for 
SRA, the source is in the range to 16; for SRAL, the source is in the range to 32. 
A right shift of zero for SRA is not possible. The most significant bit (msb) of the 
destination is replicated, and the C flag is loaded from bit of the destination, this 
instruction performs a signed division of the destination by a power of two. 

The src field is encoded in the instruction format as the 8- or 16-bit two's comple- 
ment negative of the source operand. For each operand size, the operation is 
undefined if the source operand is not in the specified range. 

The source operand may be omitted from the assembly language statement and thus 
defaults to the value 1 . 

Flags: C: Set if the last bit shifted from the destination was 1 ; cleared otherwise 

Z: Set if the result is zero; cleared otherwise 
S: Set if the result is negative; cleared otherwise 
V: Cleared 
D: Unaffected 
H: Unaffected 



142 



SRA 

Shift Right Arithmetic 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 1 


Instruction Format 


Cycles 1 


R: 


SRA Rd, #b 
SRAB Rbd, #b 
SRAL RRd, #b 








13 + 3b 
13 + 3b 
13 + 3b 












1 | 1 1 1 1 | Rd | 1 1 






1 | 1 1 1 1 | Rd | 10 1 




13 + 3b 




-b 


-b 






















10 


1 10010 


Rd | 1001 






1 | 1 10010 


Rd | 1 1 




13 + 3b 







-b 





-b 






















1 | 1 1 1 1 | Rd | 1 1 .0 1 






1 | 1 1 1 1 | Rd | 1 1 1 




13 + 3b 




-b 


-b 



















Example: If register RH6 contains %3B (00111011), the statement 

SRAB RH6,#2 
will leave the value %0E (00001110) in RH6 and set the carry flag. 

Note 1: b = number of bit positions; the execution time for b = is the same as for b = 1. 



143 



SRL 

Shift Right Logical 



SRL dst, src dst: R 

SRLB src: IM 

SRLL 



Operation: Do src times: 

c -+- dst (0) 



dst (n) ■+- dst (n + l)(for n = to msb 
dst (msb) +- 



Byte: o-^ | V ^Fl 

15 

Word: o- H h -^FI 



Long: °-*"L 



Lr 



^ 



ihu 



n = 0, 2, 4 14 

The destination operand is shifted logically right by the number of bit positions 
specified by the source operand. For SRLB, the source operand is in the range to 
8; for SRL, the source is in the range to 16; for SRLL, the source is in the range 
to 32. A right shift of zero for SRL is not possible. The most significant bit (msb) of 
the destination is filled with 0, and the C flag is loaded from bit of the destination. 
This instruction performs an unsigned division of the destination by a power of two. 

The src field is encoded in the instruction format as the 8- or 16-bit negative value of 
the source operand in two's complement rotation. For each operand size, the opera- 
tion is undefined if the source operand is not in the range specified above. 

The source operand may be omitted from the assembly language statement and thus 
defaults to the value of 1 . 

Flags: C: Set if the last bit shifted from the destination was 1 ; cleared otherwise 

Z: Set if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is one; cleared otherwise 
V: Undefined 
D: Unaffected 
H: Unaffected 



144 



SRL 

Shift Right Logical 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 1 


Instruction Format 


Cycles 1 




SRL Rd, #b 
SRLB Rbd, #b 
SRLL RRd, #b 








13 + 3b 
13 + 3b 
13 + 3b 










R: 




1 | 1 1 1 1 | Rd | 000 1 






1 | 1 1 1 1 | Rd | 000 1 




13 + 3b 




-b 


-b 






















1 | 110010 


Rd | 1 






1 o| 1 1 0010 


Rd | 0001 




13 + 3b 







-b 





-b 






















1 o| 1 100 1 1. | Rd | 0101 






10|l1001l| Rd | 1 1 




13 + 3b 




-b 


-b 





















Example: If register R0 contains %1111 (0001000100010001), the statement 

SRL R0,#6 
will leave the value %0044 (0000000001000100) in R0 and clear the carry flag. 

Note 1 : b = number of bit positions; the execution time for b = is the same as for b = 1 . 



145 



SUB 

Subtract 



SUB dst, src 

SUBB 

SUBL 



dst: R 

src: R, IM, IR, DA, X 



Operation: 



Flags: 



dst «*- dst - src 

The source operand is subtracted from the destination operand and the result is 
stored in the destination. The contents of the source are not affected. Subtraction is 
performed by adding the two's complement of the source operand to the destination 
operand. 

C: Cleared if there is a carry from the most significant bit; set otherwise, indicating 

a "borrow" 
Z: Set if the result is zero; cleared otherwise 
S: Set if the result is negative; cleared otherwise 
V: Set if arithmetic overflow occurs, that is, if the operands were of opposite signs 

and the sign of the result is the same as the sign of the source; cleared otherwise 
D: SUB, SUBL— unaffected; SUBB— set 
H: SUB, SUBL — unaffected; SUBB — cleared if there is a carry from the most 

significant bit of the low-order four bits of the result; set otherwise, indicating a 

"borrow" 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


SUB Rd, Rs 
SUBB Rbd, Rbs 

SUBL RRd, RRs 
SUB Rd, #data 

SUBB Rbd, #data 

SUBL RRd, #data 

SUB Rd, @Rsl 
SUBB Rbd, @Rsl 

SUBL RRd, @Rsi 










4 
8 

7 
7 

14 

7 
14 












,0 


0000l|w| Rs | Rd 


,» 


0000l|w| Rs | Rd 


4 
















,0 


1001 | RRs | RRd 


,0 


0100 10 | RRs | RRd 


8 














IM: 




00 


0000 10 | 0000 | Rd 






00 


000010|0000| Rd 




7 




data 


data 


























00 


00001 1 


| Rd 






00 


00001 1 


| Rd 




7 




data 


data 


data 


data 


























00 


010010 | O0OOJ Rd 






00 


010010 I 00Q0| Rd 








31 


data (high) 15 


31 


data (high) 16 


14 




15 


data (low) 


15 


data (low) 




IR: 




















00 


0000l|w| Rs*0 | Rd 


00 


0000l|w| Rs*0 | Rd 


7 
















00 


010010 | Rs*0 | Rd 


00 


01 0010 | Rs*0 | Rd 


14 



















146 



SUB 

Subtract 



Source 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycles 



DA: 



X: 



SUB Rd, address 
SUBB Rbd, address 



01 00001 W 0000 Rd 



SUBL RRd, address 



01010010 0000 Rd 



15 



SUB Rd, addr(Rs) 
SUBB Rbd, addr(Rs) 



0100001WRs*0 Rd 



10 



SUBL RRD, addr(Rs) 



1 10010 Rs*0 Rd 



16 



ss 


1 |o o o i|w 


| Rd 


segment 


offset 








oi|ooooi[w 


oj Rd 


SL 


1 segment 


0000 0000 




offset 






SS 


01 I 010010 


000 | Rd 


segment 


offset 








01010010 


| Rd 


SL 


1 segment 


0000 0000 




offset 






SS 


oi|ooooi|w 


Rs*0 | Rd 


segment 


offset 








1 |oo 00 l| W 


Rs*0 | Rd 


SL 


1 I segment 


0000 0000 




offset 






SS 


01I01 001 


Rs*0 | Rd 


segment 


offset 








1 1 10 10. 


Rs*0 | Rd 


SL 


1 segment 


0000 0000 




offset 



10 



12 



16 



18 



10 



13 



16 



19 



Example: If register R0 contains °/o0344, the statement 

SUB R0,#%AA 
will leave the value %029A in R0. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



147 



TCC 

Test Condition Code 



TCC cc, dst 
TCCB 



dst: R 



Operation: 



if cc is satisfied then 

dst (0) «•- 1 



Flags: 



This instruction is used to create a Boolean data value based on the flags set by a 
previous operation. The flags in the FCW are tested to see if the condition specified 
by u cc" is satisfied. If the condition is satisfied, then the least significant bit of the 
destination is set. If the condition is not satisfied, bit zero of the destination is not 
cleared but retains its previous value. All other bits in the destination are unaffected 
by this instruction. 

No flags affected 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


TCC cc, Rd 
TCCB cc, Rbd 




5 






|lo|l011l|w| Rd | cc | 


|lo|l011l|w| Rd | cc | 


5 











Example: 



If register Rl contains 0, and the Z flag is set, the statement 

TCC EQ,R1 
will leave the value 1 in Rl. 



148 



TEST 

Test 



TEST dst 

TESTB 

TESTL 



dst: R, IR, DA, X 



Operation: 



dst OR 



Flags: 



The destination operand is tested (logically ORed with zero), and the Z, S and P 
flags are set to reflect the attributes of the result. The flags may then be used for 
logical conditional jumps. The contents of the destination are not affected. 

C: Unaffected 

Z: Set if the result is zero; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 

P: TEST — unaffected; TESTL — undefined; TESTB — set if parity of the result is even; 

cleared otherwise 
D: Unaffected 
H: Unaffected 



Destination 

Addressing 

Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycle 



IR: 



DA: 



TEST Rd 
TESTB Rbd 



TESTL RRd 



TEST @Rdi 
TESTB @Rdi 



TESTL @Rdl 



TEST address 
TESTB address 



TESTL address 



|l0|00110|w| Rd | 1 00 | 




|l | 1 1 1 00 | Rd | 1000| 




|oo|ooi 1 o|w| Rd * o| 1 00 | 




1 1 011100 | Rd * o| 100o| 




o 1 loo 1 1 olwl 0000 I 01 00 


address 



01011100 0000 1000 



7 
13 

8 
13 

11 



16 





10|00110|w| Rd | 1 | 




10| 01 1 100 | Rd | 1 | 




oojoo 1 io|w| Rd*0 [ 1 | 




00| 01 1 100 | Rd*0 | 1 000 | 




ss 


oi|ooi io|w 


oooo| 0100 


1 segment 


offset 








o 1 |o o 1 1 o|w 


oooo| 01 00 


SL 


1 I segment 


0000 0000 




address 






SS 


01 1 011100 


0000 | 1 000 


segment 


offset 








0l| 011100 


00O0 |l 000 


SL 


1 segment 


0000 0000 




offset 



13 
8 
13 

12 
14 

17 
19 



149 



TEST 

Test 



Destination 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


X: 


TEST addr(Rd) 
TESTB addr(Rd) 








12 
17 










o 1 |oo 1 1 o|w| Rd*0 | 01 00 




SS 


o 1 [oo 1 io|w 


Rd#0 | 1 00 


12 




address 


ol segment 


offset 






















SL 


o 1 |oo 1 io|w 


Rd*0 | 1 






1 I segment 


0000 0000 


15 




offset 






















01 | 01 1 1 00 | Rd*0 | 1000 




SS 


1 1 1110 


Rd*0 | 1 000 


17 




address 


segment 


offset 




















SL 


0l| 011100 


Rd*0 | 1000 






1 1 segment 


0000 0000 


20 




offset 



















Example: If register R5 contains %FFFF ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ), the statement 

TEST R5 
will set the S flag, clear the Z flag, and leave the other flags unaffected. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



150 



TRDB 

Translate and Decrement 



Operation: 



TRDB dst, src, r dst: IR 

src: IR 

dst +- src[dst] 

AUTODECREMENT dst by 1 
r •*- r - 1 

This instruction is used to translate a string of bytes from one code to another code. 
The contents of the location addressed by the destination register (the "target byte") 
are used as an index into a table of translation values whose lowest address is con- 
tained in the source register. The index is computed by adding the target byte to the 
address contained in the source register. The addition is performed following the 
rule for address arithmetic, with the target byte treated as an unsigned 8-bit value 
extended with high-order zeros. The sum is used as the address of an 8-bit transla- 
tion value within the table which replaces the original contents of the location 
addressed by the destination register. 

The destination register is then decremented by one, thus moving the pointer to the 
previous element in the string. The word register specified by "r" (used as a 
counter) is then decremented by one. The original contents of register RH1 are lost 
and are replaced by an undefined value. Rl in nonsegmented mode, or RRO in 
segmented mode, must not be used as a source or destination pointer, and Rl should 
not be used as a counter. The source, destination, and counter registers must be 
separate and non-overlapping registers. 

Because the 8-bit target byte is added to the source register to obtain the address of 
a translation value, the table may contain 256 bytes. A smaller table size may be 
used where it is known that not all possible 8-bit target byte values will occur. The 
source register is unchanged. 

C: Unaffected 

Z: Undefined 

S: Unaffected 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Flags: 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


TRDB@Rdi, @Rsi, r 








25 












1 1 1 1 1000 


Rd *0 


1000 






io| 111000 


Rd *0 


1000 




25 




0000 | r 


Rs*0 


0000 


0000 | r 


Rs * 


0000 



















Example: 



In nonsegmented mode, if register R6 contains %4001, the byte at location %4001 
contains 3, register R9 contains %1000, the byte at location /ol003 contains %AA, 
and register R12 contains 2, the instruction 

TRDB @R6, @R9, R12 

will leave the value °/oAA in location /o4001, the value %4000 in R6, and the value 
1 in R12. R9 will not be affected. The V flag will be cleared. RH1 will be set to an 
undefined value. In segmented mode, R6 and R9 would be replaced with 
register pairs. 

Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



151 



TRDRB 

Translate Decrement and Repeat 



TRDRB dst, src, R 



dst: IR 
src: IR 



Operation: dst •«- src [dst] 

AUTODECREMENT dst by 1 
r -*- r - 1 
repeat until r = 



Flags: 



This instruction is used to translate a string of bytes from one code to another code. 
The contents of the location addressed by the destination register (the "target byte") 
are used as an index into a table of translation values whose lowest address is con- 
tained in the source register. The index is computed by adding the target byte to the 
address contained in the source register. The addition is performed following the 
rules for address arithmetic, with the target byte treated as an unsigned 8-bit value 
extended with high -order' zeros. The sum is used as the address of an 8-bit transla- 
tion value within the table that replaces the original contents of the location 
addressed by the destination register. 

The destination register is then decremented by one, thus moving the pointer to the 
previous element in the string. The word register specified by V (used as a 
counter) is then decremented by one. The entire operation is repeated until the 
result of decrementing r is zero. This instruction can translate from 1 to 65536 bytes. 
The original contents of register RH1 are lost and are replaced by an undefined 
value. The source register is unchanged. The source, destination, and counter 
registers must be separate and non-overlapping registers. 

Because the 8-bit target byte is added to the source register to obtain the address of 
a translation value, the table may contain 256 bytes. A smaller table size may be 
used where it is known that not all possible 8-bit target byte values will occur. 

This instruction can be interrupted after each execution of the basic operation. The 
program counter of the start of this instruction is saved before the interrupt request 
is accepted, so the instruction can be properly resumed. Seven cycles should be 
added to this instruction's execution time for each interrupt request that is accepted. 

C: Unaffected 
Z: Undefined 
S: Unaffected 
V: Set 

D: Unaffected 
H: Unaffected 



Addressing 
Mode 




Nonsegmented Mode 


Segmented Mode 


Syntax 


Instruction Format 


Cycles 2 


Instruction Format 


Cycles 2 




TRDRB @Rbdi, @Rbsi, r 








11+14n 










IR: 




1 o| 1 1 1000 


Rd*0 


1 100 






io| 11 1000 


Rd* 


1100 




11+14n 




0000J r 


Rs*0 


0000 


0000| r 


Rs*0 


0000 



















152 



TRDRB 

Translate Decrement and Repeat 



Example: In nonsegmented mode, if register R6 contains /o4002, the bytes at locations %4000 

through %4002 contain the values %00, %40, %80, respectively, register R9 con- 
tains %1000, the translation table from location %1000 through %10FF contains 0, 

1, 2, ..., %7F, 0, 1, 2 %7F (the second zero is located at %1080), and register 

R12 contains 3, the instruction 

TRDRB @R6, @R9, R12 

will leave the values °/oOO, %40, %00 in byte locations %4000 through %4002, 
respectively. Register R6 will contain %3FFF, and R12 will contain 0. R9 will not be 
affected. The V flag will be set, and the contents of RH1 will be replaced by an 
undefined value. In segmented mode, R6 and R9 would be replaced by register 
pairs. 



%4000 


00000000 


%4001 


10 


%4002 


10 




AFTER 


%4000 


00000000 


%4001 


10 


%4002 


00000000 



%1000 


00000000 


%1001 


1 


%1002 


10 


• 


• 


%107F 


1111111 


%1080 


00000000 


%1081 


1 


%1082 


10 


• 


• 


%10FF 


1111111 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of data elements translated. 



153 



TRIB 

Translate and Increment 



TRIB dst, src, R 



dst: IR 
src: IR 



Operation: dst «*- src[dst] 

AUTOINCREMENT dst by 1 
r -*- r - 1 



Flags: 



This instruction is used to translate a string of bytes from one code to another code. 
The contents of the location addressed by the destination register (the "target byte") 
are used as an index into a table of translation values whose lowest address is con- 
tained in the source register. The index is computed by adding the target byte to the 
address contained in the source register. The addition is performed following the 
rules for address arithmetic, with the target byte treated as an unsigned 8-bit value 
extended with high-order zeros. The sum is used as the address of an 8-bit transla- 
tion value within the table which replaces the original contents of the location 
addressed by the destination register. The destination register is then incremented 
by one, thus moving the pointer to the next element in the string. The word register 
specified by V (used as a counter) is then decremented by one. The original con- 
tents of register RH1 are lost and are replaced by an. undefined value. The source 
register is unchanged. The source, destination, and counter registers must be 
separate and non- overlapping registers. 

Because the 8-bit target byte is added to the source register to obtain the address of 
a translation value, the table may contain 256 bytes. A smaller table size may be 
used where it is known that not all possible 8-bit target byte values will occur. 

C: Unaffected 

Z: Undefined 

S: Unaffected 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 



Assembler Language 
Syntax 



Nonsegmented Mode 



Instruction Format 



Cycles 



Segmented Mode 



Instruction Format 



Cycles 



TRIB@Rdi, @Rsi, r 



1 1 1 1 1000 


Rd* 


0000 


0000 | r 


Rs *0 


0000 



25 



1 1 1 1 1000 


Rd * 


0000 


0000 | r 


Rs*0 


0000 



25 



154 



TRIB 

Translate and Increment 



Example: This instruction can be used in a "loop" of instructions which translate a string of 

data from one code to any other desired code, but an intermediate operation on 
each data element is required. The following sequence translates a string of 1000 
bytes to the same string of bytes, with all ASCII "control characters" translated 
to the "blank" character (value = 32). A test, however, 
is made for the special character "return" (value = 13) which terminates 
the loop. The translation table contains 256 bytes. The first 33 (0-32) entries all con- 
tain the value 32, and all other entries contain their own index in the table, counting 
from zero. This example assumes nonsegmented mode. In segmented mode, R4 and 
R5 would be replaced by register pairs. 

LD R3, #1000 ! initialize counter! 

LDA R4, STRING !load start addresses! 

LDA R5, TABLE 



LOOP: 



DONE: 



CPB 
JR 

TRIB 
JR 



@R4, #13 
EQ, DONE 
@R4, @R5, R3 
NOV, LOOP 



! check for return character! 
!exit loop if found! 
{translate next byte! 
! repeat until counter = 0! 



TABLE +0 


10 


TABLE +1 


10 


TABLE +2 


10 


• 


• 


TABLE + 32 


10 


TABLE + 33 


10 1 


TABLE + 34 


10 10 


• 


• 


TABLE + 255 


11111111 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



155 



TRIRB 

Translate, Increment and Repeat 



TRIRB dst, src, R 



dst: IR 
src: IR 



Operation: 



Flags: 



dst -«- src[dst] 
AUTOINCREMENT dst by I 
r •*- r — 1 
repeat until r = 

This instruction is used to translate a string of bytes from one code to another code. 
The contents of the location addressed by the destination register (the "target byte") 
are used as an index into a table of translation values whose lowest address is con- 
tained in the source register. The index is computed by adding the target byte to the 
address contained in the source register. The addition is performed following the 
rules for address arithmetic, with the target byte treated as an unsigned 8-bit value 
extended with high-order zeros. The sum is used as the address of an 8-bit transla- 
tion value within the table which replaces the original contents of the location 
addressed by the destination register. The destination register is then incremented 
by one, thus moving the pointer to the next element in the string. The word register 
specified by "r" (used as a counter) is then decremented by one. The entire opera- 
tion is repeated until the result of decrementing r is zero. This instruction can 
translate from 1 to 65536 bytes. The original contents of register RH1 are lost and are 
replaced by an undefined value. The source register is unaffected. The source, 
destination, and counter registers must be separate and non-overlapping registers. 

Because the 8-bit target byte is added to the source register to obtain the address of 
a translation value, the table may contain 256 bytes. A smaller table size may be 
used where it is known that not all possible 8-bit target byte values will occur. 

This instruction can be interrupted after each execution of the basic operation. The 
program counter of the start of this instruction is saved before the interrupt request 
is accepted, so that the instruction can be properly resumed. Seven cycles should be 
added to this instruction's execution time for each interrupt request that is accepted. 

C: Unaffected 
Z: Undefined 
S: Unaffected 
V: Set 

D: Unaffected 
H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 2 


Instruction Format 


Cycles 2 




TRIRB @Rdl, @Rsi,.r 








11 + 14n 










IR: 




10| 1 1 1000 


Rd * 


0100 






1 [ 1 1 1000 


Rd *0 


0100 








| r 


Rs * 


0000 


oooo| r 


Rs *0 


0000 


11 +14n 



















156 



TRIRB 

Translate, Increment and Repeat 



Example: The following sequence of instructions can be used to translate a string of 80 bytes 

from one code to another. The pointers to the string and the translation table are set, 
the number of bytes to translate is set, and then the translation is accomplished. 
After executing the last instruction, the V flag is set and the contents of RH1 are lost. 
The example assumes nonsegmented mode. In segmented mode, R4 and R5 would 
be replaced by register pairs. 

LDA R4, STRING 

LDA R5, TABLE 

LD R3, #80 

TRIRB @R4, @R5, R3 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of data elements translated. 



157 



TRTDB 

Translate, Test and Decrement 



TRTDB srcl, src2, R 



src 1: IR 
src 2: IR 



Operation: RH1 ««- src2[srcl]- 

AUTODECREMENT srcl by 1 
r -*- r - 1 



Flags: 



This instruction is used to scan a string of bytes testing for bytes with special 
meaning. The contents of the location addressed by the first source register (the 
"target byte") are used as an index into a table of translation values whose lowest 
address is contained in the second source register. The index is computed by adding 
the target byte to the address contained in the second source register. The addition 
is performed following the rules for address arithmetic, with the target byte treated 
as an unsigned 8-bit value extended with high-order zeros. The sum is used as the 
address of an 8-bit value within the table which is loaded into register RH1. The Z 
flag is set if the value loaded into RH1 is zero; otherwise the Z flag is cleared. The 
contents of the locations addressed by the source registers are not affected. The first 
source register is then decremented by one, thus moving the pointer to the previous 
element in the string. The word register specified by V (used as a counter) is then 
decremented by one. The second source register is unaffected. The source, destina- 
tion, and counter registers must be separate and non-overlapping registers. 

Because the 8-bit target byte is added to the second source register to obtain the 
address of a translation value, the table may contain 256 bytes. A smaller table size 
may be used where it is known that not all possible 8-bit target byte values will 
occur. 

C: Unaffected 

Z: Set if the translation value loaded into RH1 is zero; cleared otherwise 

S: Unaffected 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


TRTDB @Rsli, @Rs2i, r 








25 












10| 1 1 1000 


Rs1 * 


1010 






1 | 1110 


Rs1 *0 


1010 




25 




0000 | r 


Rs2 * 


0000 


OOOOJ r 


Rs2*0 


0000 





















Example: 



In nonsegmented mode, if register R6 contains %4001, the byte at location %4001 
contains 3, register R9 contains %1000, the byte at location /ol003 Contains %AA, 
and register R12 contains 2, the instruction 

TRTDB @R6, @R9, R12 

Will leave the value %AA in RH1, the value /o4000 in R6, and the value 1 in R12. 
Location %4001 and register R9 will not be affected. The Z and V flags will be 
cleared. In segmented mode, register pairs must be used instead of R6 and R9. 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 



158 



TRTDRB 

Translate, Test, Decrement and Repeat 



TRTDRB src 1, src 2, R 



src 1: IR 
src 2: IR 



Operation: 



Flags: 



RH1 +- src 2[srcl] 
AUTODECREMENT srcl by 1 
r -*- r - 1 
repeat until RH1 = or r = 

This instruction is used to scan a string of bytes testing for bytes with special 
meaning. The contents of the location addressed by the first source register (the 
"target byte") are used as an index into a table of translation values whose lowest 
address is contained in the second source register. The index is computed by adding 
the target byte to the address contained in the second source register. The addition 
is performed following the rules for address arithmetic, with the target byte treated 
as an unsigned 8-bit value extended with high-order zeros. The sum is used as the 
address of an 8-bit value within the table which is loaded into register RH1. The Z 
flag is set if the value loaded into RH1 is zero; otherwise the Z flag is cleared. The 
contents of the locations addressed by the source registers are not affected. The first 
source register is then decremented by one, thus moving the pointer to the previous 
element in the string. The word register specified by V (used as a counter) is then 
decremented by one. The entire operation is repeated until either the Z flag is clear, 
indicating that a non-zero translation value was loaded into RH1, or until the result 
of decrementing r is zero. This instruction can translate and test from 1 to 
65536 bytes. The source, destination, and counter registers must be separate and 
non-overlapping registers. 

Target byte values which have corresponding zero translation-table entry values are 
to be scanned over, while target byte values which have corresponding non-zero 
translation-table entry values are to be detected. Because the 8-bit target byte is 
added to the second source register to obtain the address of a translation value, the 
table may contain 256 bytes. A smaller table size may be used where it is known that 
not all possible 8-bit target byte values will occur. 

This instruction can be interrupted after each execution of the basic operation. The 
program counter of the start of this instruction is saved before the interrupt request 
is accepted, so that the instruction can be properly resumed. Seven cycles should be 
added to this instruction's execution time for each interrupt request that is accepted. 

C: Unaffected 

Z: Set if the translation value loaded into RH1 is zero; cleared otherwise 

S: Unaffected 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 2 


Instruction Format 


Cycles 2 




TRTDRB@Rsl 1 @Rs2 1 ,r 








11+14n 










IR: 




1 o| 1 1 1000 


Rs1 *0 


1110 






10| 11100 


Rs1 * 


1110 




11 +14n 




0000| r 


Rs2* 


1110 


0000 | r 


Rs2*0 


1110 





















159 



TRTDRB 

Translate, Test, Decrement and Repeat 



Example: In nonsegmented mode, if register R6 contains %4002, the bytes at locations %4000 

through %4002 contain the values %00, %40, %.80, repectively, register R9 contains 
%1000, the translation table from location %1000 through %10FF contains 0, 1, 

2, ..., %7F, 0, 1, 2 %7F (the second zero is located at %1080), and register 

R12 contains 3, the instruction 



TRTDRB @R6, @R9, R12 

will leave the value %40 in RH1 (which was loaded from location %1040). Register 
R6 will contain %4000, and R12 will contain 1. R9 will not be affected. The Z and V 
flags will be cleared. In segmented mode, register pairs are used instead of R6 
and R9. 



4000 


00000000 


4001 


10 


4002 


10 



1000 


00000000 


1001 


1 


1002 


10 


• 


• 


107F 


1111111 


1080 


00000000 


1081 


1 


1082 


10 


• 


• 


10FF 


1111111 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: n = number of data elements translated. 



160 



TRTIB 

Translate, Test and Increment 



TRTIB src 1, src2, R 



src 1: IR 
src 2: IR 



Operation: RH1 -«- src2[srcl] 

AUTOINCREMENT srcl by 1 
r -*- r - 1 



Flags: 



This instruction is used to scan a string of bytes testing for bytes with special 
meaning. The contents of the location addressed by the first source register (the 
"target byte") are used as an index into a table of translation values whose lowest 
address is contained in the second source register. The index is computed by adding 
the target byte to the address contained in the second source register. The addition 
is performed following the rules for address arithmetic, with the target byte treated 
as an unsigned 8-bit value extended with high-order zeros. The sum is used as the 
address of an 8-bit value within the table which is loaded into register RH1. The Z 
flag is set if the value loaded into RH1 is zero; otherwise the Z flag is cleared. The 
contents of the locations addressed by the source registers are not affected. The first 
source register is then incremented by one, thus moving the pointer to the next ele- 
ment in the string. The word register specified by "r" (used as a counter) is then 
decremented by one. The second source register is unaffected. The source, destina- 
tion, and counter registers must be separate and non-overlapping registers. 

Because the 8-bit target byte is added to the second source register to obtain the 
address of a translation value, the table may contain 256 bytes. A smaller table size 
may be used where it is known that not all possible 8-bit target byte values 
will occur. 

C: Unaffected 

Z: Set if the translation value loaded into RH1 is zero; cleared otherwise 

S: Unaffected 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


IR: 


TRTIB ©Rsli, @Rs2i, r 








25 












1 [ 111 000 


RS1 *0 


0010 






1 | 1 1 1000 


Rs1 *0 


0010 




25 




0000 | r 


Rs2 * 


0000 


0000| r 


Rs2 * 


0000 



















161 



TRTIB 

Translate, Test and Increment 



Example: 



This instruction can be used in a "loop" of instructions which translate and test a 
string of data, but an intermediate operation on each data element is required. The 
following sequence outputs a string of 72 bytes, with each byte, of the original string 
translated from its 7-bit ASCII code to an 8-bit value with odd parity. Lower case 
characters are translated to upper case, and any embedded control characters are 
skipped over. The translation table contains 128 bytes, which assumes that the most 
significant bit of each byte in the string to be translated is always zero. The first 32 
entries and the 128th entry are zero, so that ASCII control characters and the 
"delete" character (%7F) are suppressed. The given instruction sequence is for 
nonsegmented mode. In segmented mode, register pairs would be used instead of R3 
and R4. 



LOOP: 



LD 

LDA 

LDA 


R5, #72 
R3, STRING 
R4, TABLE 


! initialize counter! 
Iload start address! 


TRTIB 
JR 

OUTB 
JR 


@R3, @R4, R5 
Z, LOOP 
PORTn, RHl 
NOV, LOOP 


! translate and test next byte! 
!skip control character! 
(output characters! 
! repeat until counter = 0! 



DONE: 



Note 1 : Word register in nonsegmented mode, register pair in segmented mode. 



162 



TRTIRB 

Test, Increment and Repeat 



TRTIRB src 1, src 2, R 



src 1: 
src 2: 



IR 
IR 



Operation: RH1 ««- src2[srcl] 

AUTOINCREMENT srcl by 1 

r «*- r - 1 

repeat until RH1 = or R = 



Flags: 



This instruction is used to scan a string of bytes, testing for bytes with special 
meaning. The contents of the location addressed by the first source register (the 
"target byte") are used as an index into a table of translation values whose lowest 
address is contained in the second source register. The index is computed by adding 
the target byte to the address contained in the second source register. The addition 
is performed following the rules for address arithmetic, with the target byte treated 
as an unsigned 8-bit value extended with high-order zeros. The sum is used as the 
address of an 8-bit value within the table which is loaded into register RH1. The Z 
flag is set if the value loaded into RH1 is zero; otherwise the Z flag is cleared. The 
contents of the locations addressed by the source registers are not affected. 

The first source register is then incremented by one, thus moving the pointer to the 
next element in the string. The word register specified by "r" (used as a counter) is 
then decremented by one. The entire operation is repeated until either the Z flag is 
clear, indicating that a non-zero translation value was loaded into RH1, or until the 
result of decrementing r is zero. This instruction can translate and test from 1 to 
65536 bytes. The source, destination, and counter registers must be separate and 
non-overlapping registers. 

Target byte values which have corresponding zero translation table entry values are 
scanned over, while target byte values which have corresponding non-zero transla- 
tion table entry values are detected and terminate the scan. Because the 8-bit target 
byte is added to the second source register to obtain the address of a translation 
value, the table may contain 256 bytes. A smaller table size may be used where it is 
known that not all possible 8-bit target byte values will occur. 

This instruction can be interrupted after each execution of the basic operation. The 
program counter of the start of this instruction is saved before the interrupt request 
is accepted, so that the instruction can be properly resumed. Seven cycles should be 
added to this instruction's execution time for each interrupt request that is accepted. 

C: Unaffected 

Z: Set if the translation value loaded into RH1 is zero; cleared otherwise 

S: Unaffected 

V: Set if the result of decrementing r is zero; cleared otherwise 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles* 


Instruction Format 


Cycles* 


IR: 


TRTIRB @Rsll, @Rs2l, r 








11+14n 










1 | 111000 


Rs1 * 


0110 






io| 111000 


Rs1 *0 


01 10 


11 + 14n 




0000| r 


R*2*0 


1110 


O000J r 


Rs2*0 


1110 



















163 



TRTIRB 

Test, Increment and Repeat 



Example: The following sequence of instructions can be used in nonsegmented mode to scan a 

string of 80 bytes, testing for special characters as defined by corresponding non- 
zero translation table entry values. The pointers to the string and translation table 
are set, the number of bytes to scan is set, and then the translation and testing is 
done. The Z and V flags can be tested after the operation to determine if a special 
character was found and whether the end of the string has been reached. The 
translation value loaded into RH1 might then be used to index another table, or to 
select one of a set of sequences of instructions to execute next. In segmented mode, 
R4 and R5 must be replaced with register pairs. 





LDA 


R4, STRING 




LDA 


R5, TABLE 




LD 


R6, #8Q 




TRTIRB 


@R4, @R5, R6 




JR 


NZ, SPECIAL 


END_OF_ 


.STRING: 




SPECIAL: 







IR OV,LAST_CHAR_SPECIAL 



LAST_CHAR_SPECIAL: 



Note 1: Word register in nonsegmented mode, register pair in segmented mode. 
Note 2: h = number of data elements translated. 



164 



TSET 

Test and Set 



TSET dst 
TSETB 



dst: R, IR, DA, X 



Operation: 



S -*- dst(msb) 
dst(0:msb) -*- 111. ..Ill 



Flags: 



Tests the most significant bit of the destination operand, copying its value into the S 
flag, then sets the entire destination to all 1 bits. This instruction provides a locking 
mechanism which can be used to synchronize software processes which reguire 
exclusive access to certain data or instructions at one time. 



During the execution of this instruction, BUSRQ is not honored in the time between 
loading the destination from memory and storing the destination to memory. For 
systems with one processor, this ensures that the testing and setting of the destination 
will be completed without any intervening accesses. This instruction should not be 
used to synchronize software processes residing on separate processors where the 
destination is a shared memory location, unless this locking mechanism can be 
guaranteed to function correctly with multi-processor accesses. 

C: Unaffected 

Z: Unaffected 

S: Set if the most significant bit of the destination was 1 ; cleared otherwise 

V: Unaffected 

D: Unaffected 

H: Unaffected 



Addressing 
Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


TSET Rd 
TSETB Rbd 

TSET @Rdi 
TSETB @Rdi 

TSET address 
TSETB address 

TSET addr(Rd) 
TSETB addr(Rd) 








7 
11 

14 
15 








1(>|00110|w| Rd | 1 1 


1 1 1 1 1 W | Rd | 1 1 | 


7 


IR: 








OOJOO 1 1 o|w| Rd*0 | 01 10 


00|p01 1 o|w| Rd*0 | 01 1 | 


11 










DA: 




oi|ooi io|w| oooo|oi 10 






o 1 |oo 1 io|w 


0000 | 1 1 


15 




address 




1 segment 


offset 






















SL 


o 1 |oo 1 io|w 


0000 | 01 10 






1 | segment 


0000 0000 


17 




offset 




X: 
















1 100 1 10|w| Rd*0 | 1 1 




ss 


01 |ooi io|w 


Rd*0 


01 10 


15 




address 




1 segment 


offset 




















SL 


01|001 io|w 


Rd*0 | 01 10 






1 segment 


0000 0000 


18 




offset 



















165 



TSET 

Test and Set 



Example: A simple mutually-exclusive critical region may be implemented by the following 

sequence of statements: 

ENTER - 

TSET ' SEMAPHORE 

JR MI, ENTER Hoop until resource con-! 

! trolled by SEMAPHORE! 

lis available! 

'.Critical Region — only one software process! 
! executes this code at a time! 



CLR SEMAPHORE ! release resource controlled! 

!by SEMAPHORE! 



166 



XOR 

Exclusive Or 



XOR dst, src 
XORB 



dst: R 

src: R/IM, IR, DA, X 



Operation: 



dst -+- dst XOR src 



Flags: 



The source operand is logically EXCLUSIVE ORed with the destination operand and 
the result is stored in the destination. The contents of. the source are not affected. 
The EXCLUSIVE OR operation results in a one bit being stored whenever the cor- 
responding bits in the two operands are different; otherwise, a zero bit is stored. 

C: Unaffected 

Z: Set if the result is ze'ro; cleared otherwise 

S: Set if the most significant bit of the result is set; cleared otherwise 

P: XOR — unaffected; XORB — set if parity of the result is even; cleared otherwise 

D: Unaffected 

H: Unaffected 



Source 

Addressing 

Mode 


Assembler Language 
Syntax 


Nonsegmented Mode 


Segmented Mode 


Instruction Format 


Cycles 


Instruction Format 


Cycles 


R: 


XOR Rd, Rs 
XORB Rbd, Rbs 

XOR Rd, #data 
XORB Rbd, #data 

XOR Rd, @Rsi 
XORB Rbd, @Rsi 

XOR Rd, address 
XORB Rbd, address 

XOR Rd, addr(Rs) 
XORB Rbd, addr(Rs) 








4 
7 
7 

7 
9 

10 








1<>|00100|w| Rs | Rd 


1 |00 1 00| w| Rs | Rd | 


4 










IM: 




00| 001 001 | 0000 | Rd 






oo|ooiooi|oooo| Rd 


7 




data 


data 




















00| 001000 


| Rd 






00 | 001000 


| /Rd 


7 




data 


data 


data 


data 


IR: 














00|00100|w| Rs*0 | Rd 


00|00100|w| Rs*0 | Rd | 


7 


DA: 










01 |001 00|w| OOOOJ Rd 




SS 


oi|ooioo|w 


| Rd 


10 




address 


1 segment 


offset 




















SL 


oi|ooioo|w 


| Rd 






1| segment 


0000 0000 


12 




offset 




X: 
















0l|00100|w| Rs*0 | Rd 




SS 


oi|ooioo|w 


Rs*0 | Rd 


10 




address 


segment 


offset 




















SL 


oi|ooioo|w 


Rs*0 | Rd 






1 segment 


0000 0000 


13 




offset 





















167 



XOR 

Exclusive Or 



Example: If register RL3 contains %C3 (11000011) and the source operand is the immediate 

value %7B (01111011), the statement 

XORB RL3,#%7B 

will leave the value %B8 (10111000) in RL3. 

Note 1 : Word register in nonsegmented mode, register pair in segmented mode. 



168 



EPA Instruction Templates 

There are seven '"templates" for EPA instruc- 
tions. These templates correspond to EPA 
instructions, which combine EPU operations 
with possible transfers between memory and an 
EPU, between CPU registers and EPU regis- 
ters, and between the Flag byte of the CPU's 
FCW and the EPU. Each of these templates is 
described on the following pages. The descrip- 
tion assumes that the EPA control bit in the 
CPU's FCW has been set to 1. In addition, the 
description is from the point of view of 
the CPU— that is, only CPU activities are 
described; the operation of the EPU is implied, 



but the full specification of the instruction 
depends upon the implementation of the EPU 
and is beyond the scope of this manual. 

Fields ignored by the CPU are shaded in the 
diagrams of the templates. The 2-bit field in bit 
positions and 1 of the first word of each 
template would normally be used as an identi- 
fication field for selecting one of up to four 
EPUs in a multiple EPU system configuration. 
Other shaded fields would typically contain 
opcodes for instructing an EPU as to the oper- 
ation it is to perform in addition to the data 
transfer specified by the template. 



Extended Instruction 

Load Memory from EPU 



Operation: 



Memory-*- EPU 



The CPU performs the indicated address calculation and generates n EPU memory 
write transactions. The n words are supplied by an EPU and are stored in n con- 
secutive memory locations starting with the effective address. 

Flags/Registers: No flags or CPU registers are affected by this instruction. 



modelo 111 iTdst 


1 1 1" :: 




n-1 



mode 



dst 



NS 



Clock Cycles 
SS 



SL 



IR (dst gt 0) ll+3n 

1 X (dst * 0) 15 + 3n 15 + 3n 18 + 3n 

1 DA (dst = 0) 14 + 3n 15 + 3n 17 + 3n 



169 



Extended Instruction 

Load EPU from Memory 



Operation: 



EPU +- Memory 



The CPU performs the indicated address calculation and generates n EPU memory 
read transactions. The n consecutive words are fetched from the memory locations 
starting with the effective address. The data is read by an EPU and operated upon 
according to the EPA instruction encoded into the shaded fields. 

Flags/Registers: No flags or CPU registers are affected by this instruction. 



mode 11 11 src 



•^^^v&:£ ■:■;:. 



mode 



NS 



Clock Cycles 
SS 



Extended Instruction 

Load CPU from EPU 



SL 



IR (src 9fc 0) ll+3n 

1 X (src * 0) 15 + 3n 15 + 3n 18 + 3n 

1 DA (src = 0) 14 + 3n 15 + 3n 17 + 3n 



Operation: 



CPU -*- EPU registers 



The contents of n words are transferred from an EPU to consecutive CPU registers 
starting with register dst. CPU registers are transferred consecutively, with register 
following register 15. 

Flags/Registers: No flags are affected by this instruction. 

Execution Time: 11 + 3n cycles. 



10 0011 11 



HH[ 



3HFH 



„■■.„„,.„,.,„ 



170 



Extended Instruction 

Load EPU from CPU 



Operation: EPU ■*- CPU registers 

The contents of n words are transferred to an EPU from consecutive CPU registers 
starting with register src. CPU registers are transferred consecutively, with register 
following register 15. 

Flags/Registers: No flags are affected by this instruction. 

Execution Time: 11 + 3n cycles. 



10 0011 11 



v- ; *-'.-4 



iUd 



Extended Instruction 

Load FCW from EPU 

Operation: Flags ■*- EPU 

The Flags in the CPU's Flag and Control Word are loaded with information from an 
EPU on AD lines AD -AD 7 . 

Flags/Registers: The contents of CPU register are undefined after the execution of this instruction. 

Execution Time: 14 cycles. 



10 0011 10 




— _ 

o o [{i|;v 


.^f;] 0000 


'&^m 


0000 



171 



Extended Instruction 

Load EPU from FCW 

Operation: EPU •*- Flags 

The Flags in the CPU's Flag and Control Word are transferred to an EPU on AD 
lines AD0-AD7. 

Flags/Registers: The flags in the FCW are unaffected by this instruction. 

Execution Time: 14 cycles. 



100011 10 




,.l 


joo 00 




0000 



Extended Instruction 

Internal EPU Operation 

Operation: Internal EPU Operation 

The CPU treats this template as a No Op. It is typically used to initiate an internal 
EPU operation. 

Flags/Registers: The flags in the FCW are unaffected by this instruction. 

Execution Time: 14 cycles. 

10001110 01 



172 



Programmers Quick Reference 



Clock Cycles* 



Mnemonics Operands 



Addr. Word, Byte 

Modes NS SS SL 



Long Word 
NS SS SL 



Operation 



ADC 
ADCB 



R,src 



Add with Carry 

R — R + src + carry 



ADD 

ADDB 

ADDL 



R.src 



R 


4 


4 


4 


8 


8 


8 


Add 


IM 


7 


7 


7 


14 


14 


14 


R - R + src 


IR 


7 






14 








DA 


9 


10 


12 


15 


16 


18 




X 


10 


10 


13 


16 


16 


19 




R 


4 


4 


4 








AND 


IM 


7 


7 


7 








R - R AND src 


IR 

DA 


7 
9 


10 


12 










X 


10 


10 


13 











AND 
ANDB 



BIT 


dst.b 


R 


4 


4 


4 


Test Bit Static 


BITB 




IR 


8 






Z flag — NOT dst bit specified by b 






DA 


10 


11 


13 








X 


11 


11 


14 




BIT 


dst.R 


R 


10 


10 


10 


Test Bit Dynamic 


BITB 












Z flag — NOT dst bit specified by 
contents of R 


CALL 


dst 


IR 


10 


10 


15 


Call Subroutine 






DA 


12 


18 


20 


Autodecrement SP 






X 


13 


18 


21 


@ SP - PC 
PC - dst 



CP 

CPB 

CPL 



R,src 



Call Relative 

Autodecrement SP 

@ SP - PC 

PC - PC + dst( range -4094 to 

+ 4096) 



CLR 


dst 


R 


7 


7 


7 


Clear 


CLRB 




IR 


8 






dst - 






DA 


11 


12 


14 








X 


12 


12 


15 




COM 


dst 


R 


7 


7 


7 


Complement 


COMB 




IR 


12 






dst - NOT dst 






DA 


15 


16 


18 








X 


16 


16 


19 




COMFLG 


flags 




7 


7 


7 


Complement Flag 

(Any combination of C, Z, S, P/V) 



R 


4 


4 


4 


8 


8 


8 


Compare with Register 


IM 


7 


7 


7 


14 


14 


14 


R - src 


IR 


7 






14 








DA 


9 


10 


12 


15 


16 


18 




X 


10 


10 


13 


16 


16 


19 





CP dst.IM 

CPB 



IR 11 

DA 14 

X 15 



15 
15 



17 
18 



Compare with Immediate 

dst - IM 



* NS = Non-Segmented, SS = Short Segmented Offset, SL = Segmented Long Offset, Blank = Not Implemented. 



173 



Clock Cycles 



Mnemonics Operands 



Addr. 
Modes 



Word, Byte 
NS SS SL 



Long Word 
NS SS SL 



Operation 



CPD 
CPDB 



Rx,src,RY,cc Ifl 



Compare and Decrement 

Rx - src 

Autodecrement src address 

Ry — Ry — 1 



CPDR 
CPDRB 



Rx,src,Ry,cc IR 



(11 + 9n) 



Compare, Decrement and Repeat 

Ry - src 

Autodecrement src address 

R X - Ry - 1 

Repeat until cc is true or Ry = 



CPI 
CPIB 



Rx,src,Ry,cc IR 



Compare and Increment 

Rx - src 

Autoincrement src address 

Ry - Ry - 1 



CPIR 
CPIRB 



Rx,src,Ry,cc IR 



(11 + 9n) 



Compare, Increment and Repeat 

Rx - src 

Autoincrement src address 

Ry — Ry — 1 

Repeat until cc is true or Ry = 



CPSD 
CPSDB 



dst,src,R,cc IR 



Compare String and Decrement 

dst - src 

Autodecrement dst and src addresses 

R - R- 1 



CPSDR 
CPSDRB 



dst,src,R,cc IR 



(11 + 14n) 



Compare String, Deer, and Repeat 

dst - src 

Autodecrement dst and src addresses 

R - R - 1 

Repeat until cc is true or R = 



CPSI 
CPSIB 



dst,src,R,cc 



Compare String and Increment 

dst - src 

Autoincrement dst and src addresses 

R - R - 1 



CPSIR 
CPSIRB 



dst,src,R,cc IR 



(11 + 14n) 



Compare String, Incr. and Repeat 

dst - src 

Autoincrement dst and src addresses 

R - R - 1 

Repeat until cc is true or R = 



Decimal Adjust 



DEC 
DECB 



dst,n 



R 4 4 4 

IR 11 

DA 13 14 16 

X 14 14 17 



Decrement by n 

dst — dst - n 
(n = 1...16) 



DI* 



Disable Interrupt 

(Any combination of NVI, VI) 



DIV 
DIVL 



R 


107 






744 






1M 


107 






744 






IR 


107 


107 


107 


744 


744 


744 


DA 


108 


109 


111 


745 


746 


748 


X 


109 


109 


112 


746 


746 


749 



Divide (signed) 

Word: R n + i - R n , n + i + src 

R n — remainder 
Long Word: R n + 2 , n + 3- R n ... n + 3 + src 
^n,n + 1 *~ remainder 



^Privileged instruction. Executed in system mode only. 



174 



EX 
EXB 



INC 
INCB 



Clock Cycles 



Mnemonics Operands 



Addr. 
Modes 



Word. Byte 
NS SS SL 



Long Word 
NS SS SL 



Operation 



DJNZ 
DBJNZ 


R.dst 


RA 


11 


11 


11 


Decrement and Jump if Non-Zero 

R - R - 1 

If R * .0: PC - PC + dst(range -254 to 0) 


EI* 


int 




7 


7 


7 


Enable Interrupt 

(Any combination of NVI, VI) 



R,src 



dst,n 



R 6 6 6 

IR 12 

DA 15 16 18 

X 16 16 19 



Exchange 

R — src 



EXTS 

EXTSB 

EXTSL 


dst 


R 


11 


11 


11 


11 


11 


11 


Extend Sign 

Extend sign of low order half of dst 
through high order half of dst 


HALT* 






(8 


+ 3n 










HALT 


IN* 
INB* 


R,src 


IR 
DA 


10 
12 


12 


12 








Input 

R — src 



R 


4 


4 


4 


IR 


11 






DA 


13 


14 


16 


X 


14 


14 


17 



Increment by n 

dst — dst + n 
. (n = 1...16) 



IND* 
INDB* 



dst, src, R 



Input and Decrement 

dst — src 

Autodecrement dst addresed 

R - R - 1 



INDR* 
INDRB* 



dst,src,R 



IR 



(11 +.10n) 



Input, Decrement and Repeat 

dst — src 

Autodecrement dst address 
R - R - .1 
Repeat until R = 



INI* 
INIB* 



dst,src,R 



IR 21 



Input and Increment 

dst — src 

Autoincrement dst address 

R - R - 1 



INIR* 
IN1RB* 



dst, src. R 



IR 



(11 + lOn) 



Input, Increment and Repeat 

dst — src 

Autoincrement dst address 
R - R - 1 
Repeat until R = 



IRET* 



13 13 16 



Interrupt Return 

PS - @ SP 

Autoincrement SP 



IR 


10 




15 


(taken) 


lump Conditional 


IR 


7 




7 


(not taken) 


If cc is true: PC - dst 


DA 


7 


8 


10 






X 


8 


8 


11 







IR 



cc,dst 



RA 



Jump Conditional Relative 

If cc is true: PC - PC + dst 
(range -256 to + 254) 



^Privileged instruction. Executed in system mode only. 



175 



Mnemonics Operands 



Addr. 
Modes 



Clock Cycle! 



Word, Byte 
NS SS SL 



Long Word 
NS SS SL 



Operation 



LD 

LDB 

LDL 



R,src 



R 
IM 
IM 

IR 
DA 

X 

BA 
BX 



3 

7 

5 

7 

9 

10 

14 

14 



3 3 

7 7 

(byte only) 



5 
11 



5 
11 



5 

11 



Load into Register 

R — src 



10 

10 



12 
13 
14 
14 



11 

12 13 15 

13 • 13 16 
17 17 
17 17 



LD 

LDB 

LDL 



dst,R 



IR 
DA 

X 

BA 
BX 



11 12 14 

12 12 15 
14 14 14 
14 14 14 



11 
14 
15 
17 
17 



15 
15 
17 
17 



17 
18 
17 
17 



Load into Memory (Store) 
dst - R 



LD 
LDB 



dst,IM 



IR 
DA 
X 



11 

14 15 

15 15 



17 
18 



Load Immediate into Memory 

dst - IM 



LDA 



LDD 
LDDB 



R,src 



DA 


12 


13 


15 


X 


13 


13 


16 


BA 


15 


15 


15 


BX 


15 


15 


15 



dst, src, R 



20 



Load Address 

R — source address 



LDAR 


R,src 


RA 


15 


15 


15 


Load Address Relative 


LDCTL* 


CTLR,src 


R 


7 


7 


7 


Load into Control Register 

CTLR - src 


LDCTL* 


dst,CLTR 


R 


7 


7 


7 


Load from Control Register 

dst - CTLR 


LDCTLB 


FLGR,src 


R 


7 


7 


7 


Load into Flag Byte Register 

FLGR - src 


LDCTLB 


dst,FLGR 


R 


7 


7 


7 


Load from Flag Byte Register 

dst - FLGR 



Load and Decrement 

dst — src 

Autodecrement dst and src addresses 

R - R + 1 



LDDR 
LDDRB 



dst,src,R 



(11 ■+ 9 n) 



Load, Decrement and Repeat 

dst — src 

Autodecrement dst and src addresses 

R - R - 1 

Repeat until R = 



LDI 
LDIB 



dst, src, R 



Load and Increment 

dst — src 

Autoincrement dst and src addresses 

R - R - 1 



LDIR 
LDIRB 



dst, src, R 



(11 + 9 n) 



Load, Increment and Repeat 

dst — src 

Autoincrement dst and src addresses 

R - R - 1 

Repeat until R = 



176 



MULT 
MULTL 



Clock Cycle; 



Mnemonics Operands 



R.src 



Addr. 
Modes 



Word. Byte 
NS SS SL 



Long Word 
NS SS SL 



Operation 



LDK 


R,src 


IM 


5 


5 


5 








Load Constant 

R - n(n = 0...15) 


LDM 


R,src,n 


IR 
DA 
X 


11 
14 
15 


15 
15 


17 
18 


+ 3n 






Load Multiple 

dst — src (n consecutive words) 
(n = 1 ... 16) 


LDM 


dst.R.n 


IR 
DA 
X 


11 
14 
15 


15 
15 


17 

18 


+ 3n 






Load Multiple (Store Multiple) 
dst — R (n consecutive words) 
(n = 1...16) 


LDPS* 


src 


IR 
DA 
X 


12 
16 

17 


20 
20 


22 
23 








Load Program Status 

PS -'src 


LDR 
LDRB 


R,src 


RA 


14 


14 


14 


17 


17 


17 


Load Relative 

R — src 

(range -32768... +32767) 


LDR 

LDRB 

LDRL 


dst.rT 


RA 


14 


14 


14 


17 


17 


17 


Load Relative (Store Relative) 

dst - R 

(range -32768... + 32767) 


MBIT* 






7 


7 


7 








Test Multi-Micro Bit 

Set if Mj is Low; reset S if Mj is High. 


MREQ* 


dst 


R 


(12 


+ 7n) 


i 








Multi-Mircre Request 


MRES* 






5 


5 


5 








Multi-Micro Reset 


MSET* 






5 


5 


5 








Multi-Micro Set 



R 
IM 

IR 
DA 

X 



70 
70 



70 70 

70 70 
70 

71 72 74 

72 72 75 



282 4 
282-f 



282+ 282- 
282+ 282- 
282 + 

283+ 283+ 286 + 
284+ 284+ 287 + 



Multiply (signed) 

Word: R n , n +1- R n+1' src 

Long Word: R n n + 3 -R n + 2 , n + 3 ' src 
+ Plus seven cycles for each 1 in the 
absolute value of the low order 16 bits of the 
multiplicand. 



NEG 
NEGB 



R 
IR 
DA 
X 



7 7 
12 

15 16 

16 16 



Negate 

dst - - dst 



18 
19 



NOP 



No Operation 



OR 
ORB 



R 
IM 

IR 
DA 

X 



4 
7 
7 
9 
10 



10 
10 



12 
13 



OR 

R - R OR src 



OTDR* dst, src, r 

OTDRB* 



(11 + 10 n) 



Output, Decrement and Repeat 

dst — src 

Autodecrement src address 
R - R - 1 
Repeat until R = 



•Privileged instructions. Executed in system mode only. 



177 



Mnemonics Operands 



Addr. 
Modes 



Clock Cycles 



Word, Byte 
NS SS SL 



Long Word 
NS SS SL 



Operation 



OTIR* 
OTIRB* 



dst, src, R 



(11 + 10 n) 



Output. Increment and Repeat 

dst — src 

Autoincrement scr address 
R - R - 1 
Repeat until R = 



OUT* 
OUTB* 



dst,R 



IR 
DA 



10 
12 



12 12 



Output 

dst - R 



OUTD* 
OUTDB* 



dst, src, R 



Output and Decrement 

dst — src 

Autodecrement src address 

R - R - 1 



OUTI* 
OUTIB* 



dst, src, R 



Output and Increment 

dst — src 

Autoincrement src address 

R - R - 1 



POP 
POPL 



dsUR 



R 
IR 
DA 
X 



12 
16 
16 



16 
16 



8 12 12 12 Pop 

19 dst - IR 

18 23 23 25 Autoincrement contents of R 

19 23 23 26 



PUSH 
PUSHL 



R 9 

IM 12 

IR 13 

DA 14 

X 14 



9 

12 



14' 
14 



9 
12 



16 

17 



20 
16 
21 



12 



21 
21 



Push 

Autodecrement' contents of R 
IR - src 



23 
24 



RES 
RESB 



dst,b 



R 
IR 
DA 
X 



4 4 
11 

13 14 

14 14 



16 
17 



Reset Bit Static 

Reset dst bit specified by b 



RES 
RESB 


dst,R 


R 


10 10 


10 




Reset Bit Dynamic 

Re,set dst bit specified by contents R 


RESFLG 


flag 




7 7 


7 




Reset Flag 

(Any combination of C, Z, S, P/V) 


RET 


cc 




10 10 
7 7 


13 
7 


(taken) 
(not taken) 


Return Conditional 

If cc is true: PC — @ SP Autoincrement SP 


RL 
RLB 


dst,n 


R 
R 


6 for n = 

7 for n = 


1 
2 




Rotate Left 

by n bits (n = 1,2) 


RLC 
RLCB 


dst,n 


R 
R 


6 for n = 

7 for n = 


1 
2 




Rotate Left through Carry 

by n bits (n = 1, 2) 


RLDB 


R,src 


R 


9 9 


9 




Rotate Digit Left 


RR 
RRb 


dst,n 


R 
R 


6 for n = 

7 for n = 


1 
2 




Rotate Right 

by n bits (n = 1, 2) 


RRC 
RRCB 


dst,n 


R 
R 


6 for n = 

7 for n = 


1 
2 




Rotate Right through Carry 

by nbits (n = 1, 2) 



"Privileged instruction. Executed in system mode only, 



178 



sc 



Clock Cycles 



Mnemonics Operands 



Addr. 
Modes 



Word, Byte 
NS SS SL 



Long Word 
NS SS SL 



Operation 



RRDB 


R,src 


R 


9 


9 


9 


Rotate Digit Right 


SBC 
SBCB 


R,src 


R 


5 


5 


5 


Subtract with Carry 

R — R - src - carry 



IM 



33 



39 



System Call 

Autodecrement SP 
@ SP - old PS 
Push instruction 
PS - System Call PS 



SDA 

SDAB 

SDAL 



dst.R 



(15 + 3n) 



(15 + 3n) Shift Dynamic Arithmetic 

Shift dst left or right 
by contents of R 



SDL 

SDLB 

SDLL 



dst.R 



(15 + 3n) (15 + 3n) Shift Dynamic Logical 

Shift dst left or right 
by contents of R 



SET 
SETB 



SIND* 
SINDB* 



dst.b 



dst,src,R 



R 4 4 4 

IR 11 

DA 13 14 16 

•X 14 14 17 



Set Bit Static 

Set dst bit specified by b 



SET 
SETB 


dst.R 


R 


10 


10 


10 


Set Bit Dynamic 

Set dst bit specified by contents of R 


SETFLG 


flag 


X 


7 


7 


7 


Set Flag 

(Any combination of C, Z, S, P'V) 


SIN* 
SINB* 


R,src 


DA 


12 


12 


12 


Special Input 

R — src 



Special Input and Decrement 

dst — src 

Autodecrement dst address- 

R - R - 1 



SINDR* 
SINDRB* 



dst, src, R 



(11 + lOn) 



Special Input, Decrement and Repeat 

dst — src 

Autodecrement dst address 
R - R - 1 
Repeat until R = 



SINI* 
SINIB* 



Special Input and Increment 

dst — src 

Autoincrement dst address 

R - R - 1 



SINIR* 
SINIRB* 



dst,src,R 



(11 + lOn) 



Special Input, Increment and Repeat 

dst — src 

Autoincrement dst address 

R - R - 1 













Repeat until R = 


SLA 

SLAB 

SLAL 


dst,n 


R 


(13 + 3n) 


(13 + 3n) 


Shift Left Arithmetic 

by n bits 


SLL 

SLLB 

SLLL 


dst.n 


R 


(13 + 3n) 


(13 + 3n) 


Shift Left Logical 

by n bits 



"Privileged instruction. Executed in system mode only. 



179 



Clock Cycles 



Mnemonics Operands 



Addr. 
Modes 



Word. Byte 
NS SS SL 



Long Word 
NS SS SL 



Operation 



SOTDR* dst,src,R IR (11 + 10 n) 

SOTDRB* 



Special Output, Deer, and Repeat 

dst — sre 

Autodecrement sre address 
R - R - 1 
Repeat until R = 



SOTIR* 
SOTIRB* 



dst,src,R 



(11 + 10 n) 



Special Output, Incr. and Repeat 

dst — sre 

Autoincrement sre address 
R - R - 1 
Repeat until R = 



SOUT* 
SOUTB* 



dst, sre 



DA 



12 12 12 



Special Output 

dst — sre 



SOUTD* 
SOUTDB* 



dst, sre, R 



Special Output and Decrement 

dst ■— sre 

Autodecrement sre address 

R - R - 1 



SOUTI* 
SOUTIB* 



dst,src,R 



Special Output and Increment 

dst — sre 

Autoincrement sre address 

R - R - 1 



SRA 

SRAB 

SRAL 



dst,n 



(13 + 3n) 



(13 + 3 n) 



Shift Right Arithmetic 

by n bits 



SRL 

SRLB 

SRLL 



dst,n 



(13 + 3 n) 



Shift Right Logical 

by n bits 



SUB 

SUBB 

SUBL 



R,src 



R 


4 


4 


4 


8 


8 


8 


Subtract 


IM 


7 


7 


7 


14 


14 


14 


R - R - sre 


IR 


7 






14 








DA 


9 


10 


12 


15 


16 


18 




X 


10 


10 


13 


16 


16 


19 





TCC 
TCCB 



cc,dst 



Test Condition Code 

Set LSB if cc is true 



TEST 
TESTB 



R 


7 


7 


7 


13 


13 


13 


Test 


IR 


8 






13 






dst OR 


DA 


11 


12 


14 


16 


17 


19 




X 


12 


12 


15 


17 


17 


20 





•Privileged instructions. Executed in system mode only. 



180 





Operands 


Addr. 
Modes 


Clock Cycles 




Mnemonics 


Word. Byte Long Word 
NS SS SL NS SS SL 


Operation 


TRDB 


dst,src,R 


IR 


25 


Translate and Decrement 

dst — src(dst) 
Autodecrement dst address 
R - R - 1 



TRDRB 



dst, src, R 



IR 



(11 + 14n) 



Translate, Decrement and Repeat 

dst — src(dst) 
Autodecrement dst address 
R - R -■ 1 
Repeat until R = 



TRIB 



dst # src,R 



Translate and Increment 

dst — src(dst) 
Autoincrement dst address 
R - R - 1 



TRIRB 



dst ( src # R 



(11 + 14n) 



Translate, Increment and Repeat 

dst — src(dst) 
Autoincrement dst address 
R - R - 1 
Repeat until R = 



TRTDB 



Translate and Test, Decrement 

RH1 - src2 (srcl) 
Autodecrement src 1 address 
R - R - 1 



TRTDRB 



srcl,src2,R 



(11 + 14n) 



Translate and Test, Deer, and Repeat 

RH1 - src2 (srcl) 
Autodecrement src 1 address 
R - R - 1 
Repeat until R = or RH1 * 



TRTIB 



srcl,src2,R 



25 



Translate and Test, Increment 

RH1 - src2 (srcl) 
Autoincrement src address 
R - R - 1 



TRTIRB 



srcl,src2,R 



(11 + 14n) 



Translate and Test, Incr. and Repeat 

RH1 - src2 (srcl) 
Autoincrement src 1 address 
R - Rl 
Repeat until R = or RH1 • * 



TSET 
TSETB 



dst 



R 


7 


7 


7 


IR 


11 






DA 


14 


15 


17 


X 


15 


15 


18 


R 


4 


4 


4 


IM 


7 


7 


7 


IR 


7 






DA 


9 


10 


12 


X 


10 


10 


13 



Test and Set 

S flag - MSB of dst 
dst - all Is 



XOR 
XORB 



R,src 



Exclusive OR 

R - R XOR src 



181 



LOWER NIBBLE (HEX). UPPER INSTRUCTION BYTE 








1 


2 


3 


4 


5 


6 


7 


8 


9 


A 


B 


C 


D 


E 


F 





ADDB 

r — in 

R — IM 


ADD 

R - IR 

n — im 


SUBB 

R — IR 
R — IM 


SUB 

R — IR 
R ~ IM 


ORB 

R — IR 
R — IM 


OR 

R — IR 
R — IM 


ANDB 

R — IR 
R ~ IM 


AND 

R ~ IR 
R — IM 


XORB 

R — IR 
R - IM 


XOR 

R - IR 
R — IM 


CPB 

R - IR 
R - IM 


CP 

R — IR 
R — IM 


S** 

Tabl* 
1 


S*« 
Tabl* 

1 


EXTEND 
INST 


EXTEND 
INST 


1 


CPL 

R ~ IR 
R — IM 


PUSHL 

IR - IR 


SUBL 

R - IR 
R — IM 


PUSH 

IR - IR 


LDL 

R — IR 
R — IM 


POPL 

IR — IR 


ADDL 

R — IR 
R - IM 


POP 

IR — IR 


MULTL 

R - IR 
R - IM 


MULT 

R — IR 
R — IM 


DIVL 

R ' — IR 
R — IM 


DIV 

R - IR 
R — IM 


S** 

Tabl* 
2 


LDL 

IR-R 


JP 

PC-IR 


CALL 

PC — IR 


2 


LDB 

R — IR 
R - IM 


LD 

R — IR 
R - IM 


RESB 

IR — IM 
R - R 


RES 

IR — IM 
R - R 


SETB 

IR — IM 
R ~ R 


SET 

IR — IM 
R — R 


BITB 

IR — IM 

R ~ R 


BIT 

IR — IM 
R — R 


INCB 

IR — IM 


INC 

IR — IM 


DECB 

IR — IM 


DEC 

IR — IM 


EXB 

R— IR 


EX 

R— IR 


LDB 

IR-R 


LD 

IR-R 


3 


LDB 

R — BA 
LDRB 

R — RA 


LD 

R — BA 
LDR 

R - RA 


LDB 

BA — R 
LDRB 

RA ~ R 


LD 

BA - R 
LDR 

RA - R 


LDA 

R - BA 
LDAR 

R — RA 


LDL 

R — BA 
LDRL 

R - RA 


RSVD 


LDL 

BA ~ R 
LDRL 

RA — R 


RSVD 


LDPS 

IR 


S** 

Tabl* 
3A 


S*« 

Tabl* 
3B 


INB 

R— IR 


IN 

R-IR 


OUTB 

IR-R 


OUT 

IR-R 


4 


ADDB 

R ~ X 

R — DA 


ADD 

■R — X 
R — -DA 


SUBB 

R - X 

R — DA 


SUB 

R - X 
R - DA 


ORB 

R — X 
R - DA 


OR 

R — X 

R — DA 


ANDB 

R - X 

R — DA 


AND 

R ~ X 

R - DA 


XORB 

R - X 
R — DA 


XOR 

R - X 

R — DA 


CPB 

R - X 

R - DA 


CP 

R — X 
R — DA 


S** 

Tabl* 

1 


S*« 

Tabl* 
1 


EXTEND 
INST 


EXTEND 
INST 


1 = 

S5 


CPL 

R — X 
R — DA 


PUSHL 

IR — X 

IR — DA 


SUBL 

R - X 

R - DA 


PUSH 

IR - X 
IR — DA 


LDL 

R — X 
R - DA 


POPL 

IR — X 
IR — DA 


ADDL 

R - X 

R — DA 


POP 

IR- X 

IR —DA 


MULTL 

R - X ' 
R - DA 


MULT 

R - X 

R - DA 


DIVL 

R - X 

R - DA 


DIV 

R — X 


S** 
Tabl* 

2 


LDL 

X-H 

DA-R 


IP 

PC-X 
PC -DA 


CALL 

PC-X 
PC -DA 


o 

p 

IS 


LOB 

R — X 
R — DA 


LD 

R - X 

R — DA 


RESB 

X - IM 

DA ~ IM 


RES 

X — IM 

DA - IM 


SETB 

X — IM 
DA - IM 


SET 

X - IM 

DA — IM 


BITB 

X - IM 
DA — IM 


BIT 

X — IM 

DA - IM 


INCB 

X — IM 

DA - IM 


INC 

X - IM 
DA — IM 


DECB 

X - IM 

DA — IM 


DEC 

X - IM 

DA — IM 


EXB 

R-X 
R-DA 


EX 

R~X 

R-DA 


LDB 

X-R 

DA-R 


LD 

X-R 
DA-R 


s 

5 7 
| 8 

i 

« 

S 9 

5 


LDB 

R — BX 


Sm 

Tabl* 

7 


LDB 

BX — R 


LD 

BX - R 


LDA 

R — BX 


LDL 

R — 'BX 


LDA 

R - X 
R — DA 


LDL 

BX — R 


RSVD 


LDPS 

PS - X 
PS - DA 


HALT 


Sm 

Tabl* 
7 


EI 

bi 


S** 

Tabl* 
7 


RSVD 


sc 


ADDB 

R ~ R 


ADD 

R — R 


SUBB 

R - R 


SUB 

■ R — R 


ORB 

R - R 


OR 

R ~ R 


ANDB 

R - R 


AND 

R - R 


XORB 

R — R 


XOR 

R — R 


CPB 

R - R 


CP 

R - R 


s** 

Tabl* 
1 


S** 

Tabl* 

1 


EXTEND 
INST. 


EXTEND 
INST. 


CPL 

R - R 


PUSHL 

IR — R 


SUBL 

R - R 


PUSH 

IR - R 


LDL 

R — R 


POPL 

R ~ IR 


ADDL 

R ~ R 


POP - 

R - IR 


MULTL 

R - R 


MULT 

R - R 


DIVL 

R — R 


DIV 

R — R 


Sm 

Tabl* 
2 


RSVD 


RET 

PC-(SP) 


RSVD 


I 

A 


LDB 

R — R 


LD 

R ~ R 


RESB 

R ~ IM 


RES 

R — IM 


SETB 

R - IM 


SET 

R — IM 


BITB 

R - IM 


BIT 

R — IM 


INCB 

R — IM 


INC 

R — IM 


DECB 

R ~ IM 


DEC 

R — IM 


EXB 

R-R 


EX 

R-R 


TCCB 

R 


TCC 

R 


B 


DAB 

R 


EXTS 

EXTSB 

EXTSL 

R 


Sm 

Tabl* 
4 


S— 

Table 

4 


ADCB 

R - R 


ADC 

R — R 


SBCB 

R - R 


SBC 

R — R 


S** 

Tabl* 
5 


RSVD 


S** 

Tabl* 
6 


S** 

Tabl* 
S 


RRDB 

R 


LDK 

R-IM 


RLDB 

R 


RSVD 




LDB 

Rs~ IM 
































































D 


CALR 

PC — RA 






























































E 


JR 

PC - RA 
































































DJNZ 
DBINZ 

PC - RA 

































































Op Code Map 



Notes: 



1) Reserved Instructions (RSVD) should not be 
used. The result of their execution is not defined. 

2) The execution of an extended instruction will 
result in an Extended Instruction Trap if the EPA 
bit in the FCW is a zero. If the flag is a one the 
Extended Instruction will be executed by the EPU 
function. 



182 



« 2 

o 

6 

1 3 



2 7 



oc 


OD 


COMB 

IR 


COM 

IR 


CPB 

IR.IM 


CP 

IR.IM 


NEGB 

IR 


NEG 

IR 


RSVD 


RSVD 


TESTB 

IR 


TEST 

IR 


LDB 

IR— IM 


LD 

IR— IM 


TSETB 

IR 


TSET 

IR 


RSVD 


RSVD 


CLRB 

IR 


CLR 

IR 




PUSH 

IM 



4C 


4D 


COMB 

X 

DA 


COM 

X 

DA 


CPB 

X.IM 

DA.IM 


CP 

X,IM 
DA,IM 


NEGB 

X 

DA 


NEG 

X 

DA 


RSVD 


RSVD 


TESTB 

X 
DA 


TEST 

X 

DA 


LDB 

X-IM 
DA-IM 


LD 

X-IM 
DA-IM 


TSETB 

X 

DA 


TSET 

X 

DA 


RSVD 


RSVD 


CLRB 

X 

DA 


CLR 

X 

DA 



8C 


8D 


COMB 

R 


COM 

R 


LDCTLB 

R-FLGS 


SETFLG 


NEGB 

R 


NEG 

R 


RSVD 


RESFLG 


TESTB 

R 


TEST 

R 


RSVD 


COMFLG 


TSETB 

R 


TSET 

R 


RSVD 


NOP 


CLRB 

R 


CLR 

R 


LDCTLB 

FLGS-R 





Table 1. Upper Instruction Byte 





1C 




5C 




9C 


u ° 

SO 1 
UP 


RSVD 




RSVD 




RSVD 


LDM 

R— IR 


LDM 

R-X 
R-DA 










« B 
gg 

B 2 

o B 

"* 9 

o 9 


TESTL 

IR 


TESTL 

X 
DA 




TESTL 

R 


LDM 

IR— R 


LDM 

X-R 
DA-R 









INIB 


INI 





IR— IR 


IR— IR 




INIRB 


INK 




IR— IR 


IR— IR 




SINIB 


SINI 


1 


IR— IR 


IR — IR 




SINIRB 


SINIR 




IR— IR 


IR— IR 




OUTIB 


OUTI 


2 


IR— IR 


IR— IR 




OTIRB 


outir 




IR— IR 


IR — IR 




SOUTIB 


SOUTI 


3 


IR— IR 


IR— IR 




SOTIRB 


sonR 




IR— IR 


IR— IR 


INB 


IN 


O < 


R-DA 


R-DA 


P 

o 






B 


SINB 


SIN 


S 5 


R-DA 


R-DA 


5 






2 


OUTB 


OUT 


i 6 


DA-R 


DA-R 


w 






BO 


SOUTB 


SOUT 


2 7 


DA-R 


DA-R 




►J 






INDB 


IND 


8 


IR— IR 


IR— IR 




INDRB 


INDR 




IR — IR 


IR — IR 




SINDB 


SIND 


9 


IR — IR 


IR— IR 




SINDRB 


SINDR 




IR— IR 


IR— IR 




OUTDB 


OUTD 


A 


IR— IR 


IR — IR 




OTDRB 


OTDR 




IR— IR 


IR — IR 




SOUTDB 


SOUTD 


B 


IR— IR 


IR — IR 




SOTDRB 


SOTDR 




IR— IR 


IR — IR 



Table 2. Upper Instruction Byte 



Table 3. Upper Instruction Byte 



183 



B2 


B3 


RLB 

(1 bit) 
R 


RL 

(1 bit) 
R 


SLLB 

R 
SRLB 

R 


SLL 

R 
SRL 

R 


RLB 

(2 bits) 
R 


RL 

(2 bits) 
R 


SDLB 

R 


SDL 

R 


RRB 

fl bit) 
R 


RR 

(1 bit) 
R 


RSVD 


SLLL 

R 
SRLL 


RRB 

(2 bits) 
R 


RR 

(2 bits) 
R 


RSVD 


SDLL 

R 


RLCB 

(1 bit) 
R 


RLC 

(1 bit) 
R 


SLAB 

R 

SRAB 

R 


SLA 

R 
SRA 

R 


RLCB 

(2 bits) 
R 


RLC 

(2 bits) 
R 


SDAB 

R 


SDA 

R 


RRCB 

(1 bit) 
R 


RRC 

(1 bit) 
R 


RSVD 


SLAL 

R 
SRAL 


RRCB 

(2 bits) 
R 


RRC 

(2 bits) 
R 


RSVD 


SDAL 

R 



o 

H 

1 ' 



Uj 9 



BA 


BB 


CPIB 

IR 


CPI 

IR 


LDIB 

IR— IR 
LDIRB 

IR — IR 


LDI 

IR — IR 
LDIR 

IR — IR 


CPSIB 

IR 


CPSI 

IR 


RSVD 


RSVD 


CPRIB 

IR 


CPIR 

IR 


RSVD 


RSVD 


CPSIRB 

IR 


CPSIR 

IR 


RSVD 


RSVD 


CPDB 

IR 


CPD 

IR 


LDDB 

IR-IR 
LDDRB 
IR — IR 


LDD 
IR — IR 
LDDR 

IR — IR 


CPSDB 

IR 


CPSD 

IR 


RSVD 


RSVD 


CPDRB 

IR 


CPDR 

IR 


RSVD 


RSVD 


CPSDRB 

IR 


CPSDR 

IR 


RSVD 


RSVD 



7B 


7D 


IRET 

PC-(SSP) 


RSVD 


RSVD 


RSVD 


RSVD 


LDCTL 

R-FCW 


RSVD 


LDCTL 

R-RFRSH 


RSVD 


LDCTL 

R- 
PSAPSEG 


RSVD 


LDCTL 

R- 
PSAPOFF 


RSVD 


LDCTL 

R-NSPSEG 


RSVD 


LDCTL 

R-NSPOFF 


MSET 


RSVD 


MRES 


RSVD 


MBIT 


LDCTL 

FCW-R 


RS 


VD 


LDCTL 

RFRSH-R 


' 


' 


LDCTL 

PSAPSEG 
-R 


MREQ 

R 


LDCTL 

PSAPOFF 
-R 


RSVD 


LDCTL 

NSPSEG-R 


RSVD 


LDCTL 

NSPOFF-R 



Table 4. 
Upper Instruction Byte 



Table 5. 
Upper Instruction Byte 



Table 6. 
Upper Instruction Byte 



Table 7. 
Upper Instruction Byte 



184 



Topical Index 
















Data 


Addressing 


Flags 




Instruction Description 


Mnemonic 


Types 


Modes 


Affected 




Arithmetic 












Add with Carry 


ADC 


B, W 


R 


C, Z, S, V, D 1 


', H 1 


Add 


ADD 


B, W, L 


R, IM, IR, DA, X 


C, Z, S, V, D' 


l ,H' 


Compare (Immediate) 


CP 


B, W 


IR, DA, X 


C, Z, S, V 




Compare (Register) 


CP 


B, W, L 


R, IM, IR, DA, X 


C, Z, S, V 




Decimal Adjust Bit 


DAB 


B 


IR 


C, Z, S 




Decrement 


DEC 


B, W 


R, IR, DA, X 


Z, S, V 




Divide 


DIV 


W, L 


. R, IM, IR, DA, X 


C, Z, S, V 




Extend Sign 


EXTS 


B, W, L 


R 


C, Z, S, V 




Increment 


INC 


B, W 


R, IR, DA, X 


z, S, V 




Multiply 


MULT 


W, L 


R, IM, IR, DA, X 


C, Z, S, Vo 




Negate 


NEG 


B, W 


R, IR, DA, X 


C, Z, S, V 




Subtract with Carry 


SBC 


B, W 


R 


C, Z, S, V, D 1 


',H' 


Subtract 


SUB 


B, W, L 


R, IM, IR, DA, X 


C, Z, S, V, D 1 


,H' 


Bit Manipulation 












Bit Test 


BIT 


B, W 


R 


z 




Bit Reset (Static) 


RES 


B, W 


R, IR, DA, X 


— 




Bit Reset (Dynamic) 


RES 


B, W 


R 


— 




Bit Set (Static) 


SET 


B, W 


R, IR, DA, X 


— 




Bit Set (Dynamic) 


SET 


B, W 


R 


— 




Bit Test and Set 


TSET 


B, W 


R, IR, DA, X 


S 




Block Transfer and String Manipulation 












Compare and Decrement 


CPD 


B, W 


IR 


C, Z, S, V 




Compare, Decrement, and Repeat 


CPDR 


B, W 


IR 


C, Z, S, V 




Compare and Increment 


CPI 


B, W 


IR 


C, Z, S, V 




Compare, Increment, and Repeat 


CPIR 


B, W 


IR 


C, Z, S, V 




Compare String and Decrement 


CPSD 


B, W 


IR 


C, Z, S, V 




Compare String, Decrement, and Repeat 


CPSDR 


B, W 


IR 


G, Z, S, V 




Compare String and Increment 


CPSI 


B, W 


IR 


C, Z, S, V 




Compare String, Increment, and Repeat 


CPSIR 


B, W 


IR 


a z, s, v 




Load and Decrement 


LDD 


B, W 


IR 


V 




Load, Decrement, and Repeat 


LDDR 


B, W 


IR 


V 




Load and Increment 


LDI 


B, W 


IR 


V 




Load, Increment, and Repeat 


LDIR 


B, W 


IR 


V 




Translate and Decrement 


TRDB 


B 


IR 


Z, V 




Translate, Decrement, and Repeat 


TRDRB 


B 


IR 


z, V 




Translate and Increment 


TRIB 


B 


IR 


z, V 




Translate, Increment, and Repeat 


TRIRB 


B 


IR 


z, V 




Translate, Test, and Decrement 


TRTDB 


B 


IR 


z, V 




Translate, Test, Decrement, Repeat 


TRTDRB 


B 


IR 


z, V 




Translate, Test, and Increment 


TRTIB 


B 


IR 


Z, V 




Translate, Test, Increment, and Repeat 


TRTIRB 


B 


IR 


z, V 




CPU Control Instructions 












Complement Flag 


COMFLG 


— 


— 


c 2 , Z 2 , S 2 , P 2 , 


V 2 . 


Disable Interrupt 


DI 


— 


— 


— 




Enable Interrupt 


EI 


— 


— 


>— 




Halt 


HALT 


— 


— 


— 




Load Control Register (from register) 


LDCTL 


— 


R 


c 2 , Z 2 , S 2 , P 2 , 


D 2 ,H 2 


Load Control Register (to register) 


LDCTL 


— 


— 


— 




Load Program Status 


LDPS 


— 


IR, DA, X 


C, Z, S, P, D, 


H 


Multi-Bit Test 


MBIT 


— 


— 


s 




Multi-Micro Request 


MREQ 


— 


— 


z, s 




Multi-Micro Reset 


MRES 


— 


— 


— 




Multi-Micro Set 


MSET 


— 


— 


— 




No Operation 


NOP 


— 


— 


— 




Reset Flag 


RESFLG 


— 


— 


c 2 , Z 2 , S 2 , P 2 , 


V 2 


Set Flag 


SETFLG 


— 


— 


c 2 , Z 2 , S 2 , P 2 , 


V 2 


1. Flag affected only for byte operation. 












2. Flag modified only if specified by the instruction. 











185 



Topical Index (Continued) 
















Data 


Addressing 


Flags 


Instruction Description 


Mnemonic 


Types 


Modes 


Affected 


Input/Output Instructions 3 






Regular 


Special 




Input 


(S)IN 3 


B, W 


IR, DA 


(DA) 


— 


Input and Decrement 


(S)IND 3 


B, W 


IR 


(IR) 


V 


Input, Decrement and Repeat 


(S)INDR 3 


B, W 


IR 


(IR) 


V 


Input and Increment 


(S)INI 3 


B, W 


IR 


(IR) 


V 


Input, Increment, and Repeat 


(S)INIR 3 


B, W 


IR 


(IR) 


V 


Output 


(S)OUT 3 


B, W 


IR, DA 


(DA) 


— 


Output and Decrement 


. (S)OUTD 3 


B, W 


IR 


(IR) 


V 


Output, Decrement, and Repeat 


(S)OUTDR 3 


B, W 


IR 


(IR) 


V 


Output and Increment 


(S)OUTI 3 


B, W 


IR 


(IR) 


V 


Output, Increment, and Repeat 


(S)OUTIR 3 


B, W 


IR 


(IR) 


V 


Logical Instructions 












And 


AND 


B, W 


R, IM, IR, 


DA, X 


Z, S, P 


Complement 


COM 


B, W 


R, IR, DA 


, x 


Z, S, P 


Or 


OR 


B, W 


R, IM, IR, 


DA, X 


Z, S, P 


Test 


TEST 


B, W, L 


R, IR, DA, 


,x 


z, S, P 


Test Condition Code 


TCC 


B, W 


R 




— 


Exclusive Or 


XOR 


B, W 


R, IM, IR, 


DA,X 


Z, S, P 


Program Control Instructions 












Call Procedure 


CALL 


— 


IR, DA, X 




— 


Call Procedure Relative 


CALR 


_ 


RA 




— 


Decrement, Jump if Not Zero 


DJNZ 


B, W 


RA 




— 


Interrupt Return 


IRET 


— 


— 




C, Z, S, P, D, H 


Jump 


JP 


— 


IR, DA, X 




— 


Jump Relative 


JR 


— 


RA 




— 


Return From Procedure 


RET 


— 


— 




— 


System Call 


SC 


- 


- 




- 


Rotate and Shift Instructions 












Rotate Left 


RL 


B, W 


R 




— 


Rotate Left Through Carry 


RLC 


B, W 


R 




C, Z, S, V 


Rotate Left Digit 


RLDB 


B 


R 




z, s 


Rotate Right 


RR 


B, W 


R 




C, Z, S,\V 


Rotate Right Through Carry 


RRC 


B, W 


R 




c, z, s/v 


Rotate Right Digit 


RRDB 


B 


R 




z, s 


Shift Dynamic Arithmetic 


SDA 


B, W, L 


R 




C, Z, S, V 


Shift Dynamic Logical 


SDL 


B, W, L 


R 




C, Z, S, V 


Shift Left Arithmetic 


SLA 


B, W, L 


R 




C, Z, S, V 


Shift Left Logical 


SLL 


B, W, L 


R 




C, Z, S, V 


Shift Right Arithmetic 


SRA 


B, W, L 


R 




C, Z, S, V 


Shift Right Logical 


SRL 


B, W, L 


R 




C, Z, S, V 



3. Each I/O instruction has a Special counterpart used to alert other devices that a Special I/O transaction is occur- 
ring. The Special I/O mnemonic is S + Regular mnemonic. Refer to section 6.2.8 for further details. 



186 



( RO { 7 RHO 0J7 RLO o| 




I Rl [l5 RH1 RL1 0| 




( R2 | RH2 ;' RL2 ] 




( R3 | RH3 ; RL3 | 




( R4 [ RH4 ; RL4 | 




( R5 | RHS | RL5 | 




| R« | RHS ; RL6 | 




I R7 | RH7 ;' RL7 | 




[ RS | IS o| 




I R9 | | 




[ RIO ( | 




( R11 | ) 




( R12 | | 




( R13| | 




1 HI* | SYSTEM STACK POINTER (SEG. NO.) 1 


RM| NORMAL STACK POINTER (SEG.' NO.) (NSPSEGI 1 — 




j «15 | SYSTEM STACK POINTER (OFFSET) I 


( R1s| NORMAL STACK POINTER (OFFSETI (NSPOFF) | 



| 7 RHO ;7 RLO o| 




| IS RHt | RL1 o| 




| RH2 j RL2 | 




| RH3 ; RL3 




| RH4 j RL4 | 




| RHS ; RL5 




| RH6 ; | 




| RH7 ; RL6 RL7 | 




|15 0| 




























15' | SYSTEM STACK POINTER I 


| NORMAL STACK POINTER (NSP) | 



Z8001 General Purpose Registers 



Z8002 General Purpose Registers 



Register 



RQO RRO 



RR2 



RQ4 RR4 



RR6 



RQ8 RR8 



RQ12 RR12 



RR14 



RO 


RHO 


Rl 


RH1 


R2 


RH2 


R3 


RH3 


R4 


RH4 


R5 


RHS 


R6 


RH6 


R7 


RH7 


R8 


RLO 


R9 


RLI 


RIO 


RL2 


Rli 


RL3 


R12 


RL4 


R13 


RL5 


R14 


RL6 


R15 


RL7 



Binary 

0000 
0001 
0010 
0011 
0100 
0101 
0110 
0111 
1000 
1001 
1010 
1011 
1100 
1101 
1110 

mi 



Binary Encoding for Register Fields 



SYSTEM STACK 




LOW 
ADDRESS 

SYSTEM SP -»- 
AFTER TRAP 
OR INTERRUPT 




LOW 
ADDRESS 


POINTER AFTER m 
TRAP OR 


IDENTIFIER 


IDENTIFIER 




INTERRUPT 


FCW 


FCW 






PC 


PC SEGMENT 




POINTER BEFORE _ 




SYSTEM SP -*• 
BEFORE TRAP 
OR INTERRUPT 


PC OFFSET 




TRAP OR 
















-*— 1 WORD — »- 


HIGH 
ADDRESS 


-*— 1 WORD-*- 


HIGH 
ADORESS 



Format of Saved Program Status in the System Stack 



187 



CONTROL BITS 



E 


s/n|epa| 


i/i |nvi[^', , ,\- , j C 


Izls 


P/vl-D 


« 






| PROGRAM COUNTER 1 


15 




NONSEGMENTED 









H£<f>J^& 


."TiL^..:: 


w 


^■^iib;: 




:M{M 


CONTROL BITS 




FLAGS 






£ 


s/n|epa| 




|z|. 


P/vj D 


« 


siH 




B3 


PC SEGMENT NUMBER [ 


' 






'-i A ""A 




| PROGRAM COUNTER OFFSET | 



SEGMENTED 



Program Status Blocks 



BYTE OFFSET 
HEX DECIMAL 



18 24 



38 56 

3C 60 

40 64 

44 66 



23A 570 



| SEG. NO. | 


| UPPER I 


00...0 j 


Z6001 




OFFSET 


IMPLIED 
Z8002 




RESERVED 

EXTENDED 

INSTRUCTION 

TRAP 

PRIVILEGED 

INSTRUCTION 

TRAP 

.SYSTEM 
CALL 
TRAP 

SEGMENT 
TRAP 

NONMASKABLE 
INTERRUPT 

NON-VECTORED 
INTERRUPT 

VECTORED 
INTERRUPTS 




RESERVED 


FCW 


FCW 


I SEG | 


PC 


PC OFFSET 


RESERVED 


FCW 


FCW 


I SEG | 


PC 


PC OFFSET 


RESERVED 


FCW 


FCW 


I SEG | 


PC 


PC OFFSET 


RESERVED 


NOT USED 


FCW 


| SEG | 


PC OFFSET 


RESERVED 


FCW 


FCW 


I SEG I 


PC 


PC OFFSET 


RESERVED 


FCW 


FCW 


| SEG | 


PC 


PC OFFSET 


RESERVED 


FCW 


FCW 


| SEG | 


PC, 


PC OFFSET 


I SEG | 


PC 2 


PC 2 OFFSET 


| SEG | 


PC 3 


PC 3 OFFSET 


* 


i 


I SEG | 


PC n 


PC„ OFFSET 



BYTE OFFSET 
DECIMAL HEX 



540 21 C 



Program Status Area 



188 



Condition Codes 

Code 

F 

Z 

NZ 

C 

NC 

PL 

MI 

NE 

EQ 

OV 

NOV 

PE 

PO 

GE 

LT 
GT 
LE 

UGE 



ULT 
UGT 
ULE 



Meaning 

Always false* 
Always true 
Zero 
Not zero 
Carry 
No carry 
Plus 
Minus 
Not equal 
Equal 
Overflow 
No overflow 
Parity even 
Parity odd 
Greater than 
or equal 
Less than 
Greater than 
Less than or 
equal 
Unsigned 
greater than 
or equal 
Unsigned 
less than 
Unsigned 
greater than 
Unsigned less 
than or equal 



Flag Setting 



Z = 1 
Z = 
C = 1 
C = 
S = 
S = 1 
Z = 
Z = 1 

V = 1 

V = 

p = 1 

P = 

(S XOR V) = 

(S XOR V) = 1 

(Z OR (S XOR V)) = 

(Z OR (S XOR V)) = 1 

C = 



Binary 

0000 
1000 
0110 
1110 
0111 

mi 

1101 
0101 
1110 

ono 

0100 
1100 
0100 
1100 
1001 

0001 
1010 
0010 

mi 



C = 1 




0111 


((C =0) AND(Z 


= 0)) = 1 


1011 


(C OR Z) = 1 




0011 



This table provides the condition codes and the flag settings they represent. 

Note that some of the condition codes correspond to identical flag settings: i.e., Z-EQ, NZ-NE, 
NC-UGE, PE-OV, PO-NOV. 

'Presently not implemented in PLZ/ASM Z8000 compiler. 



7 6 5 4 3 2 10 


I II I I I I I I 


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 


1 1 II 1 1 1 1 1 1 1 1 


Address n 


| | 


Address n (even) Address n + 1 


I UPPER BYTE I LOWER BYTE 


Address n Address n + 1 


I UPPER WORD/UPPER BYTE I I 


Address n + 2 Address n + 3 ? 


I J LOWER WORD/LOWER BYTE I 
1 i ii j_ l 1 ..J L 1 1 1 1 1 1 1 1 J 



BITS IN A BYTE 



BITS IN A WORD 



Addressable Data Elements 



189 



Z8000 Addressing Modes 



Addressing Mode 


Operand Addressing 




Operand Value 


In the Instruction In a Register 


In Memory 




B 




- 










Register 


REGISTER ADDRESS 


OPERAND | 












IN 










Immediate 


OPERAND | 


In the Instruction 








IR 

Indirect 




r- 










[ REGISTER ADDRESS 






whose address Is in the 


Register 












register 


DA 








The content of the location 


Direct 
















Address 








X 








-* 






Index 


REGISTER ADDRESS 


~ 


INDEX 


Hon whose address is the 


BASE AODRESS 




fc| OPERAND | 


address in the instruction 






plus the content of the 
working register. 










RA 






—^ 




The content of the location 


Relative 




L_ 


PC VALUE 


whose address is the 


DISPLACEMENT 




fc-l OPERAND 1 


counter, offset by the 




KS 








displacement in the 
instruction 


BA 








^ 




The content of the location 
whose address is the 




REGISTER ADDRESS 


"* 


BASE ADDRESS 


Address 


DISPLACEMENT 




*A OPERAND 1 


address In the register, 
offset by the displacement 
in the instruction 












BX 












The content of the loca- 
tion whose address is 


Base 


REGISTER ADDRESS 




BASE ADDRESS 


,f7Y 


Index 


REGISTER ADDRESS 


INDEX 


»-| OPERAND | 


the address in a register 














another register. 



*Do not use RO or RRO as indirect, index, or base registers. 



Powers of 2 and 16 



2 048 
4 096 
8 192 
16 384 
32 768 
65 536 
131 072 
262 144 
524 288 

1 048 576 

2 097 152 
4 194 304 
8 388 608 

16 777 216 



= 16 2 


256 


2 


- 16 3 


4 096 


3 


- 16 4 


65 536 


4 


- 16 5 


1 048 576 


5 


- 16 6 


16 777 216 


6 


- 16 7 


268 435 456 


7 


- 16 s 


4 294 967 296 


8 


= • 16' 


68 719 476 736 


9 


- 16'° 


1 099 511 627 776 


10 


- 16" 


17 592 186 044 416 


11 


= 16 12 


281 474 976 710 656 


12 


- 16 11 


4 503 599 627 370 496 


13 


- 16" 


72 057 594 037 927 936 


14 


= 16' 5 


1 152 921 504 606 846 976 
Powers of 16 


15 



190 





8 




7 




6 




5 




4 




3 




2 




1 


Hex 


Decimal 


Hex 


Decimal 


Hex 


Decimal 


Hex 


Decimal 


Hex 


Decimal 


Hex 


Decimal 


Hex 


Decimal 


Hex 


Decimal 


















































1 


268,435,456 


1 


16,777,216 


1 


1,048,576 


1 


65,536 


1 


4,096 


1 


256 


1 


16 


1 


1 


2 


536,870,912 


2 


33,554,432 


2 


2.097.152 


2 


131,072 


2 


8,192 


2 


512 


2 


32 


2 


2 


3 


805,306,368 


3 


50,331,648 


3 


3,145,728 


3 


196,608 


3 


12,288 


3 


768 


3 


48 


3 


3 


4 


1,073,741,824 


4 


67,108,864 


4 


4.194,304 


4 


262,144 


4 


16.384 


4 


1,024 


4 


64 


4 


4 


5 


1,342,177,280 


5 


83,886,080 


5 


5.242,880 


5 


327,680 


5 


20,480 


5 


1,280 


5 


80 


5 


5 


6 


1,610,612,736 


6 


100,663,296 


6 


6,291,456 


6 


393,216 


6 


24,576 


6 


1,536 


6 


96 


6 


6 


7 


1,879,048,192 


7 


117,440,512 


? 


7.340,032 


7 


458,752 


7 


28.672 


7 


1,792 


7 


112 


7 


7 


8 


2,147,483,648 


8 


134,217,728 


8 


8,388,608 


8 


524,288 


8 


32.768 


8 


2,048 


8 


128 


8 


8 


9 


2,415,919,104 


9 


150,994,944 


9 


9,437,184 


9 


589,824 


9 


36.864 


9 


2,304 


9 


144 


9 


9 


A 


2,684,354,560 


A 


167,772,160 


A 


10,485.760 


A 


655,360 


A 


40,960 


A 


2,560 


A 


160 


A 


10 


B 


2,952,790,016 


B 


184,549,376 


B 


11,534,336 


B 


720,896 


B 


45,056 


B 


2,816 


B 


176 


B 


11 


C 


3,221,225,472 


C 


201,326,592 


C 


12,582,912 


C 


786.432 


C 


49,152 


C 


3,072 


C 


192 


C 


12 


D 


3,489,660,928 


D 


218,103,808 


D 


13,631,488 


D 


851.968 


D 


53,248 


D 


3,328 


D 


208 


D 


13 


E 


3,758,096,384 


E 


234,881,024 


E 


14,680,064 


E 


917.504 


E 


57,344 


E 


3,584 


E 


224 


E 


14 


F 


4,026,531.840 


F 


251,658,240 


F 


15,728,640 


F 


983.040 


F 


61,440 


F 


3,840 


F 


240 


F 


15 



6 5 4 3 

Hexadecimal and Decimal Interger Conversion Table 



To Convert Hexadecimal to Decimal 

1 . Locate the column of decimal numbers corresponding to 
the left-most digit or letter of the hexadecimal: select 
from this column and record the number that cor- 
responds to the position of the hexadecimal digit or 
letter. 

2. Repeat step 1 for the units (second from the left) 
position. 

3. Repeat step 1 for the units (third from the left) position. 

4. Add the numbers selected from the table to form the 
decimal number. 

To convert integer numbers greater than the capacity of 
the table, use the techniques below: 

Hexadecimal to Decimal 

Succesive cumulative mulitplication from left to right, 
adding units position. 

ExampJe: D34 16 = 3380 10 

D = 13 

x!6 

208 

3 = +13 

211 
x!6 
3376 

4 = _+4 

3380 



Example: 



To Convert Decimal to Hexadecimal 

1 . (a) Select from the tabel the highest decimal number 

that is equal to or less than the number to be 
converted. 

(b) Record the hexadecimal of the column containing 
the selected number. 

(c) Subtract the selected decimal from the number to be 
converted. 

2. Using the remainder from step 1(c) repeat all of step 1 
to develop the second position of the hexadecimal (and 
a remainder). 

3. Using the remainder from step 2 repeat all of step 1 to 
develop the units position of the hexadecimal. 

4. Combine terms to form the hexadecimal number. 
Decimal to Hexadecimal 

Divide and collect the remainder in reverse order. 
Exampte: 3380 10 = D34 16 Exam ple; 

1613380 remainder 



Conversion of 
Hexadecimal Value 
D34 


161 
16[ 


211 
13 


S 


1. D 


3328 






K D 


2. 3 


48 








3.4 


__6 








4. Decimal 


3380 









Conversion of 
Decimal Value 

3380 

1. D - 3328 

52 

2. 3 ^43 

4 

3. 4 -4 

4. Hexadecimal D34 



191 



ASCII Characters 



Meaning 



Character 



00 

01 

02 

03 
-04 - 

05 

06 

07 
-08 ■ 

09 

0A 

OB 
-0C ■ 

OD 

OE 

OF 

- lO- 
ll 
12 
13 

- 14 - 
15 
16 
17 

-18 - 

19 

1A 

IB 
-IC ■ 

ID 

IE 

IE 
-20- 

21 

22 

23 
-24 ■ 

25 

26 

27 
-28 - 

29 

2A 

2B 
-2C- 

2D 

2E 

2F 
-30- 

31 

32 

33 
-34 - 

35 

36 

37 
-38- 

39 

3A 

3B 
■ 3C - 

3D 

3E 

3F 



NUL 
SOH 

STX 

ETX 

-EOT - 

ENQ 

ACK 

BEL 

BS - 

HT 

LF 

VT 

FF - 

CR 

SO 

SI 

- DLE- 

DC1 

DC2 

DC3 

■ DC4 - 

NAK 

SYN 

ETB 

-CAN- 

EM 
SUB 
ESC 

FS - 

GS 

RS 

US 

SP- 



NULL Character 
Start of Heading 
Start of Text 
End of Text 

- End of Transmission 

Enquiry 

Acknowledge 
Bell 

-Backspace 

Horizontal Tabulation 
Line Feed 
Vertical Tabulation 

- Form Feed 

Carriage Return 

Shift Out 
Shift In 

- Data Link Escape 

Device Control 1 

Device Control 2 
Device Control 3 

- Device Control 4 

Negative Acknowledge 
Synchronous Idle 

End of Transmission Block 

- Cancel . : 

End of Medium 
Substitute 

Escape 

- File Separator 

Group Separator 

Record Separator 
Unit Separator 

- Space 



40 
41 
42 
43 

- 44 ■ 
45 
46 
47 

-48 - 

49 

4A 

4B 
-4C - 

4D 

4E 

4F 

- 50 - 
51 
52 
53 

-54 - 
55 
56 
57 

- 58- 
59 

'5A 

5B 
-5C ■ 

5D 

5E 

5F 
-60- 

61 

62 

63 
-64- 

65 

66 

67 

- 68 - 
69 
6A 
6B 

• 6C- 

6D 

6E 

6F 

70 - 
■71 

72 

73 

■ 74 - 
75 
'76 
77 
78 - 
79 
7A 
7B 

■ 7C ■ 
7D 
7E 
7F 



A 
B 
C 

- D- 
E 

F 
G 
-H- 
I 
J 
K 

- L - 
M 
N 
O 

- P - 
Q 
R 

S 

- T- 
U 
V 
W 

- X - 
Y 

Z 

( 

-\ " 

] 



{ 
- i — 

} 

DEL 



192 



SALES OFFICES 



AUSTRALIA 

NSW 2027 EDGECLIFF 

Suite 21 1 , Edgecliff centre 
203-233, New South Head Road 
Tel. (61-2)327.39.22 
Telex: 071 126911 TCAUS 
Telefax: (61-2) 327.61.76 

BRAZIL 

05413 SAO PAULO 

R. Henrique Schaumann 286-CJ33 
Tel. (55-1 1)883-5455 
Telex: (391)1 1-37988 "UMBR BR" 
Telefax: 11-551-128-22367 

CANADA 

BRAMPTON, ONTARIO 

341 Main St. North 
Tel. (416) 455-0505 
Telefax: 416-455-2606 

CHINA 

BEIJING 

Beijing No. 5 Semiconductor 

Device Factory 

14 Wu LuTong Road 

Da Shang Mau Wai 

Tel. (861) 2024378 

Telex 222722 STM CH 

DENMARK 

2730 HERLEV 

Herlev Torv, 4 

Tel. (45-42) 94.85.33 

Telex: 3541 1 

Telefax: (45-42) 948694 

FINLAND 

LOHJASF-08150 

Karjalankatu, 2 
Tel. 12.155.11 
Telefax. 12.155.66 

FRANCE 

94253 GENTILLY Cedex 

7 - avenue Gallieni - BR 93 
Tel.: (33-1) 47.40.75.75 
Telex: 632570 STMHQ 
Telefax: (33-1) 47.40.79.10 

67000 STRASBOURG 

20, Place des Halles 
Tel. (33) 88.75.50.66 
Telex: 870001 F 
Telefax: (33) 88.22.29.32 



HONG KONG 

WANCHAI 

22nd Floor - Hopewell centre 
183 Queen's Road East 
Tel. (852-5) 8615788 
Telex: 60955 ESGIES HX 
Telefax: (852-5) 8656589 

INDIA 

NEW DELH1 110001 

Liason Office 

62, Upper Ground Floor 

World Trade Centre 

Barakhamba Lane 

Tel. 3715191 

Telex: 031-66816 STM I IN 

Telefax: 3715192 



ITALY 

20090 ASSAGO (Ml) 

V.le Milanofiori - Strada 4 - Palazzo A/4/A 
Tel. (39-2)89213.1 (10 linee) 
Telex: 330131 -330141 SGSAGR 
Telefax: (39-2) 8250449 

40033 CASALECCHIO Dl RENO (BO) 

ViaR. Fucini, 12 
Tel. (39-51)591914 
Telex: 512442 
Telefax: (39-51) 591305 



00161 ROMA 

Via A. Torlonia, 15 
Tel. (39-6) 8443341 
Telex: 620653 SGSATE I 
Telefax: (39-6) 8444474 

JAPAN 

TOKYO 108 

Nisseki - Takanawa Bid. 4F 

2-18-10 Takanawa 

Minato-Ku 

Tel. (81-3) 280-4121 

Telefax: (81-3) 280-4131 

KOREA 

SEOUL 121 

8th floor Shinwon Building 
823-14, Yuksam-Dong 
Kang-Nam-Gu 
Tel. (82-2) 553-0399 
Telex: SGSKOR K29998 
Telefax: (82-2) 552-1051 

NETHERLANDS 

5612 AM EINDHOVEN 

Dillenburgstraat25 
Tel.: (31-40) 550015 
Telex: 51186 
Telefax: (31-40) 528835 



SINGAPORE 

SINGAPORE 2056 

28 Ang Mo Kb - Industrial Park 2 
Tel. (65) 4821411 
Telex: RS 55201 ESGIES 
Telefax: (65) 4820240 

SPAIN 

08021 BARCELONA 

Calle Platon, 6 4 ,F Floor, 5 th Door 
Tel. (34-3) 4143300-4143361 
Telefax: (34-3) 2021461 



28027 MADRID 

Calle Albacete, 5 
Tel. (34-1) 4051615 
Telex: 27060 TCCEE 
Telefax: (34-1) 4031 134 

SWEDEN 

S-16421 KISTA 

Borgarfjordsgatan, 13 - Box 1094 
Tel.: (46-8) 7939220 
Telex: 12078 THSWS 
Telefax: (46-8) 7504950 

SWITZERLAND 

1218 GRAND-SACONNEX (GENEVA) 

Chemin Francois-Lehmann, 18/A 
Tel. (41-22) 7986462 
Telex: 415493 STM CH 
Telefax: (41-22) 7984869 

TAIWAN 

TAIPEI 

12th Floor 

571, Tun Hua South Road 
Tel. (886-2) 755-41 11 
Telex: 10310 ESGIETW 
Telefax: (886-2) 755-4008 

UNITED KINGDOM and EIRE 

MARLOW, BUCKS 

Planar House, Parkway 

Globe Park 

Tel.: (44-628) 890800 

Telex: 847458 

Telefax: (44-628) 890391 



SALES OFFICES 



U.S.A. 

NORTH & SOUTH AMERICAN 
MARKETING HEADQUARTERS 
1000 East Bell Road 
Phoenix, AZ 85022-2699 
(1)-(602) 867-6100 

SALES COVERAGE BY STATE 

ALABAMA 

Huntsville - (205) 533-5995 

ARIZONA 

Phoenix - (602) 867-6340 

CALIFORNIA 

Santa Ana -(71 4) 957-601 8 
San Jose - (408) 452-8585 

COLORADO 

Boulder (303) 449-9000 

ILLINOIS 

Schaumburg - (708) 517-1890 

INDIANA 

Kokomo- (317) 459-4700 

MASSACHUSETTS 

Lincoln -(61 7) 259-0300 

MICHIGAN 

Livonia -(31 3) 462-4030 



NEW JERSEY 

Voorhees - (609) 772-6222 

NEW YORK 

Poughkeepsie - (914) 454-8813 

NORTH CAROLINA 

Raleigh -(919) 787-6555 

TEXAS 

Carrollton- (214) 466-8844 

FOR RF AND MICROWAVE 
POWER TRANSISTORS CONTACT 
THE FOLLOWING REGIONAL 
OFFICES IN THE U.S.A. 

NEW JERSEY 

Somerset (201) 563-6575 

PENNSYLVANIA 

Montgomeryville - (215) 362-8500 



WEST GERMANY 

6000 FRANKFURT 

Gutleutstrabe 322 
Tel. (49-69) 237492 
Telex: 176997 689 
Telefax: (49-69) 231957 
Teletex: 6997689=STVBP 

8011 GRASBRUNN 

Bretonischer Ring 4 
Neukeferloh Technopar.k 
Tel.: (49-89) 460060 
Telex: 52821 1 
Telefax: (49-89) 4605454 
Teletex: 8971 07=STDISTR 

3000 HANNOVER 1 

Eckenerstrasse 5 
Tel. (49-51 1)634191 
Telex 175118418 
Teletex: 5118418 csfbeh 
Telefax: (49-511) 633552 

8500 NURNBERG 20 

Erlenstegenstrasse, 72 
Tel.: (49-911) 597032 
Telex: 626243 
Telefax: (49-911) 5980701 

5200 SIEGBURG 

Frankfurter Str. 22a 
Tel. (49-2241) 660 84-86 
Telex: 889510 
Telefax: (49-2241) 67584 

7000 STUTTGART 

Oberer Kirchhaldenweg 135 
Tel. (49-71 1)692041 
Telex: 721718 
Telefax: (49-711) 691408 



Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the 
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No 
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned 
in this publication are subject to change without notice. This publication supersedes and replaces all informations previously supplied. 
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express 
written approval of SGS-THOMSON Microelectronics. 

© 1990 SGS-THOMSON Microelectronics - Printed in Italy- All Rights Reserved 
TM-Z8000 is a trademark of Zilog Inc. 

SGS-THOMSON Microelectronics GROUP OF COMPANIES 

Australia - Brazil - China - France - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - 

Singapore - Spain - Sweden - Switzerland - Taiwan - United Kingdom - U.S.A. - West Germany 

AGC - GESSATE CMI) 




BELL INDUSTRIES 

Electronic Distribution Group 

1161 N. Fairoaks Avenue 

Sunnyvale, California 94089 

(408) 734-8570 

FAX NO. (408)734-8875